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X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?gL3pYZ0CQeyATs0d4WTMbJgOcufdMHcqmMh6nFfRkK44u9TCfhE3GU0xTRjs?= =?us-ascii?Q?oUIIx6x0tU6udVcOAZFGTS+KlNmVg1cWGOyaB5dbTs3DacCubCc6oklFRkBg?= =?us-ascii?Q?b1Mh/ABcdqGckrjCNN2EJ7PZy7PWYRP10swKT+GIlI6twfmYWs0Kj35VcOwD?= =?us-ascii?Q?ai4Nv9T/1L77p1nbm3JjKF4dkHEXtForIwpUnGlYjsRJ7QRQz27FzZbRAqB0?= =?us-ascii?Q?6vFQ0vLAO+udk5R5TxDpYXsMGLcHDmjGWM4JdzNxygs8f+92hVBL6+7kfC1M?= =?us-ascii?Q?JA6aLzoJRb8pmI3mqZaXSnESvlNF0YpHHd62rA+G8CWjlA3bm5vfJOFdbv3z?= =?us-ascii?Q?qC6MbEcGI+mWuteswS9Uwo5LmdIKSKwamku3WaZZiEMGib1HS9K4ergqzJx7?= =?us-ascii?Q?AXTGU6opFnZ9of3O4MStuXohdL5FhuIMj/vdptSmnfDLeCX5ofwj2AtBNoB0?= =?us-ascii?Q?45OPOZ0zm3Vnay/6O4PnrpDhQOZgj/HFHiDYNO6yRUrir7ugOoyJNsZ9PlDm?= =?us-ascii?Q?ftKSGFmXTefnX8fezf8AmjUSC2YGBPl4U2CJld7XGF5fJLMpNrkk2m/eIqK8?= =?us-ascii?Q?RtK1i7Tlgis2IFqsp/BgP4nDFxa6E4jEfsHANPJSFVSDaciejj9ZMziz4akM?= =?us-ascii?Q?VCgdXYbhfujaZ6k741BMpfpZ55W109HfaBTqh/jvzA+izmNLoSDClnKKkfCe?= =?us-ascii?Q?QpxQx+pEUbCzCRr0+xwwkGhf5EkXQimRwn10YC1/HZ/QNux56rYTm1TWxrYT?= =?us-ascii?Q?HuvTvTpKg3duWN2RtYZUSf5AO3e2vT4EiR1h0Z263Z65hGcuf3JzOWOz/8mJ?= =?us-ascii?Q?wadUZOuLR2m6q9FyC3OOGxiRlLEUJ+QkNoUk/zTG3+6/M5/6exxwLMuT0HH6?= =?us-ascii?Q?9jtw5UF/uQTQWKEMwaJ72QNCEkhtC6kp+FOCY7OZf62MF7NbeDE9R/z8Jl1z?= =?us-ascii?Q?kTr2NlyygvgzQ6UId3lVcwFz14J+IkbaNbIBuTZBiNyEeXHFCLcgjilHKwrm?= =?us-ascii?Q?LixjVQQ8kd2ivuX1zgT9Ruf45mksnFZMmXBqbs2DvnMnhx4JNGr45lBNeeiV?= =?us-ascii?Q?/szDysrbdujgPS/MJ23kS0Bg4TP4vOjGcO/SVJxLbZqIqbOcajmZJXL9booZ?= =?us-ascii?Q?HeCBCcmGRBS4eijc4boHstCSAdnEak1s98i/Uh/ma1Wbe+xV+uxdWQkGF5EM?= =?us-ascii?Q?8q4YcaYRxaIUJDxSi0RzgBxAxj2hyqFIgaR3YXXB/rm4x4yd/bylZhFUxMov?= =?us-ascii?Q?lvLkR33lnSEDIjPFs4HG3druO8I0GMbmZkhQKTVNdK6qgptwReBppzZxDEjF?= =?us-ascii?Q?QNHpPFGracmtTr7KOQcg1Gju?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 59867b5e-199e-40a2-7eca-08d9006340ed X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB3834.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2021 23:07:34.3512 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NIlUtknwzUiL97gu0eA/3qnGOpk4Cy5US4HRY+BlnaQtDufQf9OdRkTOCI2AwB86 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0105 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 15, 2021 at 03:11:19PM +0200, Auger Eric wrote: > Hi Jason, > > On 4/1/21 6:03 PM, Jason Gunthorpe wrote: > > On Thu, Apr 01, 2021 at 02:08:17PM +0000, Liu, Yi L wrote: > > > >> DMA page faults are delivered to root-complex via page request message and > >> it is per-device according to PCIe spec. Page request handling flow is: > >> > >> 1) iommu driver receives a page request from device > >> 2) iommu driver parses the page request message. Get the RID,PASID, faulted > >> page and requested permissions etc. > >> 3) iommu driver triggers fault handler registered by device driver with > >> iommu_report_device_fault() > > > > This seems confused. > > > > The PASID should define how to handle the page fault, not the driver. > > In my series I don't use PASID at all. I am just enabling nested stage > and the guest uses a single context. I don't allocate any user PASID at > any point. > > When there is a fault at physical level (a stage 1 fault that concerns > the guest), this latter needs to be reported and injected into the > guest. The vfio pci driver registers a fault handler to the iommu layer > and in that fault handler it fills a circ bugger and triggers an eventfd > that is listened to by the VFIO-PCI QEMU device. this latter retrives > the faault from the mmapped circ buffer, it knowns which vIOMMU it is > attached to, and passes the fault to the vIOMMU. > Then the vIOMMU triggers and IRQ in the guest. > > We are reusing the existing concepts from VFIO, region, IRQ to do that. > > For that use case, would you also use /dev/ioasid? /dev/ioasid could do all the things you described vfio-pci as doing, it can even do them the same way you just described. Stated another way, do you plan to duplicate all of this code someday for vfio-cxl? What about for vfio-platform? ARM SMMU can be hooked to platform devices, right? I feel what you guys are struggling with is some choice in the iommu kernel APIs that cause the events to be delivered to the pci_device owner, not the PASID owner. That feels solvable. Jason