From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 686B0C433ED for ; Wed, 21 Apr 2021 04:29:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 33A1F61415 for ; Wed, 21 Apr 2021 04:29:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235105AbhDUE3U (ORCPT ); Wed, 21 Apr 2021 00:29:20 -0400 Received: from new4-smtp.messagingengine.com ([66.111.4.230]:56291 "EHLO new4-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231575AbhDUE3K (ORCPT ); Wed, 21 Apr 2021 00:29:10 -0400 Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailnew.nyi.internal (Postfix) with ESMTP id 1F65C580E32; Wed, 21 Apr 2021 00:28:38 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Wed, 21 Apr 2021 00:28:38 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm2; bh=fzJUD2qGibX3T c+nSeqt20oBjnAxswijfmk5lfSvqdE=; b=PAlWGuyjfTPm5XghulgfXJEVSgVDi sL/Lta7mLPkuNY6C1tmaOEf+J9rtDeyRBkcAyoNyw1BCfnbsvTDqnehvMKgPaH0B phyPlkUNFkkDp12xFubgemFoTfkKHFhgCHLT5hfz9zvveoM7PUQp0qum28j2ivAo 1mmGvAnwabHa6gr5iK9G9wxYf7tYmmmW2YkLD4XVBT7KHZMqGN61zyiaf+kN7jQW 7ChncrGKq7GASa5BAkq4EvMY2H1olCMDHvyWWl/r520UAFWbw1+GSTrHBSYxPBJK s0sjwql2dKpNCBGXKfJB1VjOLjrVnYolzx7X5HJQLfX5LjAP6zsCVMXSg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=fzJUD2qGibX3Tc+nSeqt20oBjnAxswijfmk5lfSvqdE=; b=Z2wccEBK q6mdN1sC8RiySwRaBxWps2kZjp3suvDkFT3uR1KdKe6LHzdDD5JH5YJAuGp5y3BF CW+DhJYIobZueR56cTPmGguHgxPG+g8h6J01FOlyvuE1O5rwzLW8UBVdD0oLzFba tqJhWW4HkTVaBQWenTNLqolMO8hXJ7YVbxwIHcPPUwToL1RKK6ADOY5hukDt7jdY cQohPBHamno59yRpSa/lvqcmzfBviIn1QZ9AFyQGEfVuJirYM3ekzRXeq1vqb3Cl bi5JMUJhM3lTyQ6+Plsz6ij5DVW9oOhu8v/kbZlaR8RmJs9p2d2rGOtrtH3sd6Z7 47R2k9lu7+43Jg== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduledrvddtjedgkeduucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpeduhfejfedvhffgfeehtefghfeiiefgfeehgfdvvdevfeegjeehjedv gfejheeuieenucfkphepjedtrddufeehrddugeekrdduhedunecuvehluhhsthgvrhfuih iivgeptdenucfrrghrrghmpehmrghilhhfrhhomhepshgrmhhuvghlsehshhholhhlrghn ugdrohhrgh X-ME-Proxy: Received: from titanium.stl.sholland.net (70-135-148-151.lightspeed.stlsmo.sbcglobal.net [70.135.148.151]) by mail.messagingengine.com (Postfix) with ESMTPA id 8E273240067; Wed, 21 Apr 2021 00:28:36 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Andre Przywara , Greg Kroah-Hartman , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, Samuel Holland Subject: [PATCH 2/2] arm64: dts: allwinner: h6: Wrap DWC3 and PHY in glue layer Date: Tue, 20 Apr 2021 23:28:34 -0500 Message-Id: <20210421042834.27309-3-samuel@sholland.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210421042834.27309-1-samuel@sholland.org> References: <20210421042834.27309-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The USB3 IP in the H6 is organized such that the reset line affects both the DWC3 core and the PHY. To model that, following the example of several other platforms, wrap those nodes in a glue layer node. The inner nodes no longer need to be disabled, since the glue layer is disabled by default to keep it in reset. Signed-off-by: Samuel Holland --- .../dts/allwinner/sun50i-h6-beelink-gs1.dts | 6 +- .../dts/allwinner/sun50i-h6-orangepi-3.dts | 6 +- .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 9 ++- .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 6 +- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 60 ++++++++++--------- 5 files changed, 40 insertions(+), 47 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts index 0dde972324e7..5bab12d81468 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts @@ -86,10 +86,6 @@ &de { status = "okay"; }; -&dwc3 { - status = "okay"; -}; - &ehci0 { status = "okay"; }; @@ -333,6 +329,6 @@ &usb2phy { status = "okay"; }; -&usb3phy { +&usb3 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts index 38c48130f079..baff16caedb5 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -111,10 +111,6 @@ &de { status = "okay"; }; -&dwc3 { - status = "okay"; -}; - &ehci0 { status = "okay"; }; @@ -388,6 +384,6 @@ &usb2phy { status = "okay"; }; -&usb3phy { +&usb3 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts index 647669511381..fe4d74ade6e0 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts @@ -94,10 +94,6 @@ &de { status = "okay"; }; -&dwc3 { - status = "okay"; -}; - &ehci0 { status = "okay"; }; @@ -362,7 +358,10 @@ &usb2phy { status = "okay"; }; +&usb3 { + status = "okay"; +}; + &usb3phy { phy-supply = <®_usb_vbus>; - status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts index be81330db14f..8cb06df231ab 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts @@ -55,10 +55,6 @@ &de { status = "okay"; }; -&dwc3 { - status = "okay"; -}; - &ehci0 { status = "okay"; }; @@ -119,6 +115,6 @@ &usb2phy { status = "okay"; }; -&usb3phy { +&usb3 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 15b14ed566dc..c5eea8b50ef8 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -797,36 +797,42 @@ ohci0: usb@5101400 { status = "disabled"; }; - dwc3: usb@5200000 { - compatible = "snps,dwc3"; - reg = <0x05200000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_BUS_XHCI>, - <&ccu CLK_BUS_XHCI>, - <&rtc 0>; - clock-names = "ref", "bus_early", "suspend"; + usb3: usb@5200000 { + compatible = "allwinner,sun50i-h6-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; resets = <&ccu RST_BUS_XHCI>; - /* - * The datasheet of the chip doesn't declare the - * peripheral function, and there's no boards known - * to have a USB Type-B port routed to the port. - * In addition, no one has tested the peripheral - * function yet. - * So set the dr_mode to "host" in the DTSI file. - */ - dr_mode = "host"; - phys = <&usb3phy>; - phy-names = "usb3-phy"; status = "disabled"; - }; - usb3phy: phy@5210000 { - compatible = "allwinner,sun50i-h6-usb3-phy"; - reg = <0x5210000 0x10000>; - clocks = <&ccu CLK_USB_PHY1>; - resets = <&ccu RST_USB_PHY1>; - #phy-cells = <0>; - status = "disabled"; + dwc3: usb@5200000 { + compatible = "snps,dwc3"; + reg = <0x05200000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_XHCI>, + <&ccu CLK_BUS_XHCI>, + <&rtc 0>; + clock-names = "ref", "bus_early", "suspend"; + /* + * The datasheet of the chip doesn't declare the + * peripheral function, and there's no boards known + * to have a USB Type-B port routed to the port. + * In addition, no one has tested the peripheral + * function yet. + * So set the dr_mode to "host" in the DTSI file. + */ + dr_mode = "host"; + phys = <&usb3phy>; + phy-names = "usb3-phy"; + }; + + usb3phy: phy@5210000 { + compatible = "allwinner,sun50i-h6-usb3-phy"; + reg = <0x5210000 0x10000>; + clocks = <&ccu CLK_USB_PHY1>; + resets = <&ccu RST_USB_PHY1>; + #phy-cells = <0>; + }; }; ehci3: usb@5311000 { -- 2.26.3