From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF485C433ED for ; Thu, 22 Apr 2021 06:45:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9EF916144A for ; Thu, 22 Apr 2021 06:45:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234898AbhDVGpe (ORCPT ); Thu, 22 Apr 2021 02:45:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229547AbhDVGpb (ORCPT ); Thu, 22 Apr 2021 02:45:31 -0400 Received: from mail-qv1-xf4a.google.com (mail-qv1-xf4a.google.com [IPv6:2607:f8b0:4864:20::f4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B05AFC06174A for ; Wed, 21 Apr 2021 23:44:57 -0700 (PDT) Received: by mail-qv1-xf4a.google.com with SMTP id f7-20020a0562141d27b029019a6fd0a183so15225113qvd.23 for ; Wed, 21 Apr 2021 23:44:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:message-id:mime-version:subject:from:to:cc; bh=l+qKKt5CthNo7gsKeiDmyb/kZ1TcAtPvmD2Gk6Cbjnk=; b=b1iMBV9GjdZUYj2yI91PEybzTlsso3VQDe8xFMroa8ouR/ttvj3knfM95AcNp1o84N g3TViOskADOkMIRz01ZVq4DUjQZyZYMngikbAuJ1Osp/zLsc28t3HSQ2FpA3Ga3BsWKu rb2XTXvhd8z9TEDkexQdPsGGr/zaZNAV6mlSti35luArLtEty+Y9rHswJOSwg9ygNTBn 9XompmxpjhsB013aKMMkXTACZtH8PEBV7p+ZV1Z6tknsyI8DvVaQ5ujGbpl8USHDp0AC rCRYL7yckdt0n+qQPGJ5E8F2K6ndnfTtbd1GP0VFWMkO0OHeIaswtKYYuDFLF5XwBoce 3B2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=l+qKKt5CthNo7gsKeiDmyb/kZ1TcAtPvmD2Gk6Cbjnk=; b=m1Uja+50jmZu6z2z1oVd8g/sPiKNG7mKf5G93H6cU/b2bahEGJLrRCuZZV231pKLOt 14CAu70Z0JUBczkPojVKajZ0MACwhNSvNaxV8icbg/vcvQjnySsO1kaQK+b6nl4hPhY7 sokMH9eUHcLRlRUYWAQMPqoZr91500PIUUTkM13exyIj0acgCyN7YCHg2F/hGc/yjQS2 Oc1nSuA8mioJ+fnB4wbk2jixdDX9F7XxdGsI0qbEbkg6DerEG2rqJvWiy4uA7A7vylsX D70DGRbP8W8G7BAZaPR5K604/F1MFoCRvoPVo2v9V/XfP2QdB3vETvjR5YpMcidISBrZ V1Gw== X-Gm-Message-State: AOAM530a3QcDqLK0XWr70uqauMkoSCuFdEN6PsTYfj2r0YH3JaogaXbi 8hb4I3wvGgw8OfiiAUl2wGa6y/mbEw== X-Google-Smtp-Source: ABdhPJxKnTjrg7o9jl1LZdW4wy1+iae01OymOtOg+SLBRFzgbEQoqfWU08/k6ULzAeLc86G4rUyFprUPpg== X-Received: from elver.muc.corp.google.com ([2a00:79e0:15:13:6273:c89a:6562:e1ba]) (user=elver job=sendgmr) by 2002:a0c:f454:: with SMTP id h20mr1734578qvm.40.1619073896837; Wed, 21 Apr 2021 23:44:56 -0700 (PDT) Date: Thu, 22 Apr 2021 08:44:36 +0200 Message-Id: <20210422064437.3577327-1-elver@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.31.1.498.g6c1eba8ee3d-goog Subject: [PATCH tip 1/2] signal, perf: Fix siginfo_t by avoiding u64 on 32-bit architectures From: Marco Elver To: elver@google.com, peterz@infradead.org, mingo@redhat.com, tglx@linutronix.de Cc: m.szyprowski@samsung.com, jonathanh@nvidia.com, dvyukov@google.com, glider@google.com, arnd@arndb.de, christian@brauner.io, axboe@kernel.dk, pcc@google.com, oleg@redhat.com, kasan-dev@googlegroups.com, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On some architectures, like Arm, the alignment of a structure is that of its largest member. This means that there is no portable way to add 64-bit integers to siginfo_t on 32-bit architectures, because siginfo_t does not contain any 64-bit integers on 32-bit architectures. In the case of the si_perf field, word size is sufficient since there is no exact requirement on size, given the data it contains is user-defined via perf_event_attr::sig_data. On 32-bit architectures, any excess bits of perf_event_attr::sig_data will therefore be truncated when copying into si_perf. Since this field is intended to disambiguate events (e.g. encoding relevant information if there are more events of the same type), 32 bits should provide enough entropy to do so on 32-bit architectures. For 64-bit architectures, no change is intended. Fixes: fb6cc127e0b6 ("signal: Introduce TRAP_PERF si_code and si_perf to siginfo") Reported-by: Marek Szyprowski Tested-by: Marek Szyprowski Reported-by: Jon Hunter Signed-off-by: Marco Elver --- Note: I added static_assert()s to verify the siginfo_t layout to arch/arm and arch/arm64, which caught the problem. I'll send them separately to arm&arm64 maintainers respectively. --- include/linux/compat.h | 2 +- include/uapi/asm-generic/siginfo.h | 2 +- tools/testing/selftests/perf_events/sigtrap_threads.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/linux/compat.h b/include/linux/compat.h index c8821d966812..f0d2dd35d408 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -237,7 +237,7 @@ typedef struct compat_siginfo { u32 _pkey; } _addr_pkey; /* used when si_code=TRAP_PERF */ - compat_u64 _perf; + compat_ulong_t _perf; }; } _sigfault; diff --git a/include/uapi/asm-generic/siginfo.h b/include/uapi/asm-generic/siginfo.h index d0bb9125c853..03d6f6d2c1fe 100644 --- a/include/uapi/asm-generic/siginfo.h +++ b/include/uapi/asm-generic/siginfo.h @@ -92,7 +92,7 @@ union __sifields { __u32 _pkey; } _addr_pkey; /* used when si_code=TRAP_PERF */ - __u64 _perf; + unsigned long _perf; }; } _sigfault; diff --git a/tools/testing/selftests/perf_events/sigtrap_threads.c b/tools/testing/selftests/perf_events/sigtrap_threads.c index 9c0fd442da60..78ddf5e11625 100644 --- a/tools/testing/selftests/perf_events/sigtrap_threads.c +++ b/tools/testing/selftests/perf_events/sigtrap_threads.c @@ -44,7 +44,7 @@ static struct { } ctx; /* Unique value to check si_perf is correctly set from perf_event_attr::sig_data. */ -#define TEST_SIG_DATA(addr) (~(uint64_t)(addr)) +#define TEST_SIG_DATA(addr) (~(unsigned long)(addr)) static struct perf_event_attr make_event_attr(bool enabled, volatile void *addr) { -- 2.31.1.498.g6c1eba8ee3d-goog