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Fri, 23 Apr 2021 14:55:28 +0000 Received: from SDONTHINENI-DESKTOP.nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Apr 2021 14:55:26 +0000 From: Shanker Donthineni To: Bjorn Helgaas CC: , , Sinan Kaya , Vikram Sethi , Shanker Donthineni Subject: [PATCH 1/1] PCI: Add pci reset quirk for Nvidia GPUs Date: Fri, 23 Apr 2021 09:54:02 -0500 Message-ID: <20210423145402.14559-1-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8712a0da-26a1-4891-2e64-08d90667d571 X-MS-TrafficTypeDiagnostic: BN6PR12MB1330: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7xZy/jOBrfGAax489o2FkIWq1sWJRcxWJ4WLuhmtE71crNkqN9HbERBR5NaQlxhPmBxxsdOAwLaoDJL/UTyw3UC8yttf6G8VBlpYGZOhyHzmrrbCASRY3ZkBgqC9/Pqr4ul44M945v6+IeexuQzLvSKTYgbQ8tiFhL4Zn46t1j2yYDp7/ocwI+qQ7c3sNqFUXnwtCZlbTiZC8J3y0gjCQDPYmHjsqcP0QztCnqxTiMvTrO2hb2rn7p2unZgWlLhufnKEbb7IfoKdjYzp9ILM8P0pMxN/U8gPtqVnMzLzOnDSwIb2jSZ5t5eE0Yh+Fnw8wA+aPSsDGXEbcTVzLUqrrVKRwC7sZJ8naandD8aYH2Lgjarw7SmtGnKiG9CACIM+bxL2XFBtnlLXLMq2vAyIOv2PqDZVNn+NIDAxn/O7Yy9H/waTneCeDTSfF35MP+dhkAp+tPcFcIFfy/5Ykgdxk49YFGq/wDyVQLZe5kT0f4HpPS21m+X/Kp+h3b69M1BqZvDG8DO44yu9oTKd+e3jodPtZw0DkjBbMNranujhQ4pRpgqpLyKBZG4QGSZjJj2NbFjIL6eGfE1j4+APQZKaq64RDP2+fdmWIaDNkLNzMJyH9/FVQTNRp503SS2mgsMxLqOUydIrj3PsOZVIo4fIIqEyE6wEHsz/ecnd70FBH+Q= X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(39860400002)(396003)(136003)(346002)(376002)(46966006)(36840700001)(82740400003)(54906003)(70586007)(7636003)(70206006)(47076005)(7696005)(36860700001)(8676002)(4326008)(6916009)(16526019)(36756003)(5660300002)(86362001)(356005)(426003)(186003)(336012)(26005)(82310400003)(2906002)(83380400001)(6666004)(107886003)(316002)(1076003)(478600001)(36906005)(8936002)(2616005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2021 14:55:28.1048 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8712a0da-26a1-4891-2e64-08d90667d571 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1330 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On select platforms, some Nvidia GPU devices require platform-specific quirks around device reset, and these GPUs do not work with FLR/SBR. For these devices, add a quirk to handle the device reset in firmware. Platforms that need the device reset quirk expose the firmware reset method for the affected devices and the GPUs in these platforms have a unique device ID range. This reset issue will be fixed in the next generation of hardware. Signed-off-by: Shanker Donthineni --- drivers/pci/quirks.c | 54 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 653660e3ba9e..23fc90d209c2 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3913,6 +3913,59 @@ static int delay_250ms_after_flr(struct pci_dev *dev, int probe) return 0; } +/* + * Some Nvidia GPU devices do not work with bus reset, SBR needs to be + * prevented for those affected devices. + */ +static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) +{ + if ((dev->device & 0xffc0) == 0x2340) + dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, + quirk_nvidia_no_bus_reset); + +/* + * Some Nvidia GPU devices do not work with standard resets. These GPU + * devices are only in select systems and those systems have _RST method + * defined in the firmware. This quirk invokes a _RST() on the associated + * device to fix the reset issue. + */ +static int reset_nvidia_gpu_quirk(struct pci_dev *dev, int probe) +{ +#ifdef CONFIG_ACPI + acpi_handle handle = ACPI_HANDLE(&dev->dev); + + /* + * Check for the affected devices' ID range. If device is not in + * the affected range, return -ENOTTY indicating no device + * specific reset method is available. + */ + if ((dev->device & 0xffc0) != 0x2340) + return -ENOTTY; + + /* + * Return -ENOTTY indicating no device-specific reset method if _RST + * method is not defined + */ + if (!handle || !acpi_has_method(handle, "_RST")) + return -ENOTTY; + + /* Return 0 for probe phase indicating that we can reset this device */ + if (probe) + return 0; + + /* Invoke _RST() method to perform the device-specific reset */ + if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) { + pci_warn(dev, "Failed to reset the device\n"); + return -EINVAL; + } + return 0; +#else + return -ENOTTY; +#endif +} + static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, reset_intel_82599_sfp_virtfn }, @@ -3924,6 +3977,7 @@ static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, reset_chelsio_generic_dev }, + { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, reset_nvidia_gpu_quirk }, { 0 } }; -- 2.17.1