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From: Brijesh Singh <brijesh.singh@amd.com>
To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de,
	thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com,
	dave.hansen@intel.com, rientjes@google.com, seanjc@google.com,
	peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com,
	Brijesh Singh <brijesh.singh@amd.com>
Subject: [PATCH Part1 RFC v2 18/20] x86/boot: Add Confidential Computing address to setup_header
Date: Fri, 30 Apr 2021 07:16:14 -0500	[thread overview]
Message-ID: <20210430121616.2295-19-brijesh.singh@amd.com> (raw)
In-Reply-To: <20210430121616.2295-1-brijesh.singh@amd.com>

While launching the encrypted guests, the hypervisor may need to provide
some additional information that will used during the guest boot. In the
case of AMD SEV-SNP the information includes the address of the secrets
and CPUID pages. The secrets page contains information such as a VM to
PSP communication key, and CPUID page contain PSP filtered CPUID values.

When booting under the EFI based BIOS, the EFI configuration table
contains an entry for the confidential computing blob. In order to support
booting encrypted guests on non EFI VM, the hypervisor need to pass these
additional information to the kernel with different method.

For this purpose expand the struct setup_header to hold the physical
address of the confidential computing blob location. Being zero means it
isn't passed.

Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
---
 Documentation/x86/boot.rst            | 26 ++++++++++++++++++++++++++
 arch/x86/boot/header.S                |  7 ++++++-
 arch/x86/include/uapi/asm/bootparam.h |  1 +
 3 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/Documentation/x86/boot.rst b/Documentation/x86/boot.rst
index fc844913dece..f7c6c3204b40 100644
--- a/Documentation/x86/boot.rst
+++ b/Documentation/x86/boot.rst
@@ -75,6 +75,8 @@ Protocol 2.14	BURNT BY INCORRECT COMMIT
 		DO NOT USE!!! ASSUME SAME AS 2.13.
 
 Protocol 2.15	(Kernel 5.5) Added the kernel_info and kernel_info.setup_type_max.
+
+Protocol 2.16	(Kernel 5.14) Added the confidential computing blob address
 =============	============================================================
 
 .. note::
@@ -226,6 +228,7 @@ Offset/Size	Proto		Name			Meaning
 0260/4		2.10+		init_size		Linear memory required during initialization
 0264/4		2.11+		handover_offset		Offset of handover entry point
 0268/4		2.15+		kernel_info_offset	Offset of the kernel_info
+026C/4		2.16+		cc_blob_address	        Physical address of the confidential computing blob
 ===========	========	=====================	============================================
 
 .. note::
@@ -1026,6 +1029,29 @@ Offset/size:	0x000c/4
 
   This field contains maximal allowed type for setup_data and setup_indirect structs.
 
+============	==================
+Field name:	cc_blob_address
+Type:		write (optional)
+Offset/size:	0x26C/4
+Protocol:	2.16+
+============	==================
+
+  This field can be set by the boot loader to tell the kernel the physical address
+  of the confidential computing blob info.
+
+  A value of 0 indicates that either the blob is not provided or use the EFI configuration
+  table to retrieve the blob location.
+
+  In the case of AMD SEV the blob look like this::
+
+  struct cc_blob_sev_info {
+        u32 magic;      /* 0x414d4445 (AMDE) */
+        u16 version;
+        u32 secrets_phys; /* pointer to secrets page */
+        u32 secrets_len;
+        u64 cpuid_phys;   /* 32-bit pointer to cpuid page */
+        u32 cpuid_len;
+  }
 
 The Image Checksum
 ==================
diff --git a/arch/x86/boot/header.S b/arch/x86/boot/header.S
index 6dbd7e9f74c9..b4a014a18f91 100644
--- a/arch/x86/boot/header.S
+++ b/arch/x86/boot/header.S
@@ -303,7 +303,7 @@ _start:
 	# Part 2 of the header, from the old setup.S
 
 		.ascii	"HdrS"		# header signature
-		.word	0x020f		# header version number (>= 0x0105)
+		.word	0x0210		# header version number (>= 0x0105)
 					# or else old loadlin-1.5 will fail)
 		.globl realmode_swtch
 realmode_swtch:	.word	0, 0		# default_switch, SETUPSEG
@@ -577,6 +577,11 @@ pref_address:		.quad LOAD_PHYSICAL_ADDR	# preferred load addr
 init_size:		.long INIT_SIZE		# kernel initialization size
 handover_offset:	.long 0			# Filled in by build.c
 kernel_info_offset:	.long 0			# Filled in by build.c
+cc_blob_address:	.long 0			# (Header version 0x210 or later)
+						# If nonzero, a 32-bit pointer to
+						# the confidential computing blob.
+						# The blob will contain the information
+						# used while booting the encrypted VM.
 
 # End of setup header #####################################################
 
diff --git a/arch/x86/include/uapi/asm/bootparam.h b/arch/x86/include/uapi/asm/bootparam.h
index b25d3f82c2f3..210e1a0fb4ce 100644
--- a/arch/x86/include/uapi/asm/bootparam.h
+++ b/arch/x86/include/uapi/asm/bootparam.h
@@ -102,6 +102,7 @@ struct setup_header {
 	__u32	init_size;
 	__u32	handover_offset;
 	__u32	kernel_info_offset;
+	__u32	cc_blob_address;
 } __attribute__((packed));
 
 struct sys_desc_table {
-- 
2.17.1


  parent reply	other threads:[~2021-04-30 12:18 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-30 12:15 [PATCH Part1 RFC v2 00/20] Add AMD Secure Nested Paging (SEV-SNP) Guest Support Brijesh Singh
2021-04-30 12:15 ` [PATCH Part1 RFC v2 01/20] x86/sev: Define the GHCB MSR protocol for AP reset hold Brijesh Singh
2021-04-30 12:15 ` [PATCH Part1 RFC v2 02/20] x86/sev: Save the negotiated GHCB version Brijesh Singh
2021-05-11  9:23   ` Borislav Petkov
2021-05-11 18:29     ` Brijesh Singh
2021-05-11 18:41       ` Borislav Petkov
2021-05-12 14:03         ` Brijesh Singh
2021-05-12 14:31           ` Borislav Petkov
2021-05-12 15:03             ` Brijesh Singh
2021-04-30 12:15 ` [PATCH Part1 RFC v2 03/20] x86/sev: Add support for hypervisor feature VMGEXIT Brijesh Singh
2021-05-11 10:01   ` Borislav Petkov
2021-05-11 18:53     ` Brijesh Singh
2021-05-17 14:40       ` Borislav Petkov
2021-04-30 12:16 ` [PATCH Part1 RFC v2 04/20] x86/sev: Increase the GHCB protocol version Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 05/20] x86/sev: Define SNP Page State Change VMGEXIT structure Brijesh Singh
2021-05-18 10:41   ` Borislav Petkov
2021-05-18 15:06     ` Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 06/20] x86/sev: Define SNP guest request NAE events Brijesh Singh
2021-05-18 10:45   ` Borislav Petkov
2021-05-18 13:42     ` Brijesh Singh
2021-05-18 13:54       ` Borislav Petkov
2021-05-18 14:13         ` Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 07/20] x86/sev: Define error codes for reason set 1 Brijesh Singh
2021-05-18 11:05   ` Borislav Petkov
2021-04-30 12:16 ` [PATCH Part1 RFC v2 08/20] x86/mm: Add sev_snp_active() helper Brijesh Singh
2021-05-18 18:11   ` Borislav Petkov
2021-05-19 17:28     ` Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 09/20] x86/sev: check SEV-SNP features support Brijesh Singh
2021-05-20 16:02   ` Borislav Petkov
2021-05-20 17:40     ` Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 10/20] x86/sev: Add a helper for the PVALIDATE instruction Brijesh Singh
2021-04-30 13:05   ` Brijesh Singh
2021-05-20 17:32     ` Borislav Petkov
2021-05-20 17:44       ` Brijesh Singh
2021-05-20 17:51         ` Borislav Petkov
2021-05-20 17:57           ` Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 11/20] x86/compressed: Add helper for validating pages in the decompression stage Brijesh Singh
2021-05-20 17:52   ` Borislav Petkov
2021-05-20 18:05     ` Brijesh Singh
2021-05-25 10:18       ` Borislav Petkov
2021-04-30 12:16 ` [PATCH Part1 RFC v2 12/20] x86/compressed: Register GHCB memory when SEV-SNP is active Brijesh Singh
2021-05-25 10:41   ` Borislav Petkov
2021-04-30 12:16 ` [PATCH Part1 RFC v2 13/20] x86/sev: " Brijesh Singh
2021-05-25 11:11   ` Borislav Petkov
2021-05-25 14:28     ` Brijesh Singh
2021-05-25 14:35       ` Borislav Petkov
2021-05-25 14:47         ` Brijesh Singh
2021-05-26  9:57           ` Borislav Petkov
2021-05-26 13:23             ` Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 14/20] x86/sev: Add helper for validating pages in early enc attribute changes Brijesh Singh
2021-05-26 10:39   ` Borislav Petkov
2021-05-26 13:34     ` Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 15/20] x86/kernel: Make the bss.decrypted section shared in RMP table Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 16/20] x86/kernel: Validate rom memory before accessing when SEV-SNP is active Brijesh Singh
2021-05-27 11:49   ` Borislav Petkov
2021-05-27 12:12     ` Brijesh Singh
2021-05-27 12:23       ` Borislav Petkov
2021-05-27 12:56         ` Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 17/20] x86/mm: Add support to validate memory when changing C-bit Brijesh Singh
2021-04-30 12:16 ` Brijesh Singh [this message]
2021-04-30 12:16 ` [PATCH Part1 RFC v2 19/20] x86/sev: Register SNP guest request platform device Brijesh Singh
2021-04-30 12:16 ` [PATCH Part1 RFC v2 20/20] virt: Add SEV-SNP guest driver Brijesh Singh

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