From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07590C433ED for ; Tue, 4 May 2021 19:08:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E018A610E9 for ; Tue, 4 May 2021 19:08:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232443AbhEDTJE (ORCPT ); Tue, 4 May 2021 15:09:04 -0400 Received: from mga17.intel.com ([192.55.52.151]:38664 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232116AbhEDTIY (ORCPT ); Tue, 4 May 2021 15:08:24 -0400 IronPort-SDR: r4x4kS/cZ/nhe6qoXeNLU00cmc+2+LdEL7cifaOir6DehFN9bZcUiGZgvn1T9yf2UXCDngO4zl IN+GUQupTo+g== X-IronPort-AV: E=McAfee;i="6200,9189,9974"; a="178269915" X-IronPort-AV: E=Sophos;i="5.82,272,1613462400"; d="scan'208";a="178269915" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2021 12:07:18 -0700 IronPort-SDR: C8jKyzyJxmEiqdnxm50esgsms5hZVzaSXDJumriaTarr52BNXgJYgdsklsLRhuKESVcY8fbp+D 1xo5yPZhZQ+g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,272,1613462400"; d="scan'208";a="618591767" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga006.fm.intel.com with ESMTP; 04 May 2021 12:07:18 -0700 From: Ricardo Neri To: Thomas Gleixner , Ingo Molnar , Borislav Petkov Cc: "H. Peter Anvin" , Ashok Raj , Andi Kleen , Tony Luck , Nicholas Piggin , "Peter Zijlstra (Intel)" , Andrew Morton , Stephane Eranian , Suravee Suthikulpanit , "Ravi V. Shankar" , Ricardo Neri , x86@kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Andi Kleen Subject: [RFC PATCH v5 16/16] x86/tsc: Switch to perf-based hardlockup detector if TSC become unstable Date: Tue, 4 May 2021 12:05:26 -0700 Message-Id: <20210504190526.22347-17-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504190526.22347-1-ricardo.neri-calderon@linux.intel.com> References: <20210504190526.22347-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The HPET-based hardlockup detector relies on the TSC to determine if an observed NMI interrupt was originated by HPET timer. Hence, this detector can no longer be used with an unstable TSC. In such case, permanently stop the HPET-based hardlockup detector and start the perf-based detector. Add stub versions of hardlockup_detector_switch_to_perf() to be used when the HPET hardlockup detector and/or when CONFIG_HPET_TIMER are not selected. Cc: "H. Peter Anvin" Cc: Ashok Raj Cc: Andi Kleen Cc: Tony Luck Cc: Peter Zijlstra Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: x86@kernel.org Suggested-by: Thomas Gleixner Signed-off-by: Ricardo Neri --- Changes since v4: * Added a stub version of hardlockup_detector_switch_to_perf() for !CONFIG_HPET_TIMER. (lkp) * Reconfigure the whole lockup detector instead of unconditionally starting the perf-based hardlockup detector. Changes since v3: * None Changes since v2: * Introduced this patch. Changes since v1: * N/A --- arch/x86/include/asm/hpet.h | 3 +++ arch/x86/kernel/tsc.c | 2 ++ arch/x86/kernel/watchdog_hld.c | 6 ++++++ 3 files changed, 11 insertions(+) diff --git a/arch/x86/include/asm/hpet.h b/arch/x86/include/asm/hpet.h index 1ff7436c1ce6..df11c7d4af44 100644 --- a/arch/x86/include/asm/hpet.h +++ b/arch/x86/include/asm/hpet.h @@ -148,18 +148,21 @@ extern int hardlockup_detector_hpet_init(void); extern void hardlockup_detector_hpet_stop(void); extern void hardlockup_detector_hpet_enable(unsigned int cpu); extern void hardlockup_detector_hpet_disable(unsigned int cpu); +extern void hardlockup_detector_switch_to_perf(void); #else static inline int hardlockup_detector_hpet_init(void) { return -ENODEV; } static inline void hardlockup_detector_hpet_stop(void) {} static inline void hardlockup_detector_hpet_enable(unsigned int cpu) {} static inline void hardlockup_detector_hpet_disable(unsigned int cpu) {} +static inline void hardlockup_detector_switch_to_perf(void) {} #endif /* CONFIG_X86_HARDLOCKUP_DETECTOR_HPET */ #else /* CONFIG_HPET_TIMER */ static inline int hpet_enable(void) { return 0; } static inline int is_hpet_enabled(void) { return 0; } +static inline void hardlockup_detector_switch_to_perf(void) {} #define hpet_readl(a) 0 #define default_setup_hpet_msi NULL diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 57ec01192180..86ac13a83884 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -1174,6 +1174,8 @@ void mark_tsc_unstable(char *reason) clocksource_mark_unstable(&clocksource_tsc_early); clocksource_mark_unstable(&clocksource_tsc); + + hardlockup_detector_switch_to_perf(); } EXPORT_SYMBOL_GPL(mark_tsc_unstable); diff --git a/arch/x86/kernel/watchdog_hld.c b/arch/x86/kernel/watchdog_hld.c index 8947a7644421..a4415ad4aa85 100644 --- a/arch/x86/kernel/watchdog_hld.c +++ b/arch/x86/kernel/watchdog_hld.c @@ -78,3 +78,9 @@ void watchdog_nmi_stop(void) if (detector_type == X86_HARDLOCKUP_DETECTOR_HPET) hardlockup_detector_hpet_stop(); } + +void hardlockup_detector_switch_to_perf(void) +{ + detector_type = X86_HARDLOCKUP_DETECTOR_PERF; + lockup_detector_reconfigure(); +} -- 2.17.1