From: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
To: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de
Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
p.zabel@pengutronix.de, l.stach@pengutronix.de, krzk@kernel.org,
agx@sigxcpu.org, marex@denx.de, andrew.smirnov@gmail.com,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, ping.bai@nxp.com,
frieder.schrempf@kontron.de, aford173@gmail.com,
abel.vesa@nxp.com, Peng Fan <peng.fan@nxp.com>
Subject: [PATCH V2 07/13] soc: imx: gpcv2: allow domains without power-sequence control
Date: Thu, 6 May 2021 09:04:34 +0800 [thread overview]
Message-ID: <20210506010440.7016-8-peng.fan@oss.nxp.com> (raw)
In-Reply-To: <20210506010440.7016-1-peng.fan@oss.nxp.com>
From: Lucas Stach <l.stach@pengutronix.de>
Some of the PGC domains only control the handshake with the ADB400
and don't have any power sequence controls. Make such domains work
by allowing the pxx and map bits to be empty and skip all actions
using those controls.
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/soc/imx/gpcv2.c | 89 +++++++++++++++++++++++------------------
1 file changed, 49 insertions(+), 40 deletions(-)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index bfea8560cb64..0428f0eddee0 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -163,24 +163,27 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
goto out_regulator_disable;
}
- /* request the domain to power up */
- regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
- domain->bits.pxx, domain->bits.pxx);
- /*
- * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
- * for PUP_REQ/PDN_REQ bit to be cleared
- */
- ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
- reg_val, !(reg_val & domain->bits.pxx),
- 0, USEC_PER_MSEC);
- if (ret) {
- dev_err(domain->dev, "failed to command PGC\n");
- goto out_clk_disable;
- }
+ if (domain->bits.pxx) {
+ /* request the domain to power up */
+ regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
+ domain->bits.pxx, domain->bits.pxx);
+ /*
+ * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
+ * for PUP_REQ/PDN_REQ bit to be cleared
+ */
+ ret = regmap_read_poll_timeout(domain->regmap,
+ GPC_PU_PGC_SW_PUP_REQ, reg_val,
+ !(reg_val & domain->bits.pxx),
+ 0, USEC_PER_MSEC);
+ if (ret) {
+ dev_err(domain->dev, "failed to command PGC\n");
+ goto out_clk_disable;
+ }
- /* disable power control */
- regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
- GPC_PGC_CTRL_PCR);
+ /* disable power control */
+ regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
+ GPC_PGC_CTRL_PCR);
+ }
/* request the ADB400 to power up */
if (domain->bits.hskreq) {
@@ -245,23 +248,26 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
}
}
- /* enable power control */
- regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
- GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
-
- /* request the domain to power down */
- regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
- domain->bits.pxx, domain->bits.pxx);
- /*
- * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
- * for PUP_REQ/PDN_REQ bit to be cleared
- */
- ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
- reg_val, !(reg_val & domain->bits.pxx),
- 0, USEC_PER_MSEC);
- if (ret) {
- dev_err(domain->dev, "failed to command PGC\n");
- goto out_clk_disable;
+ if (domain->bits.pxx) {
+ /* enable power control */
+ regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
+ GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+
+ /* request the domain to power down */
+ regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
+ domain->bits.pxx, domain->bits.pxx);
+ /*
+ * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
+ * for PUP_REQ/PDN_REQ bit to be cleared
+ */
+ ret = regmap_read_poll_timeout(domain->regmap,
+ GPC_PU_PGC_SW_PDN_REQ, reg_val,
+ !(reg_val & domain->bits.pxx),
+ 0, USEC_PER_MSEC);
+ if (ret) {
+ dev_err(domain->dev, "failed to command PGC\n");
+ goto out_clk_disable;
+ }
}
/* Disable reset clocks for all devices in the domain */
@@ -536,8 +542,9 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
pm_runtime_enable(domain->dev);
- regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
- domain->bits.map, domain->bits.map);
+ if (domain->bits.map)
+ regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, domain->bits.map);
ret = pm_genpd_init(&domain->genpd, NULL, true);
if (ret) {
@@ -557,8 +564,9 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
out_genpd_remove:
pm_genpd_remove(&domain->genpd);
out_domain_unmap:
- regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
- domain->bits.map, 0);
+ if (domain->bits.map)
+ regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, 0);
pm_runtime_disable(domain->dev);
return ret;
@@ -571,8 +579,9 @@ static int imx_pgc_domain_remove(struct platform_device *pdev)
of_genpd_del_provider(domain->dev->of_node);
pm_genpd_remove(&domain->genpd);
- regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
- domain->bits.map, 0);
+ if (domain->bits.map)
+ regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, 0);
pm_runtime_disable(domain->dev);
--
2.30.0
next prev parent reply other threads:[~2021-05-06 0:33 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-06 1:04 [PATCH V2 00/13] soc: imx: gpcv2: support i.MX8MM Peng Fan (OSS)
2021-05-06 1:04 ` [PATCH V2 01/13] soc: imx: gpcv2: move to more ideomatic error handling in probe Peng Fan (OSS)
2021-05-06 1:04 ` [PATCH V2 02/13] soc: imx: gpcv2: move domain mapping to domain driver probe Peng Fan (OSS)
2021-05-06 1:04 ` [PATCH V2 03/13] soc: imx: gpcv2: switch to clk_bulk_* API Peng Fan (OSS)
2021-05-06 6:30 ` Frieder Schrempf
2021-05-06 1:04 ` [PATCH V2 04/13] soc: imx: gpcv2: split power up and power down sequence control Peng Fan (OSS)
2021-05-06 6:36 ` Frieder Schrempf
2021-05-06 1:04 ` [PATCH V2 05/13] soc: imx: gpcv2: wait for ADB400 handshake Peng Fan (OSS)
2021-05-06 1:04 ` [PATCH V2 06/13] soc: imx: gpcv2: add runtime PM support for power-domains Peng Fan (OSS)
2021-05-06 1:04 ` Peng Fan (OSS) [this message]
2021-05-06 1:04 ` [PATCH V2 08/13] dt-bindings: imx: gpcv2: add support for optional resets Peng Fan (OSS)
2021-05-06 6:43 ` Frieder Schrempf
2021-05-07 21:16 ` Rob Herring
2021-05-08 0:50 ` Peng Fan
2021-05-06 1:04 ` [PATCH V2 09/13] soc: " Peng Fan (OSS)
2021-05-06 1:04 ` [PATCH V2 10/13] dt-bindings: power: add defines for i.MX8MM power domains Peng Fan (OSS)
2021-05-06 1:04 ` [PATCH V2 11/13] soc: imx: gpcv2: add support " Peng Fan (OSS)
2021-05-06 1:04 ` [PATCH V2 12/13] soc: imx: gpcv2: Add support for missing i.MX8MM VPU/DISPMIX " Peng Fan (OSS)
2021-05-06 1:04 ` [PATCH V2 13/13] soc: imx: gpcv2: move reset assert after requesting domain power up Peng Fan (OSS)
2021-05-06 6:56 ` Frieder Schrempf
2021-05-06 8:32 ` [PATCH V2 00/13] soc: imx: gpcv2: support i.MX8MM Frieder Schrempf
2021-05-19 16:09 ` Frieder Schrempf
2021-05-20 15:16 ` Frieder Schrempf
2021-07-21 20:51 ` Lucas Stach
2021-07-22 6:36 ` Frieder Schrempf
2021-08-04 14:30 ` Ezequiel Garcia
2021-08-09 8:15 ` Lucas Stach
2021-09-03 12:26 ` Benjamin Gaignard
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