From: "Pali Rohár" <pali@kernel.org>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Rob Herring <robh@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: "Russell King" <rmk+kernel@armlinux.org.uk>,
"Marek Behún" <kabel@kernel.org>,
"Remi Pommarel" <repk@triplefau.lt>, Xogium <contact@xogium.me>,
"Tomasz Maciej Nowak" <tmn505@gmail.com>,
"Marc Zyngier" <maz@kernel.org>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 38/42] PCI: aardvark: Cleanup some register macros
Date: Thu, 6 May 2021 17:31:49 +0200 [thread overview]
Message-ID: <20210506153153.30454-39-pali@kernel.org> (raw)
In-Reply-To: <20210506153153.30454-1-pali@kernel.org>
Define SPEED_GEN_* macros with correct PCIE_GEN_SEL_SHIFT.
Simplify macro for setting root complex mode (use BIT instead of
MSK+SHIFT).
Rename PCIE_MSG_PM_PME_MASK to PCIE_ISR0_MSG_PM_PME to match existing
naming convention, rename PCIE_ISR0_MSI_INT_PENDING to PCIE_ISR0_MSI_INT as
it is used for both interrupt mask and pending bit.
Change the code which disables strict ordering by doing it explicitly
(instead of not specifying *_STRICT_ORDER_ENABLE macro, specify bitwise
negation of that macro).
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <kabel@kernel.org>
---
drivers/pci/controller/pci-aardvark.c | 34 +++++++++++++--------------
1 file changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 2258b9ae1084..3c18e139b095 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -63,11 +63,10 @@
#define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
#define PCIE_GEN_SEL_MSK 0x3
#define PCIE_GEN_SEL_SHIFT 0x0
-#define SPEED_GEN_1 0
-#define SPEED_GEN_2 1
-#define SPEED_GEN_3 2
-#define IS_RC_MSK 1
-#define IS_RC_SHIFT 2
+#define SPEED_GEN_1 (0 << PCIE_GEN_SEL_SHIFT)
+#define SPEED_GEN_2 (1 << PCIE_GEN_SEL_SHIFT)
+#define SPEED_GEN_3 (2 << PCIE_GEN_SEL_SHIFT)
+#define IS_RC BIT(2)
#define LANE_CNT_MSK 0x18
#define LANE_CNT_SHIFT 0x3
#define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
@@ -91,15 +90,15 @@
#define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1)
#define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30)
#define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
-#define PCIE_MSG_PM_PME_MASK BIT(7)
#define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
-#define PCIE_ISR0_MSI_INT_PENDING BIT(24)
+#define PCIE_ISR0_MSG_PM_PME BIT(7)
#define PCIE_ISR0_CORR_ERR BIT(11)
#define PCIE_ISR0_NFAT_ERR BIT(12)
#define PCIE_ISR0_FAT_ERR BIT(13)
#define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
#define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
-#define PCIE_ISR0_ALL_MASK GENMASK(26, 0)
+#define PCIE_ISR0_MSI_INT BIT(24)
+#define PCIE_ISR0_ALL_MASK GENMASK(26, 0)
#define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
#define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
#define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
@@ -345,7 +344,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
/* Set PCI global control register to RC mode */
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
- reg |= (IS_RC_MSK << IS_RC_SHIFT);
+ reg |= IS_RC;
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
/*
@@ -379,8 +378,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
/* Program PCIe Control 2 to disable strict ordering */
- reg = PCIE_CORE_CTRL2_RESERVED |
- PCIE_CORE_CTRL2_TD_ENABLE;
+ reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
+ reg &= ~PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE;
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
/* Set lane X1 */
@@ -412,7 +411,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
/* Unmask summary MSI interrupt */
reg = advk_readl(pcie, PCIE_ISR0_MASK_REG);
- reg &= ~PCIE_ISR0_MSI_INT_PENDING;
+ reg &= ~PCIE_ISR0_MSI_INT;
advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
/* Unmask bits for ERR interrupt */
@@ -422,7 +421,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
/* Unmask PME interrupt for processing of PME requester */
reg = advk_readl(pcie, PCIE_ISR0_MASK_REG);
- reg &= ~PCIE_MSG_PM_PME_MASK;
+ reg &= ~PCIE_ISR0_MSG_PM_PME;
advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
/* Enable summary interrupt for GIC SPI source */
@@ -1265,8 +1264,7 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
generic_handle_irq(virq);
}
- advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
- PCIE_ISR0_REG);
+ advk_writel(pcie, PCIE_ISR0_MSI_INT, PCIE_ISR0_REG);
}
static void advk_pcie_handle_int(struct advk_pcie *pcie)
@@ -1290,8 +1288,8 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie)
return;
/* Process PME interrupt as the first one to do not miss PME requester id */
- if (isr0_status & PCIE_MSG_PM_PME_MASK) {
- advk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG);
+ if (isr0_status & PCIE_ISR0_MSG_PM_PME) {
+ advk_writel(pcie, PCIE_ISR0_MSG_PM_PME, PCIE_ISR0_REG);
/*
* PCIE_MSG_LOG_REG contains the last inbound message,
* so store requester id only when PME was not asserted yet.
@@ -1326,7 +1324,7 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie)
}
/* Process MSI interrupts */
- if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
+ if (isr0_status & PCIE_ISR0_MSI_INT)
advk_pcie_handle_msi(pcie);
/* Process legacy interrupts */
--
2.20.1
next prev parent reply other threads:[~2021-05-06 15:37 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-06 15:31 [PATCH 00/42] PCI: aardvark: Various driver fixes Pali Rohár
2021-05-06 15:31 ` [PATCH 01/42] PCI: aardvark: Fix kernel panic during PIO transfer Pali Rohár
2021-05-19 8:06 ` Pali Rohár
2021-05-06 15:31 ` [PATCH 02/42] PCI: aardvark: Fix checking for PIO Non-posted Request Pali Rohár
2021-05-06 15:31 ` [PATCH 03/42] PCI: aardvark: Fix checking for PIO status Pali Rohár
2021-05-06 15:31 ` [PATCH 04/42] PCI: aardvark: Increase polling delay to 1.5s while waiting for PIO response Pali Rohár
2021-05-06 15:31 ` [PATCH 05/42] PCI: pci-bridge-emul: Add PCIe Root Capabilities Register Pali Rohár
2021-05-06 23:10 ` Bjorn Helgaas
2021-05-07 14:40 ` Pali Rohár
2021-05-07 16:41 ` Bjorn Helgaas
2021-05-06 15:31 ` [PATCH 06/42] PCI: aardvark: Fix reporting CRS Software Visibility on emulated bridge Pali Rohár
2021-05-07 13:03 ` Bjorn Helgaas
2021-05-07 15:25 ` Pali Rohár
2021-05-07 15:33 ` Pali Rohár
2021-05-06 15:31 ` [PATCH 07/42] PCI: aardvark: Fix link training Pali Rohár
2021-05-06 15:31 ` [PATCH 08/42] PCI: Add PCI_EXP_DEVCTL_PAYLOAD_* macros Pali Rohár
2021-05-06 15:31 ` [PATCH 09/42] PCI: aardvark: Fix PCIe Max Payload Size setting Pali Rohár
2021-05-06 15:31 ` [PATCH 10/42] PCI: aardvark: Implement workaround for the readback value of VEND_ID Pali Rohár
2021-05-06 15:31 ` [PATCH 11/42] PCI: aardvark: Do not touch status bits of masked interrupts in interrupt handler Pali Rohár
2021-05-06 15:31 ` [PATCH 12/42] PCI: aardvark: Check for virq mapping when processing INTx IRQ Pali Rohár
2021-05-07 9:15 ` Marc Zyngier
2021-06-04 16:24 ` Pali Rohár
2021-06-04 16:29 ` Marc Zyngier
2021-05-06 15:31 ` [PATCH 13/42] PCI: aardvark: Remove irq_mask_ack callback for INTx interrupts Pali Rohár
2021-05-07 9:16 ` Marc Zyngier
2021-05-06 15:31 ` [PATCH 14/42] PCI: aardvark: Don't mask irq when mapping Pali Rohár
2021-05-07 9:20 ` Marc Zyngier
2021-05-07 9:27 ` Pali Rohár
2021-05-06 15:31 ` [PATCH 15/42] PCI: aardvark: Change name of INTx irq_chip to advk-INT Pali Rohár
2021-05-07 9:08 ` Marc Zyngier
2021-05-24 14:36 ` Marek Behún
2021-05-24 15:14 ` Marc Zyngier
2021-05-06 15:31 ` [PATCH 16/42] PCI: aardvark: Remove unneeded goto Pali Rohár
2021-05-06 15:31 ` [PATCH 17/42] PCI: aardvark: Fix support for MSI interrupts Pali Rohár
2021-05-07 10:16 ` Marc Zyngier
2021-05-07 14:44 ` Pali Rohár
2021-05-07 16:24 ` Marc Zyngier
2021-06-04 16:02 ` Pali Rohár
2021-06-04 16:22 ` Marc Zyngier
2021-05-06 15:31 ` [PATCH 18/42] PCI: aardvark: Correctly clear and unmask all " Pali Rohár
2021-05-07 10:19 ` Marc Zyngier
2021-05-07 10:21 ` Pali Rohár
2021-05-06 15:31 ` [PATCH 19/42] PCI: aardvark: Fix setting MSI address Pali Rohár
2021-05-07 10:25 ` Marc Zyngier
2021-05-06 15:31 ` [PATCH 20/42] PCI: aardvark: Add support for more than 32 MSI interrupts Pali Rohár
2021-07-02 21:35 ` Pali Rohár
2021-05-06 15:31 ` [PATCH 21/42] PCI: aardvark: Add support for masking " Pali Rohár
2021-05-06 15:31 ` [PATCH 22/42] PCI: aardvark: Enable MSI-X support Pali Rohár
2021-05-06 15:31 ` [PATCH 23/42] PCI: aardvark: Fix support for ERR interrupt on emulated bridge Pali Rohár
2021-05-06 15:31 ` [PATCH 24/42] PCI: aardvark: Fix support for PME " Pali Rohár
2021-05-06 15:31 ` [PATCH 25/42] PCI: aardvark: Fix support for PME requester " Pali Rohár
2021-05-06 15:31 ` [PATCH 26/42] PCI: aardvark: Fix support for bus mastering and PCI_COMMAND " Pali Rohár
2021-05-06 15:31 ` [PATCH 27/42] PCI: aardvark: Disable bus mastering and mask all interrupts when unbinding driver Pali Rohár
2021-05-06 15:31 ` [PATCH 28/42] PCI: aardvark: Free config space for emulated root bridge when unbinding driver to fix memory leak Pali Rohár
2021-05-06 15:31 ` [PATCH 29/42] PCI: aardvark: Reset PCIe card and disable PHY when unbinding driver Pali Rohár
2021-05-06 15:31 ` [PATCH 30/42] PCI: aardvark: Rewrite irq code to chained irq handler Pali Rohár
2021-05-06 15:31 ` [PATCH 31/42] PCI: aardvark: Use separate INTA interrupt for emulated root bridge Pali Rohár
2021-05-06 15:31 ` [PATCH 32/42] PCI: pci-bridge-emul: Add description for class_revision field Pali Rohár
2021-05-06 15:31 ` [PATCH 33/42] PCI: pci-bridge-emul: Add definitions for missing capabilities registers Pali Rohár
2021-05-06 15:31 ` [PATCH 34/42] PCI: aardvark: Add support for DEVCAP2, DEVCTL2, LNKCAP2 and LNKCTL2 registers on emulated bridge Pali Rohár
2021-05-06 15:31 ` [PATCH 35/42] PCI: aardvark: Add support for PCI_BRIDGE_CTL_BUS_RESET " Pali Rohár
2021-05-06 15:31 ` [PATCH 36/42] PCI: aardvark: Replace custom PCIE_CORE_ERR_CAPCTL_* macros by linux/pci_regs.h macros Pali Rohár
2021-05-06 15:31 ` [PATCH 37/42] PCI: aardvark: Replace custom PCIE_CORE_INT_* macros by linux PCI_INTERRUPT_* values Pali Rohár
2021-05-06 15:31 ` Pali Rohár [this message]
2021-05-06 15:31 ` [PATCH 39/42] PCI: aardvark: Add comments for OB_WIN_ENABLE and ADDR_WIN_DISABLE Pali Rohár
2021-05-06 15:31 ` [PATCH 40/42] PCI: pci-bridge-emul: re-arrange register tests Pali Rohár
2021-05-06 15:31 ` [PATCH 41/42] PCI: pci-bridge-emul: add support for PCIe extended capabilities Pali Rohár
2021-05-06 15:31 ` [PATCH 42/42] PCI: aardvark: Add support for Advanced Error Reporting registers on emulated bridge Pali Rohár
2021-06-03 15:16 ` [PATCH 00/42] PCI: aardvark: Various driver fixes Lorenzo Pieralisi
2021-06-03 17:02 ` Pali Rohár
2021-06-03 18:02 ` Simon Glass
2021-06-03 18:18 ` Pali Rohár
2021-06-04 14:05 ` Lorenzo Pieralisi
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