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Fri, 7 May 2021 19:28:12 +0000 Received: from DM6PR12MB3834.namprd12.prod.outlook.com ([fe80::ddb4:2cbb:4589:f039]) by DM6PR12MB3834.namprd12.prod.outlook.com ([fe80::ddb4:2cbb:4589:f039%4]) with mapi id 15.20.4108.030; Fri, 7 May 2021 19:28:12 +0000 Date: Fri, 7 May 2021 16:28:10 -0300 From: Jason Gunthorpe To: "Raj, Ashok" Cc: Jean-Philippe Brucker , Jacob Pan , "Tian, Kevin" , Alex Williamson , "Liu, Yi L" , Auger Eric , LKML , Joerg Roedel , Lu Baolu , David Woodhouse , "iommu@lists.linux-foundation.org" , "cgroups@vger.kernel.org" , Tejun Heo , Johannes Weiner , Jean-Philippe Brucker , Jonathan Corbet , "Wu, Hao" , "Jiang, Dave" Subject: Re: [PATCH V4 05/18] iommu/ioasid: Redefine IOASID set and allocation APIs Message-ID: <20210507192810.GY1370958@nvidia.com> References: <20210505102259.044cafdf@jacob-builder> <20210505180023.GJ1370958@nvidia.com> <20210505130446.3ee2fccd@jacob-builder> <20210506122730.GQ1370958@nvidia.com> <20210506163240.GA9058@otc-nc-03> <20210507172051.GW1370958@nvidia.com> <20210507181458.GA73499@otc-nc-03> <20210507182050.GX1370958@nvidia.com> <20210507192325.GB73499@otc-nc-03> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?Vtp4aIVhOAWmEiX0SSTXp55uPZSXsiHs+gM9SPjGLroWwJhfFb+HRePpltFJ?= =?us-ascii?Q?QslbXDwNRIYkQ4n4Ca4u2vvL6Q9BWuiMhuzWxf1raY/E+wGUnEI+SCM2YhWB?= =?us-ascii?Q?EBKlbON8k0dq7J0hJrXN5BimIApd0QA9IxweaRwG3qrhrAQaW5E45syNClMt?= =?us-ascii?Q?KuHQb5zzXocbJT5nMZRbSXOLaSEQv/kSj9rOXkjXXNPQh/o6EnaiQkuAVTfT?= =?us-ascii?Q?X8Ti8XA+rW0N2UWwJwznXcmI4FsGEA22sXJTwgv731S4xFixf3417HBdX/xs?= =?us-ascii?Q?Lj5aUT4kj1i1FmCFjBMzWRBG8FUam/h+Z/5idtzNsF7Qs0nitYOIA0R4cHE8?= =?us-ascii?Q?akpLPvDcb4aBvChW50cx4bQyma+9srw73FSnF+7UtqVeeD7IJ9XITPZQc/CQ?= =?us-ascii?Q?7LKDi4Bvn4i7E+za3XzuLUPZ3MG3vWap+lECzDivIKw5HdK8LjJQa/Z5M/zR?= =?us-ascii?Q?TzG5q1zrXC3hfCOPnUtT+KbUh6I2u8yt9UTAXbl72PFfCIA6DMjAkgEwtt0v?= =?us-ascii?Q?SPTIw4QVwPlHmjSkswLs6uruN0sYX5PSFQx4eAENnGiu8oZYa2PZZtQvdVG/?= =?us-ascii?Q?TmeIVe3HKB5KagdfACYv95XsuUt1BOt2fzguqw9IdG+qyJiXA0q6UfZClRvi?= =?us-ascii?Q?zrsx8ChJ4jgXoboMUMU5s5CFBoqcpbz+qU/GaChFrpqjFe8asf2NLGx8wjCH?= =?us-ascii?Q?kDbPRcr5FEgdBURQuSiyElQrUnfF8dklCsEhyOspDUC+jCH9nHqZPRwUB7DV?= =?us-ascii?Q?CcodetZtpGeepVX+95ivlPqGVYTxEIcr+fmtVu/+i3erOViRYQRWoLWSO2Oe?= =?us-ascii?Q?ZJfcyKjRrSgkxrAqkvf2XFFvs9ORkjfOMmovAEWvq2PUzfYxd0pCLSze/KoS?= =?us-ascii?Q?HEV2uxpbnntxN4SFdYvSetMbUQKsSiCo/kGY9K66xoUsOIUPvyGR3HOuTEg7?= =?us-ascii?Q?NVICsM9d/1oAoSd7dq15gjGvjiTdKM4XpwfAjRoeBeQu1Drr5Ll2TehkY9+B?= =?us-ascii?Q?0bjoUDeZKqHdPBOX7FX+odVlbdc3oOPRrjDwpKTkoCh3ws2h4Uo2m+Xfxlhu?= =?us-ascii?Q?0A56LyigvYlCPwEnCSg+M4a8uSbYx0bjRT3VHq1ZPPbXHsDABVWds/yAv8f3?= =?us-ascii?Q?quFeCE0f7dVNCBLDvp9qd6EP728QrqGJBVOnt5Cif3Jyl+o9aUzijXtD/NTL?= =?us-ascii?Q?qzXxUBdU9g/fZ6lX8RojX5aFB5uYSQBH6Dt1tBrKEZNUji4M8rvaEkLHgB5E?= =?us-ascii?Q?vf6MCoQnGN6VG/CzPhxYjHoJBIyd5QfBYD8uaeSwGOn6xx66am3qbilbvMFz?= =?us-ascii?Q?oZdl8290DlaYv7+AcOGtPLsf?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: e2b14d74-5b47-4bfe-c929-08d9118e4102 X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB3834.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 May 2021 19:28:12.5414 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +BdXthI7zn7/+L5/Q/PzlDfmAw25mnHtixpmvcIQ5DdIWmFW9eyjNtx0zqAeAK3z X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4042 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, May 07, 2021 at 12:23:25PM -0700, Raj, Ashok wrote: > Hi Jason > > - Removed lizefan's email due to bounces... > > On Fri, May 07, 2021 at 03:20:50PM -0300, Jason Gunthorpe wrote: > > On Fri, May 07, 2021 at 11:14:58AM -0700, Raj, Ashok wrote: > > > On Fri, May 07, 2021 at 02:20:51PM -0300, Jason Gunthorpe wrote: > > > > On Thu, May 06, 2021 at 09:32:40AM -0700, Raj, Ashok wrote: > > > > > > > > > For platforms that support ENQCMD, it is required to mandate PASIDs are > > > > > global across the entire system. Maybe its better to call them gPASID for > > > > > guest and hPASID for host. Short reason being gPASID->hPASID is a guest > > > > > wide mapping for ENQCMD and not a per-RID based mapping. (We covered that > > > > > in earlier responses) > > > > > > > > I don't think it is actually ENQCMD that forces this, ENQCMD can use a > > > > per-RID PASID in the translation table as well. > > > > > > When using ENQCMD the PASID that needs to be sent on the wire is picked > > > from an MSR setup by kernel. This is context switched along with the > > > process. So each process has only 1 PASID that can go out when using > > > ENQCMD. ENQCMD takes one mmio address specific to the acclerator and a > > > source for the descriptor. > > > > Oh. I forgot this also globally locked the PASID to a single > > MSR. Sigh. That makes the whole mechanism useless for anything except > > whole process SVA. > > Is there another kind of SVA? Our mapping from that each process requires a > single mm, and PASID for SVM was a direct map from that. There are lots of potential applications for something like ENQCMD that are not whole process SVA. Linking it to a single PASID basically nukes any other use of it unfortunately. > > I would have to ask for a PASID that has the property it needs. You > > are saying the property is even bigger than "usable on a group of > > RIDs" but is actually "global for every RID and IOMMU in the system so > > it can go into a MSR". Gross, but fine, ask for that explicitly when > > allocating the PASID. > > If one process has a single mm, is that also gross? :-) So a single process > having a PASID is just an identifier for IOMMU. It just seems like what a > mm is for a process == PASID for SVM-IOMMU support. > > The unanswered question is how do we plumb from vIOMMU without a custom > allocator to get a system wide PASID? PASID allocation is part of the iommu driver, it really shouldn't be global. When the architecture code goes to allocate a single PASID for the mm_struct it should flag that allocation request with a 'must work for all RIDs flag' and the iommu driver should take care of it. That might mean the iommu driver consults a global static xarray, or maybe it does a hypercall, but it should be done through that API, not a side care global singleton. Jason