From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>,
Ben Widawsky <ben.widawsky@intel.com>,
<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-acpi@vger.kernel.org>
Subject: Re: [PATCH 6/8] cxl/Kconfig: Default drivers to CONFIG_CXL_BUS
Date: Mon, 10 May 2021 16:18:14 +0100 [thread overview]
Message-ID: <20210510161814.00007e99@Huawei.com> (raw)
In-Reply-To: <162042791307.1202325.2513845748708305095.stgit@dwillia2-desk3.amr.corp.intel.com>
On Fri, 7 May 2021 15:51:53 -0700
Dan Williams <dan.j.williams@intel.com> wrote:
> CONFIG_CXL_BUS is default 'n' as expected for new functionality. When
> that is enabled do not make the end user hunt for all the expected
> sub-options to enable. For example CONFIG_CXL_BUS without CONFIG_CXL_MEM
> is an odd/expert configuration, so is CONFIG_CXL_MEM without
> CONFIG_CXL_ACPI (on ACPI capable platforms). Default CONFIG_CXL_MEM and
> CONFIG_CXL_ACPI to CONFIG_CXL_BUS.
>
> Acked-by: Ben Widawsky <ben.widawsky@intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/Kconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
> index fb282af84afd..1da7970a5e55 100644
> --- a/drivers/cxl/Kconfig
> +++ b/drivers/cxl/Kconfig
> @@ -15,6 +15,7 @@ if CXL_BUS
>
> config CXL_MEM
> tristate "CXL.mem: Memory Devices"
> + default CXL_BUS
> help
> The CXL.mem protocol allows a device to act as a provider of
> "System RAM" and/or "Persistent Memory" that is fully coherent
> @@ -54,6 +55,7 @@ config CXL_MEM_RAW_COMMANDS
> config CXL_ACPI
> tristate "CXL ACPI: Platform Support"
> depends on ACPI
> + default CXL_BUS
> help
> Enable support for host managed device memory (HDM) resources
> published by a platform's ACPI CXL memory layout description.
>
next prev parent reply other threads:[~2021-05-10 15:21 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-07 22:51 [PATCH v3 0/8] CXL Port Enumeration and Plans for v5.14 Dan Williams
2021-05-07 22:51 ` [PATCH 1/8] cxl/mem: Move some definitions to mem.h Dan Williams
2021-05-10 15:14 ` Jonathan Cameron
2021-05-12 6:20 ` Dan Williams
2021-05-07 22:51 ` [PATCH 2/8] cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices Dan Williams
2021-05-10 15:17 ` Jonathan Cameron
2021-05-12 6:26 ` Dan Williams
2021-05-07 22:51 ` [PATCH 3/8] cxl/core: Rename bus.c to core.c Dan Williams
2021-05-10 15:17 ` Jonathan Cameron
2021-05-07 22:51 ` [PATCH 4/8] cxl/core: Refactor CXL register lookup for bridge reuse Dan Williams
2021-05-07 22:51 ` [PATCH 5/8] cxl/acpi: Introduce ACPI0017 driver and cxl_root Dan Williams
2021-05-10 14:56 ` Jonathan Cameron
2021-05-12 6:29 ` Dan Williams
2021-05-07 22:51 ` [PATCH 6/8] cxl/Kconfig: Default drivers to CONFIG_CXL_BUS Dan Williams
2021-05-10 15:18 ` Jonathan Cameron [this message]
2021-05-07 22:51 ` [PATCH 7/8] cxl/port: Introduce cxl_port objects Dan Williams
2021-05-08 2:24 ` kernel test robot
2021-05-10 15:21 ` Jonathan Cameron
2021-05-12 6:36 ` Dan Williams
2021-05-07 22:52 ` [PATCH 8/8] cxl/acpi: Add module parameters to stand in for ACPI tables Dan Williams
2021-05-10 17:22 ` [PATCH v3 0/8] CXL Port Enumeration and Plans for v5.14 Jonathan Cameron
2021-05-10 17:31 ` Dan Williams
-- strict thread matches above, loose matches on Subject: below --
2021-03-24 21:30 [PATCH 0/8] CXL Port Enumeration Dan Williams
2021-03-24 21:30 ` [PATCH 6/8] cxl/Kconfig: Default drivers to CONFIG_CXL_BUS Dan Williams
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