From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95C50C433ED for ; Sun, 16 May 2021 23:06:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 76DBB61186 for ; Sun, 16 May 2021 23:06:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234616AbhEPXH6 (ORCPT ); Sun, 16 May 2021 19:07:58 -0400 Received: from mx2.suse.de ([195.135.220.15]:44012 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232079AbhEPXHi (ORCPT ); Sun, 16 May 2021 19:07:38 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 04EC7B1FE; Sun, 16 May 2021 23:06:22 +0000 (UTC) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rob Herring , Heiko Stuebner , devicetree@vger.kernel.org Subject: [PATCH 9/9] arm64: dts: rockchip: rk1808: Add CPU operating points Date: Mon, 17 May 2021 01:05:51 +0200 Message-Id: <20210516230551.12469-10-afaerber@suse.de> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210516230551.12469-1-afaerber@suse.de> References: <20210516230551.12469-1-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Associate operating points with both CPU nodes. Data source is the shipping TB-RK1808M0 DTB. Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/rockchip/rk1808.dtsi | 64 ++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi index b4a71c5c8be7..82614c47f144 100644 --- a/arch/arm64/boot/dts/rockchip/rk1808.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk1808.dtsi @@ -32,7 +32,10 @@ cpu0: cpu@0 { compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; + dynamic-power-coefficient = <74>; + operating-points-v2 = <&cpu0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -40,6 +43,7 @@ cpu1: cpu@1 { compatible = "arm,cortex-a35"; reg = <0x0 0x1>; enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -57,6 +61,66 @@ CPU_SLEEP: cpu-sleep { }; }; + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <800000 800000 950000>; + clock-latency-ns = <40000>; + }; + + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <825000 825000 950000>; + clock-latency-ns = <40000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <850000 850000 950000>; + clock-latency-ns = <40000>; + }; + + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <875000 875000 950000>; + clock-latency-ns = <40000>; + }; + + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <900000 900000 950000>; + clock-latency-ns = <40000>; + }; + }; + arm-pmu { compatible = "arm,cortex-a35-pmu"; interrupts = , -- 2.31.1