From: abelvesa@kernel.org
To: Rob Herring <robh@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>, Jacky Bai <ping.bai@nxp.com>,
Dong Aisheng <aisheng.dong@nxp.com>
Cc: NXP Linux Team <linux-imx@nxp.com>,
devicetree@vger.kernel.org,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-arm-kernel@lists.infradead.org,
Abel Vesa <abel.vesa@nxp.com>
Subject: [PATCH 6/7] arm64: dts: freescale: Add lsio subsys dtsi for imx8dxl
Date: Mon, 17 May 2021 20:12:04 +0300 [thread overview]
Message-ID: <20210517171205.1581938-7-abelvesa@kernel.org> (raw)
In-Reply-To: <20210517171205.1581938-1-abelvesa@kernel.org>
From: Jacky Bai <ping.bai@nxp.com>
On i.MX8DXL, the LSIO subsystem includes below devices:
1x Inline Encryption Engine (IEE)
1x FlexSPI
4x Pulse Width Modulator (PWM)
5x General Purpose Timer (GPT)
8x GPIO
14x Message Unit (MU)
256KB On-Chip Memory (OCRAM)
compared to the common imx8-ss-lsio dtsi, some nodes' interrupt
property need to be updated.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
.../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 68 +++++++++++++++++++
1 file changed, 68 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
new file mode 100644
index 000000000000..7496a38694df
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+&lsio_gpio0 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio1 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio2 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio3 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio4 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio5 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio6 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio7 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu0 {
+ compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu1 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu2 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu3 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu4 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+};
--
2.31.1
next prev parent reply other threads:[~2021-05-17 17:12 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-17 17:11 [PATCH 0/7] arm64: dts: freescale: Add i.MX8DXL support abelvesa
2021-05-17 17:11 ` [PATCH 1/7] arm64: dts: freescale: Add the top level dtsi support for imx8dxl abelvesa
2021-05-18 7:35 ` Dong Aisheng
2021-06-02 9:29 ` Abel Vesa
2021-05-17 17:12 ` [PATCH 2/7] arm64: dts: imx8-ss-lsio: Add mu5a mailbox abelvesa
2021-05-18 7:50 ` Dong Aisheng
2021-06-02 9:48 ` Abel Vesa
2021-05-17 17:12 ` [PATCH 3/7] arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl abelvesa
2021-05-18 7:52 ` Dong Aisheng
2021-06-02 11:28 ` Abel Vesa
2021-05-17 17:12 ` [PATCH 4/7] arm64: dts: freescale: Add the imx8dxl connectivity subsys dtsi abelvesa
2021-05-18 7:53 ` Dong Aisheng
2021-05-17 17:12 ` [PATCH 5/7] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl abelvesa
2021-05-18 7:54 ` Dong Aisheng
2021-05-17 17:12 ` abelvesa [this message]
2021-05-18 7:55 ` [PATCH 6/7] arm64: dts: freescale: Add lsio " Dong Aisheng
2021-05-17 17:12 ` [PATCH 7/7] arm64: dts: imx8dxl: Add i.MX8DXL evk board support abelvesa
2021-05-18 7:57 ` Dong Aisheng
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210517171205.1581938-7-abelvesa@kernel.org \
--to=abelvesa@kernel.org \
--cc=abel.vesa@nxp.com \
--cc=aisheng.dong@nxp.com \
--cc=devicetree@vger.kernel.org \
--cc=festevam@gmail.com \
--cc=kernel@pengutronix.de \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-imx@nxp.com \
--cc=linux-kernel@vger.kernel.org \
--cc=ping.bai@nxp.com \
--cc=robh@kernel.org \
--cc=shawnguo@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).