From: Roger Lu <roger.lu@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Enric Balletbo Serra <eballetbo@gmail.com>,
Kevin Hilman <khilman@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Nicolas Boichat <drinkcat@google.com>,
Stephen Boyd <sboyd@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: Fan Chen <fan.chen@mediatek.com>,
HenryC Chen <HenryC.Chen@mediatek.com>,
YT Lee <yt.lee@mediatek.com>,
Xiaoqing Liu <Xiaoqing.Liu@mediatek.com>,
Charles Yang <Charles.Yang@mediatek.com>,
Angus Lin <Angus.Lin@mediatek.com>,
Mark Rutland <mark.rutland@arm.com>, Nishanth Menon <nm@ti.com>,
Roger Lu <roger.lu@mediatek.com>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-pm@vger.kernel.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Guenter Roeck <linux@roeck-us.net>
Subject: [PATCH v17 2/7] arm64: dts: mt8183: add svs device information
Date: Tue, 18 May 2021 13:18:43 +0800 [thread overview]
Message-ID: <20210518051848.22170-3-roger.lu@mediatek.com> (raw)
In-Reply-To: <20210518051848.22170-1-roger.lu@mediatek.com>
add compitable/reg/irq/clock/efuse setting in svs node
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 80519a145f13..441d617ece43 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -657,6 +657,18 @@
status = "disabled";
};
+ svs: svs@1100b000 {
+ compatible = "mediatek,mt8183-svs";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_THERM>;
+ clock-names = "main";
+ nvmem-cells = <&svs_calibration>,
+ <&thermal_calibration>;
+ nvmem-cell-names = "svs-calibration-data",
+ "t-calibration-data";
+ };
+
pwm0: pwm@1100e000 {
compatible = "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
@@ -941,9 +953,15 @@
reg = <0 0x11f10000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+ thermal_calibration: calib@180 {
+ reg = <0x180 0xc>;
+ };
mipi_tx_calibration: calib@190 {
reg = <0x190 0xc>;
};
+ svs_calibration: calib@580 {
+ reg = <0x580 0x64>;
+ };
};
u3phy: usb-phy@11f40000 {
--
2.18.0
next prev parent reply other threads:[~2021-05-18 5:18 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-18 5:18 [PATCH v17 0/7] soc: mediatek: SVS: introduce MTK SVS Roger Lu
2021-05-18 5:18 ` [PATCH v17 1/7] dt-bindings: soc: mediatek: add mtk svs dt-bindings Roger Lu
2021-05-18 5:18 ` Roger Lu [this message]
2021-05-18 5:18 ` [PATCH v17 3/7] soc: mediatek: SVS: introduce MTK SVS engine Roger Lu
2021-05-18 5:18 ` [PATCH v17 4/7] soc: mediatek: SVS: add debug commands Roger Lu
2021-05-18 5:18 ` [PATCH v17 5/7] dt-bindings: soc: mediatek: add mt8192 svs dt-bindings Roger Lu
2021-05-18 5:18 ` [PATCH v17 6/7] arm64: dts: mt8192: add svs device information Roger Lu
2021-05-18 5:18 ` [PATCH v17 7/7] soc: mediatek: SVS: add mt8192 SVS GPU driver Roger Lu
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