From: Shradha Todi <shradha.t@samsung.com>
To: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lorenzo.pieralisi@arm.com, robh@kernel.org, bhelgaas@google.com,
pankaj.dubey@samsung.com, p.rajanbabu@samsung.com,
hari.tv@samsung.com, niyas.ahmed@samsung.com,
l.mehra@samsung.com, Shradha Todi <shradha.t@samsung.com>
Subject: [PATCH 0/3] Add support for RAS DES feature in PCIe DW controller
Date: Tue, 18 May 2021 23:16:15 +0530 [thread overview]
Message-ID: <20210518174618.42089-1-shradha.t@samsung.com> (raw)
In-Reply-To: CGME20210518173814epcas5p46b312c35e11c130a6a8d043f10d12ee4@epcas5p4.samsung.com
DesignWare controller provides a vendor specific extended capability called
RASDES as an IP feature. This extended capability provides hardware
information like:
- Debug registers to know the state of the link or controller.
- Error injection mechanisms to inject various PCIe errors
including sequence number, CRC
- Statistical counters to know how many times a particular event occurred
However, in Linux we do not have any generic or custom support to be able to
use this feature in an efficient manner. This is the reason we are proposing
this framework. Debug and bring up time of high-speed IPs are highly dependent
on costlier hardware analyzers and this solution will in some ways help to
reduce the HW analyzer usage.
The debugfs entries can be used to get information about underlying hardware
and can be shared with user space. Separate debugfs entries has been created to
cater to all the DES hooks provided by the controller. The debugfs entries
interacts with the RASDES registers in the required sequence and provides the
meaningful data to the user. This eases the effort to understand and use the
register information for debugging.
Shradha Todi (3):
PCI: dwc: Add support for vendor specific capability search
PCI: debugfs: Add support for RAS framework in DWC
PCI: dwc: Create debugfs files in DWC driver
drivers/pci/controller/dwc/Kconfig | 9 +
drivers/pci/controller/dwc/Makefile | 1 +
.../controller/dwc/pcie-designware-debugfs.c | 544 ++++++++++++++++++
.../controller/dwc/pcie-designware-debugfs.h | 133 +++++
drivers/pci/controller/dwc/pcie-designware.c | 21 +
drivers/pci/controller/dwc/pcie-designware.h | 5 +
6 files changed, 713 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pcie-designware-debugfs.c
create mode 100644 drivers/pci/controller/dwc/pcie-designware-debugfs.h
--
2.17.1
next parent reply other threads:[~2021-05-19 3:53 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20210518173814epcas5p46b312c35e11c130a6a8d043f10d12ee4@epcas5p4.samsung.com>
2021-05-18 17:46 ` Shradha Todi [this message]
[not found] ` <CGME20210518173819epcas5p1ea10c2748b4bb0687184ff04a7a76796@epcas5p1.samsung.com>
2021-05-18 17:46 ` [PATCH 1/3] PCI: dwc: Add support for vendor specific capability search Shradha Todi
2021-05-21 23:31 ` Krzysztof Wilczyński
2021-05-27 11:49 ` Vidya Sagar
2021-05-27 11:54 ` Vidya Sagar
[not found] ` <CGME20210518173823epcas5p1cb9f93e209ca4055365048287ec43ee8@epcas5p1.samsung.com>
2021-05-18 17:46 ` [PATCH 2/3] PCI: debugfs: Add support for RAS framework in DWC Shradha Todi
2021-05-21 19:57 ` Bjorn Helgaas
2021-05-21 23:25 ` Krzysztof Wilczyński
2021-05-27 17:20 ` Vidya Sagar
[not found] ` <CGME20210518173826epcas5p32f6b141c9ab4b33e88638cf90a502ef1@epcas5p3.samsung.com>
2021-05-18 17:46 ` [PATCH 3/3] PCI: dwc: Create debugfs files in DWC driver Shradha Todi
2021-05-21 20:04 ` Bjorn Helgaas
2021-05-27 11:53 ` Vidya Sagar
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