* [PATCH v3 01/17] dt-bindings: qcom-bam: Convert binding to YAML
2021-05-19 14:36 [PATCH v3 00/17] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
@ 2021-05-19 14:36 ` Bhupesh Sharma
2021-05-21 1:43 ` Rob Herring
2021-05-21 8:08 ` Stephan Gerhold
2021-05-19 14:36 ` [PATCH v3 02/17] dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties Bhupesh Sharma
` (16 subsequent siblings)
17 siblings, 2 replies; 37+ messages in thread
From: Bhupesh Sharma @ 2021-05-19 14:36 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
Convert Qualcomm BAM DMA devicetree binding to YAML.
Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: dmaengine@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: bhupesh.linux@gmail.com
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 50 ----------
.../devicetree/bindings/dma/qcom_bam_dma.yaml | 91 +++++++++++++++++++
2 files changed, 91 insertions(+), 50 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
deleted file mode 100644
index cf5b9e44432c..000000000000
--- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-QCOM BAM DMA controller
-
-Required properties:
-- compatible: must be one of the following:
- * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084
- * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960
- * "qcom,bam-v1.7.0" for MSM8916
-- reg: Address range for DMA registers
-- interrupts: Should contain the one interrupt shared by all channels
-- #dma-cells: must be <1>, the cell in the dmas property of the client device
- represents the channel number
-- clocks: required clock
-- clock-names: must contain "bam_clk" entry
-- qcom,ee : indicates the active Execution Environment identifier (0-7) used in
- the secure world.
-- qcom,controlled-remotely : optional, indicates that the bam is controlled by
- remote proccessor i.e. execution environment.
-- num-channels : optional, indicates supported number of DMA channels in a
- remotely controlled bam.
-- qcom,num-ees : optional, indicates supported number of Execution Environments
- in a remotely controlled bam.
-
-Example:
-
- uart-bam: dma@f9984000 = {
- compatible = "qcom,bam-v1.4.0";
- reg = <0xf9984000 0x15000>;
- interrupts = <0 94 0>;
- clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
- clock-names = "bam_clk";
- #dma-cells = <1>;
- qcom,ee = <0>;
- };
-
-DMA clients must use the format described in the dma.txt file, using a two cell
-specifier for each channel.
-
-Example:
- serial@f991e000 {
- compatible = "qcom,msm-uart";
- reg = <0xf991e000 0x1000>
- <0xf9944000 0x19000>;
- interrupts = <0 108 0>;
- clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
- <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
-
- dmas = <&uart-bam 0>, <&uart-bam 1>;
- dma-names = "rx", "tx";
- };
diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
new file mode 100644
index 000000000000..173e4d7508a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/qcom_bam_dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: QCOM BAM DMA controller binding
+
+maintainers:
+ - Bhupesh Sharma <bhupesh.sharma@linaro.org>
+
+description: |
+ This document defines the binding for the BAM DMA controller
+ found on Qualcomm parts.
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - qcom,bam-v1.4.0
+ - qcom,bam-v1.3.0
+ - qcom,bam-v1.7.0
+
+ reg:
+ maxItems: 1
+ description: Address range of the DMA registers.
+
+ clocks:
+ minItems: 1
+ maxItems: 8
+
+ clock-names:
+ const: bam_clk
+
+ interrupts:
+ maxItems: 1
+ description: Single interrupt line shared by all channels.
+
+ num-channels:
+ maxItems: 31
+ description: |
+ Indicates supported number of DMA channels in a remotely controlled bam.
+
+ "#dma-cells":
+ const: 1
+ description: The single cell represents the channel index.
+
+ qcom,ee:
+ $ref: /schemas/types.yaml#/definitions/uint8
+ description:
+ Indicates the active Execution Environment identifier (0-7)
+ used in the secure world.
+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
+
+ qcom,controlled-remotely:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Indicates that the bam is controlled by remote proccessor i.e.
+ execution environment.
+
+ qcom,num-ees:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Indicates supported number of Execution Environments in a
+ remotely controlled bam.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - "#dma-cells"
+ - qcom,ee
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-msm8974.h>
+ dma-controller@f9984000 {
+ compatible = "qcom,bam-v1.4.0";
+ reg = <0xf9984000 0x15000>;
+ interrupts = <0 94 0>;
+ clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = /bits/ 8 <0>;
+ };
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v3 01/17] dt-bindings: qcom-bam: Convert binding to YAML
2021-05-19 14:36 ` [PATCH v3 01/17] dt-bindings: qcom-bam: Convert binding to YAML Bhupesh Sharma
@ 2021-05-21 1:43 ` Rob Herring
2021-06-04 3:27 ` Bhupesh Sharma
2021-05-21 8:08 ` Stephan Gerhold
1 sibling, 1 reply; 37+ messages in thread
From: Rob Herring @ 2021-05-21 1:43 UTC (permalink / raw)
To: Bhupesh Sharma
Cc: linux-arm-msm, Thara Gopinath, Bjorn Andersson, Andy Gross,
Herbert Xu, David S . Miller, Stephen Boyd, Michael Turquette,
Vinod Koul, dmaengine, linux-clk, linux-crypto, devicetree,
linux-kernel, bhupesh.linux
On Wed, May 19, 2021 at 08:06:44PM +0530, Bhupesh Sharma wrote:
> Convert Qualcomm BAM DMA devicetree binding to YAML.
>
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Herbert Xu <herbert@gondor.apana.org.au>
> Cc: David S. Miller <davem@davemloft.net>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: dmaengine@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-crypto@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: bhupesh.linux@gmail.com
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
> .../devicetree/bindings/dma/qcom_bam_dma.txt | 50 ----------
> .../devicetree/bindings/dma/qcom_bam_dma.yaml | 91 +++++++++++++++++++
> 2 files changed, 91 insertions(+), 50 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
>
> diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> deleted file mode 100644
> index cf5b9e44432c..000000000000
> --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> +++ /dev/null
> @@ -1,50 +0,0 @@
> -QCOM BAM DMA controller
> -
> -Required properties:
> -- compatible: must be one of the following:
> - * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084
> - * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960
> - * "qcom,bam-v1.7.0" for MSM8916
> -- reg: Address range for DMA registers
> -- interrupts: Should contain the one interrupt shared by all channels
> -- #dma-cells: must be <1>, the cell in the dmas property of the client device
> - represents the channel number
> -- clocks: required clock
> -- clock-names: must contain "bam_clk" entry
> -- qcom,ee : indicates the active Execution Environment identifier (0-7) used in
> - the secure world.
> -- qcom,controlled-remotely : optional, indicates that the bam is controlled by
> - remote proccessor i.e. execution environment.
> -- num-channels : optional, indicates supported number of DMA channels in a
> - remotely controlled bam.
> -- qcom,num-ees : optional, indicates supported number of Execution Environments
> - in a remotely controlled bam.
> -
> -Example:
> -
> - uart-bam: dma@f9984000 = {
> - compatible = "qcom,bam-v1.4.0";
> - reg = <0xf9984000 0x15000>;
> - interrupts = <0 94 0>;
> - clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
> - clock-names = "bam_clk";
> - #dma-cells = <1>;
> - qcom,ee = <0>;
> - };
> -
> -DMA clients must use the format described in the dma.txt file, using a two cell
> -specifier for each channel.
> -
> -Example:
> - serial@f991e000 {
> - compatible = "qcom,msm-uart";
> - reg = <0xf991e000 0x1000>
> - <0xf9944000 0x19000>;
> - interrupts = <0 108 0>;
> - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
> - <&gcc GCC_BLSP1_AHB_CLK>;
> - clock-names = "core", "iface";
> -
> - dmas = <&uart-bam 0>, <&uart-bam 1>;
> - dma-names = "rx", "tx";
> - };
> diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> new file mode 100644
> index 000000000000..173e4d7508a6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> @@ -0,0 +1,91 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/qcom_bam_dma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: QCOM BAM DMA controller binding
> +
> +maintainers:
> + - Bhupesh Sharma <bhupesh.sharma@linaro.org>
> +
> +description: |
> + This document defines the binding for the BAM DMA controller
> + found on Qualcomm parts.
> +
> +allOf:
> + - $ref: "dma-controller.yaml#"
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,bam-v1.4.0
> + - qcom,bam-v1.3.0
> + - qcom,bam-v1.7.0
Can we keep the SoC association please.
> +
> + reg:
> + maxItems: 1
> + description: Address range of the DMA registers.
Drop description.
> +
> + clocks:
> + minItems: 1
> + maxItems: 8
> +
> + clock-names:
> + const: bam_clk
This is going to fail if you try more than 1 clock.
> +
> + interrupts:
> + maxItems: 1
> + description: Single interrupt line shared by all channels.
Drop description
> +
> + num-channels:
> + maxItems: 31
> + description: |
> + Indicates supported number of DMA channels in a remotely controlled bam.
> +
> + "#dma-cells":
> + const: 1
> + description: The single cell represents the channel index.
> +
> + qcom,ee:
> + $ref: /schemas/types.yaml#/definitions/uint8
> + description:
> + Indicates the active Execution Environment identifier (0-7)
> + used in the secure world.
> + enum: [0, 1, 2, 3, 4, 5, 6, 7]
> +
> + qcom,controlled-remotely:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + Indicates that the bam is controlled by remote proccessor i.e.
> + execution environment.
> +
> + qcom,num-ees:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Indicates supported number of Execution Environments in a
> + remotely controlled bam.
0-2^32 is valid?
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - "#dma-cells"
> + - qcom,ee
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-msm8974.h>
> + dma-controller@f9984000 {
> + compatible = "qcom,bam-v1.4.0";
> + reg = <0xf9984000 0x15000>;
> + interrupts = <0 94 0>;
> + clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
> + clock-names = "bam_clk";
> + #dma-cells = <1>;
> + qcom,ee = /bits/ 8 <0>;
> + };
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH v3 01/17] dt-bindings: qcom-bam: Convert binding to YAML
2021-05-21 1:43 ` Rob Herring
@ 2021-06-04 3:27 ` Bhupesh Sharma
2021-07-29 19:34 ` Rob Herring
0 siblings, 1 reply; 37+ messages in thread
From: Bhupesh Sharma @ 2021-06-04 3:27 UTC (permalink / raw)
To: Rob Herring
Cc: linux-arm-msm, Thara Gopinath, Bjorn Andersson, Andy Gross,
Herbert Xu, David S . Miller, Stephen Boyd, Michael Turquette,
Vinod Koul, dmaengine, linux-clk, linux-crypto, devicetree,
linux-kernel, bhupesh.linux
Hello Rob,
Thanks for the review and sorry for the late reply.
On Fri, 21 May 2021 at 07:13, Rob Herring <robh@kernel.org> wrote:
>
> On Wed, May 19, 2021 at 08:06:44PM +0530, Bhupesh Sharma wrote:
> > Convert Qualcomm BAM DMA devicetree binding to YAML.
> >
> > Cc: Thara Gopinath <thara.gopinath@linaro.org>
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Andy Gross <agross@kernel.org>
> > Cc: Herbert Xu <herbert@gondor.apana.org.au>
> > Cc: David S. Miller <davem@davemloft.net>
> > Cc: Stephen Boyd <sboyd@kernel.org>
> > Cc: Michael Turquette <mturquette@baylibre.com>
> > Cc: Vinod Koul <vkoul@kernel.org>
> > Cc: dmaengine@vger.kernel.org
> > Cc: linux-clk@vger.kernel.org
> > Cc: linux-crypto@vger.kernel.org
> > Cc: devicetree@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> > Cc: bhupesh.linux@gmail.com
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> > .../devicetree/bindings/dma/qcom_bam_dma.txt | 50 ----------
> > .../devicetree/bindings/dma/qcom_bam_dma.yaml | 91 +++++++++++++++++++
> > 2 files changed, 91 insertions(+), 50 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> > create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> > deleted file mode 100644
> > index cf5b9e44432c..000000000000
> > --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> > +++ /dev/null
> > @@ -1,50 +0,0 @@
> > -QCOM BAM DMA controller
> > -
> > -Required properties:
> > -- compatible: must be one of the following:
> > - * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084
> > - * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960
> > - * "qcom,bam-v1.7.0" for MSM8916
> > -- reg: Address range for DMA registers
> > -- interrupts: Should contain the one interrupt shared by all channels
> > -- #dma-cells: must be <1>, the cell in the dmas property of the client device
> > - represents the channel number
> > -- clocks: required clock
> > -- clock-names: must contain "bam_clk" entry
> > -- qcom,ee : indicates the active Execution Environment identifier (0-7) used in
> > - the secure world.
> > -- qcom,controlled-remotely : optional, indicates that the bam is controlled by
> > - remote proccessor i.e. execution environment.
> > -- num-channels : optional, indicates supported number of DMA channels in a
> > - remotely controlled bam.
> > -- qcom,num-ees : optional, indicates supported number of Execution Environments
> > - in a remotely controlled bam.
> > -
> > -Example:
> > -
> > - uart-bam: dma@f9984000 = {
> > - compatible = "qcom,bam-v1.4.0";
> > - reg = <0xf9984000 0x15000>;
> > - interrupts = <0 94 0>;
> > - clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
> > - clock-names = "bam_clk";
> > - #dma-cells = <1>;
> > - qcom,ee = <0>;
> > - };
> > -
> > -DMA clients must use the format described in the dma.txt file, using a two cell
> > -specifier for each channel.
> > -
> > -Example:
> > - serial@f991e000 {
> > - compatible = "qcom,msm-uart";
> > - reg = <0xf991e000 0x1000>
> > - <0xf9944000 0x19000>;
> > - interrupts = <0 108 0>;
> > - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
> > - <&gcc GCC_BLSP1_AHB_CLK>;
> > - clock-names = "core", "iface";
> > -
> > - dmas = <&uart-bam 0>, <&uart-bam 1>;
> > - dma-names = "rx", "tx";
> > - };
> > diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> > new file mode 100644
> > index 000000000000..173e4d7508a6
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> > @@ -0,0 +1,91 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/dma/qcom_bam_dma.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: QCOM BAM DMA controller binding
> > +
> > +maintainers:
> > + - Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > +
> > +description: |
> > + This document defines the binding for the BAM DMA controller
> > + found on Qualcomm parts.
> > +
> > +allOf:
> > + - $ref: "dma-controller.yaml#"
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - qcom,bam-v1.4.0
> > + - qcom,bam-v1.3.0
> > + - qcom,bam-v1.7.0
>
> Can we keep the SoC association please.
The original bam dma bindings are as per the underlying bam IP
version, so I would prefer that we keep it this way for this series.
Later on I can send a patchset to convert the bam DMA dt-bindings, dts
and driver to work with 'SoC association' instead.
> > +
> > + reg:
> > + maxItems: 1
> > + description: Address range of the DMA registers.
>
> Drop description.
Sure.
> > +
> > + clocks:
> > + minItems: 1
> > + maxItems: 8
> > +
> > + clock-names:
> > + const: bam_clk
>
> This is going to fail if you try more than 1 clock.
Right, currently we have one clock, but I can recheck and make fixes in v4.
> > +
> > + interrupts:
> > + maxItems: 1
> > + description: Single interrupt line shared by all channels.
>
> Drop description
Ok.
> > +
> > + num-channels:
> > + maxItems: 31
> > + description: |
> > + Indicates supported number of DMA channels in a remotely controlled bam.
> > +
> > + "#dma-cells":
> > + const: 1
> > + description: The single cell represents the channel index.
> > +
> > + qcom,ee:
> > + $ref: /schemas/types.yaml#/definitions/uint8
> > + description:
> > + Indicates the active Execution Environment identifier (0-7)
> > + used in the secure world.
> > + enum: [0, 1, 2, 3, 4, 5, 6, 7]
> > +
> > + qcom,controlled-remotely:
> > + $ref: /schemas/types.yaml#/definitions/flag
> > + description:
> > + Indicates that the bam is controlled by remote proccessor i.e.
> > + execution environment.
> > +
> > + qcom,num-ees:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description:
> > + Indicates supported number of Execution Environments in a
> > + remotely controlled bam.
>
> 0-2^32 is valid?
Oh, got it. Will fix it in v4.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > + - clock-names
> > + - "#dma-cells"
> > + - qcom,ee
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/qcom,gcc-msm8974.h>
> > + dma-controller@f9984000 {
> > + compatible = "qcom,bam-v1.4.0";
> > + reg = <0xf9984000 0x15000>;
> > + interrupts = <0 94 0>;
> > + clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
> > + clock-names = "bam_clk";
> > + #dma-cells = <1>;
> > + qcom,ee = /bits/ 8 <0>;
> > + };
> > --
> > 2.31.1
Thanks,
Bhupesh
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH v3 01/17] dt-bindings: qcom-bam: Convert binding to YAML
2021-06-04 3:27 ` Bhupesh Sharma
@ 2021-07-29 19:34 ` Rob Herring
0 siblings, 0 replies; 37+ messages in thread
From: Rob Herring @ 2021-07-29 19:34 UTC (permalink / raw)
To: Bhupesh Sharma
Cc: linux-arm-msm, Thara Gopinath, Bjorn Andersson, Andy Gross,
Herbert Xu, David S . Miller, Stephen Boyd, Michael Turquette,
Vinod Koul, open list:DMA GENERIC OFFLOAD ENGINE SUBSYSTEM,
linux-clk, open list:HARDWARE RANDOM NUMBER GENERATOR CORE,
devicetree, linux-kernel, Bhupesh Sharma
On Thu, Jun 3, 2021 at 9:27 PM Bhupesh Sharma <bhupesh.sharma@linaro.org> wrote:
>
> Hello Rob,
>
> Thanks for the review and sorry for the late reply.
>
> On Fri, 21 May 2021 at 07:13, Rob Herring <robh@kernel.org> wrote:
> >
> > On Wed, May 19, 2021 at 08:06:44PM +0530, Bhupesh Sharma wrote:
> > > Convert Qualcomm BAM DMA devicetree binding to YAML.
> > >
> > > Cc: Thara Gopinath <thara.gopinath@linaro.org>
> > > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > > Cc: Rob Herring <robh+dt@kernel.org>
> > > Cc: Andy Gross <agross@kernel.org>
> > > Cc: Herbert Xu <herbert@gondor.apana.org.au>
> > > Cc: David S. Miller <davem@davemloft.net>
> > > Cc: Stephen Boyd <sboyd@kernel.org>
> > > Cc: Michael Turquette <mturquette@baylibre.com>
> > > Cc: Vinod Koul <vkoul@kernel.org>
> > > Cc: dmaengine@vger.kernel.org
> > > Cc: linux-clk@vger.kernel.org
> > > Cc: linux-crypto@vger.kernel.org
> > > Cc: devicetree@vger.kernel.org
> > > Cc: linux-kernel@vger.kernel.org
> > > Cc: bhupesh.linux@gmail.com
> > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > > ---
> > > .../devicetree/bindings/dma/qcom_bam_dma.txt | 50 ----------
> > > .../devicetree/bindings/dma/qcom_bam_dma.yaml | 91 +++++++++++++++++++
> > > 2 files changed, 91 insertions(+), 50 deletions(-)
> > > delete mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> > > create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> > > deleted file mode 100644
> > > index cf5b9e44432c..000000000000
> > > --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> > > +++ /dev/null
> > > @@ -1,50 +0,0 @@
> > > -QCOM BAM DMA controller
> > > -
> > > -Required properties:
> > > -- compatible: must be one of the following:
> > > - * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084
> > > - * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960
> > > - * "qcom,bam-v1.7.0" for MSM8916
> > > -- reg: Address range for DMA registers
> > > -- interrupts: Should contain the one interrupt shared by all channels
> > > -- #dma-cells: must be <1>, the cell in the dmas property of the client device
> > > - represents the channel number
> > > -- clocks: required clock
> > > -- clock-names: must contain "bam_clk" entry
> > > -- qcom,ee : indicates the active Execution Environment identifier (0-7) used in
> > > - the secure world.
> > > -- qcom,controlled-remotely : optional, indicates that the bam is controlled by
> > > - remote proccessor i.e. execution environment.
> > > -- num-channels : optional, indicates supported number of DMA channels in a
> > > - remotely controlled bam.
> > > -- qcom,num-ees : optional, indicates supported number of Execution Environments
> > > - in a remotely controlled bam.
> > > -
> > > -Example:
> > > -
> > > - uart-bam: dma@f9984000 = {
> > > - compatible = "qcom,bam-v1.4.0";
> > > - reg = <0xf9984000 0x15000>;
> > > - interrupts = <0 94 0>;
> > > - clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
> > > - clock-names = "bam_clk";
> > > - #dma-cells = <1>;
> > > - qcom,ee = <0>;
> > > - };
> > > -
> > > -DMA clients must use the format described in the dma.txt file, using a two cell
> > > -specifier for each channel.
> > > -
> > > -Example:
> > > - serial@f991e000 {
> > > - compatible = "qcom,msm-uart";
> > > - reg = <0xf991e000 0x1000>
> > > - <0xf9944000 0x19000>;
> > > - interrupts = <0 108 0>;
> > > - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
> > > - <&gcc GCC_BLSP1_AHB_CLK>;
> > > - clock-names = "core", "iface";
> > > -
> > > - dmas = <&uart-bam 0>, <&uart-bam 1>;
> > > - dma-names = "rx", "tx";
> > > - };
> > > diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> > > new file mode 100644
> > > index 000000000000..173e4d7508a6
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> > > @@ -0,0 +1,91 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/dma/qcom_bam_dma.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: QCOM BAM DMA controller binding
> > > +
> > > +maintainers:
> > > + - Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > > +
> > > +description: |
> > > + This document defines the binding for the BAM DMA controller
> > > + found on Qualcomm parts.
> > > +
> > > +allOf:
> > > + - $ref: "dma-controller.yaml#"
> > > +
> > > +properties:
> > > + compatible:
> > > + enum:
> > > + - qcom,bam-v1.4.0
> > > + - qcom,bam-v1.3.0
> > > + - qcom,bam-v1.7.0
> >
> > Can we keep the SoC association please.
>
> The original bam dma bindings are as per the underlying bam IP
> version, so I would prefer that we keep it this way for this series.
>
> Later on I can send a patchset to convert the bam DMA dt-bindings, dts
> and driver to work with 'SoC association' instead.
I just mean keep a comment with the mapping of versions to SoC:
> > > - * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084
> > > - * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960
> > > - * "qcom,bam-v1.7.0" for MSM8916
Otherwise, we are losing that information.
Rob
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v3 01/17] dt-bindings: qcom-bam: Convert binding to YAML
2021-05-19 14:36 ` [PATCH v3 01/17] dt-bindings: qcom-bam: Convert binding to YAML Bhupesh Sharma
2021-05-21 1:43 ` Rob Herring
@ 2021-05-21 8:08 ` Stephan Gerhold
2021-06-04 3:40 ` Bhupesh Sharma
1 sibling, 1 reply; 37+ messages in thread
From: Stephan Gerhold @ 2021-05-21 8:08 UTC (permalink / raw)
To: Bhupesh Sharma
Cc: linux-arm-msm, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
Hi,
On Wed, May 19, 2021 at 08:06:44PM +0530, Bhupesh Sharma wrote:
> Convert Qualcomm BAM DMA devicetree binding to YAML.
>
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Herbert Xu <herbert@gondor.apana.org.au>
> Cc: David S. Miller <davem@davemloft.net>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: dmaengine@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-crypto@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: bhupesh.linux@gmail.com
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
> .../devicetree/bindings/dma/qcom_bam_dma.txt | 50 ----------
> .../devicetree/bindings/dma/qcom_bam_dma.yaml | 91 +++++++++++++++++++
> 2 files changed, 91 insertions(+), 50 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
>
> diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> deleted file mode 100644
> index cf5b9e44432c..000000000000
> --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> +++ /dev/null
> @@ -1,50 +0,0 @@
> -QCOM BAM DMA controller
> -
> -Required properties:
> -- compatible: must be one of the following:
> - * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084
> - * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960
> - * "qcom,bam-v1.7.0" for MSM8916
> -- reg: Address range for DMA registers
> -- interrupts: Should contain the one interrupt shared by all channels
> -- #dma-cells: must be <1>, the cell in the dmas property of the client device
> - represents the channel number
> -- clocks: required clock
> -- clock-names: must contain "bam_clk" entry
> -- qcom,ee : indicates the active Execution Environment identifier (0-7) used in
> - the secure world.
> -- qcom,controlled-remotely : optional, indicates that the bam is controlled by
> - remote proccessor i.e. execution environment.
> -- num-channels : optional, indicates supported number of DMA channels in a
> - remotely controlled bam.
> -- qcom,num-ees : optional, indicates supported number of Execution Environments
> - in a remotely controlled bam.
> -
> -Example:
> -
> - uart-bam: dma@f9984000 = {
> - compatible = "qcom,bam-v1.4.0";
> - reg = <0xf9984000 0x15000>;
> - interrupts = <0 94 0>;
> - clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
> - clock-names = "bam_clk";
> - #dma-cells = <1>;
> - qcom,ee = <0>;
> - };
> -
> -DMA clients must use the format described in the dma.txt file, using a two cell
> -specifier for each channel.
> -
> -Example:
> - serial@f991e000 {
> - compatible = "qcom,msm-uart";
> - reg = <0xf991e000 0x1000>
> - <0xf9944000 0x19000>;
> - interrupts = <0 108 0>;
> - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
> - <&gcc GCC_BLSP1_AHB_CLK>;
> - clock-names = "core", "iface";
> -
> - dmas = <&uart-bam 0>, <&uart-bam 1>;
> - dma-names = "rx", "tx";
> - };
> diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> new file mode 100644
> index 000000000000..173e4d7508a6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> @@ -0,0 +1,91 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/qcom_bam_dma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: QCOM BAM DMA controller binding
> +
> +maintainers:
> + - Bhupesh Sharma <bhupesh.sharma@linaro.org>
> +
> +description: |
> + This document defines the binding for the BAM DMA controller
> + found on Qualcomm parts.
> +
> +allOf:
> + - $ref: "dma-controller.yaml#"
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,bam-v1.4.0
> + - qcom,bam-v1.3.0
> + - qcom,bam-v1.7.0
> +
> + reg:
> + maxItems: 1
> + description: Address range of the DMA registers.
> +
> + clocks:
> + minItems: 1
> + maxItems: 8
> +
> + clock-names:
> + const: bam_clk
> +
> + interrupts:
> + maxItems: 1
> + description: Single interrupt line shared by all channels.
> +
> + num-channels:
> + maxItems: 31
maxItems doesn't seem right here, since num-channels isn't an array.
Perhaps you meant maximum: 31?
Can you check your bindings on the existing device trees with
"make dtbs_check" and make sure that only reasonable errors remain?
This fails on pretty much every device tree:
arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: dma-controller@9184000: num-channels: [[31]] is too short
From schema: Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> + description: |
> + Indicates supported number of DMA channels in a remotely controlled bam.
> +
> + "#dma-cells":
> + const: 1
> + description: The single cell represents the channel index.
> +
> + qcom,ee:
> + $ref: /schemas/types.yaml#/definitions/uint8
> + description:
> + Indicates the active Execution Environment identifier (0-7)
> + used in the secure world.
> + enum: [0, 1, 2, 3, 4, 5, 6, 7]
> +
bam_dma.c reads this as uint32 and all existing device tree specify it
as uint32. I don't think adding the /bits/ 8 to all existing device
trees is really worth it.
arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: dma-controller@9184000: qcom,ee: missing size tag in [[1]]
From schema: Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> + qcom,controlled-remotely:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + Indicates that the bam is controlled by remote proccessor i.e.
> + execution environment.
> +
> + qcom,num-ees:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Indicates supported number of Execution Environments in a
> + remotely controlled bam.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
clocks is often missing if qcom,controlled-remotely is set, e.g.
slimbam: dma-controller@9184000 {
compatible = "qcom,bam-v1.7.0";
qcom,controlled-remotely;
reg = <0x09184000 0x32000>;
num-channels = <31>;
interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
qcom,ee = <1>;
qcom,num-ees = <2>;
};
arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: dma-controller@9184000: 'clocks' is a required property
From schema: Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: dma-controller@9184000: 'clock-names' is a required property
From schema: Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
You might be able to encode this with an if: statement (clocks required
if qcom,controlled-remotely not specified), not sure.
Stephan
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH v3 01/17] dt-bindings: qcom-bam: Convert binding to YAML
2021-05-21 8:08 ` Stephan Gerhold
@ 2021-06-04 3:40 ` Bhupesh Sharma
0 siblings, 0 replies; 37+ messages in thread
From: Bhupesh Sharma @ 2021-06-04 3:40 UTC (permalink / raw)
To: Stephan Gerhold
Cc: linux-arm-msm, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
Hi Stephan,
Thanks for the review.
On Fri, 21 May 2021 at 13:41, Stephan Gerhold <stephan@gerhold.net> wrote:
>
> Hi,
>
> On Wed, May 19, 2021 at 08:06:44PM +0530, Bhupesh Sharma wrote:
> > Convert Qualcomm BAM DMA devicetree binding to YAML.
> >
> > Cc: Thara Gopinath <thara.gopinath@linaro.org>
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Andy Gross <agross@kernel.org>
> > Cc: Herbert Xu <herbert@gondor.apana.org.au>
> > Cc: David S. Miller <davem@davemloft.net>
> > Cc: Stephen Boyd <sboyd@kernel.org>
> > Cc: Michael Turquette <mturquette@baylibre.com>
> > Cc: Vinod Koul <vkoul@kernel.org>
> > Cc: dmaengine@vger.kernel.org
> > Cc: linux-clk@vger.kernel.org
> > Cc: linux-crypto@vger.kernel.org
> > Cc: devicetree@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> > Cc: bhupesh.linux@gmail.com
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> > .../devicetree/bindings/dma/qcom_bam_dma.txt | 50 ----------
> > .../devicetree/bindings/dma/qcom_bam_dma.yaml | 91 +++++++++++++++++++
> > 2 files changed, 91 insertions(+), 50 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> > create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> > deleted file mode 100644
> > index cf5b9e44432c..000000000000
> > --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> > +++ /dev/null
> > @@ -1,50 +0,0 @@
> > -QCOM BAM DMA controller
> > -
> > -Required properties:
> > -- compatible: must be one of the following:
> > - * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084
> > - * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960
> > - * "qcom,bam-v1.7.0" for MSM8916
> > -- reg: Address range for DMA registers
> > -- interrupts: Should contain the one interrupt shared by all channels
> > -- #dma-cells: must be <1>, the cell in the dmas property of the client device
> > - represents the channel number
> > -- clocks: required clock
> > -- clock-names: must contain "bam_clk" entry
> > -- qcom,ee : indicates the active Execution Environment identifier (0-7) used in
> > - the secure world.
> > -- qcom,controlled-remotely : optional, indicates that the bam is controlled by
> > - remote proccessor i.e. execution environment.
> > -- num-channels : optional, indicates supported number of DMA channels in a
> > - remotely controlled bam.
> > -- qcom,num-ees : optional, indicates supported number of Execution Environments
> > - in a remotely controlled bam.
> > -
> > -Example:
> > -
> > - uart-bam: dma@f9984000 = {
> > - compatible = "qcom,bam-v1.4.0";
> > - reg = <0xf9984000 0x15000>;
> > - interrupts = <0 94 0>;
> > - clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
> > - clock-names = "bam_clk";
> > - #dma-cells = <1>;
> > - qcom,ee = <0>;
> > - };
> > -
> > -DMA clients must use the format described in the dma.txt file, using a two cell
> > -specifier for each channel.
> > -
> > -Example:
> > - serial@f991e000 {
> > - compatible = "qcom,msm-uart";
> > - reg = <0xf991e000 0x1000>
> > - <0xf9944000 0x19000>;
> > - interrupts = <0 108 0>;
> > - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
> > - <&gcc GCC_BLSP1_AHB_CLK>;
> > - clock-names = "core", "iface";
> > -
> > - dmas = <&uart-bam 0>, <&uart-bam 1>;
> > - dma-names = "rx", "tx";
> > - };
> > diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> > new file mode 100644
> > index 000000000000..173e4d7508a6
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> > @@ -0,0 +1,91 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/dma/qcom_bam_dma.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: QCOM BAM DMA controller binding
> > +
> > +maintainers:
> > + - Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > +
> > +description: |
> > + This document defines the binding for the BAM DMA controller
> > + found on Qualcomm parts.
> > +
> > +allOf:
> > + - $ref: "dma-controller.yaml#"
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - qcom,bam-v1.4.0
> > + - qcom,bam-v1.3.0
> > + - qcom,bam-v1.7.0
> > +
> > + reg:
> > + maxItems: 1
> > + description: Address range of the DMA registers.
> > +
> > + clocks:
> > + minItems: 1
> > + maxItems: 8
> > +
> > + clock-names:
> > + const: bam_clk
> > +
> > + interrupts:
> > + maxItems: 1
> > + description: Single interrupt line shared by all channels.
> > +
> > + num-channels:
> > + maxItems: 31
>
> maxItems doesn't seem right here, since num-channels isn't an array.
> Perhaps you meant maximum: 31?
>
> Can you check your bindings on the existing device trees with
> "make dtbs_check" and make sure that only reasonable errors remain?
>
> This fails on pretty much every device tree:
>
> arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: dma-controller@9184000: num-channels: [[31]] is too short
> From schema: Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
I did run "make dtbs_check" and I don't remember seeing the issues you reported.
Hmm.. maybe I missed something. Let me recheck and fix issues in v4.
> > + description: |
> > + Indicates supported number of DMA channels in a remotely controlled bam.
> > +
> > + "#dma-cells":
> > + const: 1
> > + description: The single cell represents the channel index.
> > +
> > + qcom,ee:
> > + $ref: /schemas/types.yaml#/definitions/uint8
> > + description:
> > + Indicates the active Execution Environment identifier (0-7)
> > + used in the secure world.
> > + enum: [0, 1, 2, 3, 4, 5, 6, 7]
> > +
>
> bam_dma.c reads this as uint32 and all existing device tree specify it
> as uint32. I don't think adding the /bits/ 8 to all existing device
> trees is really worth it.
>
> arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: dma-controller@9184000: qcom,ee: missing size tag in [[1]]
> From schema: Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
Ok.
> > + qcom,controlled-remotely:
> > + $ref: /schemas/types.yaml#/definitions/flag
> > + description:
> > + Indicates that the bam is controlled by remote proccessor i.e.
> > + execution environment.
> > +
> > + qcom,num-ees:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description:
> > + Indicates supported number of Execution Environments in a
> > + remotely controlled bam.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > + - clock-names
>
> clocks is often missing if qcom,controlled-remotely is set, e.g.
>
> slimbam: dma-controller@9184000 {
> compatible = "qcom,bam-v1.7.0";
> qcom,controlled-remotely;
> reg = <0x09184000 0x32000>;
> num-channels = <31>;
> interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
> #dma-cells = <1>;
> qcom,ee = <1>;
> qcom,num-ees = <2>;
> };
>
> arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: dma-controller@9184000: 'clocks' is a required property
> From schema: Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: dma-controller@9184000: 'clock-names' is a required property
> From schema: Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
>
> You might be able to encode this with an if: statement (clocks required
> if qcom,controlled-remotely not specified), not sure.
Ok.
Thanks,
Bhupesh
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 02/17] dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties
2021-05-19 14:36 [PATCH v3 00/17] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
2021-05-19 14:36 ` [PATCH v3 01/17] dt-bindings: qcom-bam: Convert binding to YAML Bhupesh Sharma
@ 2021-05-19 14:36 ` Bhupesh Sharma
2021-05-19 14:36 ` [PATCH v3 03/17] dt-bindings: qcom-bam: Add 'iommus' to required properties Bhupesh Sharma
` (15 subsequent siblings)
17 siblings, 0 replies; 37+ messages in thread
From: Bhupesh Sharma @ 2021-05-19 14:36 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
Add new optional properties - 'interconnects' and
'interconnect-names' to the device-tree binding documentation for
qcom-bam DMA IP.
These properties describe the interconnect path between bam and main
memory and the interconnect type respectively.
Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: dmaengine@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: bhupesh.linux@gmail.com
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
index 173e4d7508a6..d2900616006c 100644
--- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
+++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
@@ -47,6 +47,14 @@ properties:
const: 1
description: The single cell represents the channel index.
+ interconnects:
+ maxItems: 1
+ description: |
+ Interconnect path between bam and main memory.
+
+ interconnect-names:
+ const: memory
+
qcom,ee:
$ref: /schemas/types.yaml#/definitions/uint8
description:
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v3 03/17] dt-bindings: qcom-bam: Add 'iommus' to required properties
2021-05-19 14:36 [PATCH v3 00/17] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
2021-05-19 14:36 ` [PATCH v3 01/17] dt-bindings: qcom-bam: Convert binding to YAML Bhupesh Sharma
2021-05-19 14:36 ` [PATCH v3 02/17] dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties Bhupesh Sharma
@ 2021-05-19 14:36 ` Bhupesh Sharma
2021-05-21 1:44 ` Rob Herring
2021-05-21 8:11 ` Stephan Gerhold
2021-05-19 14:36 ` [PATCH v3 04/17] dt-bindings: qcom-qce: Convert bindings to yaml Bhupesh Sharma
` (14 subsequent siblings)
17 siblings, 2 replies; 37+ messages in thread
From: Bhupesh Sharma @ 2021-05-19 14:36 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
Add the missing required property - 'iommus' to the
device-tree binding documentation for qcom-bam DMA IP.
This property describes the phandle(s) to apps_smmu node with sid mask.
Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: dmaengine@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: bhupesh.linux@gmail.com
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
.../devicetree/bindings/dma/qcom_bam_dma.yaml | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
index d2900616006c..2479862a3654 100644
--- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
+++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
@@ -55,6 +55,12 @@ properties:
interconnect-names:
const: memory
+ iommus:
+ minItems: 1
+ maxItems: 8
+ description: |
+ phandle to apps_smmu node with sid mask.
+
qcom,ee:
$ref: /schemas/types.yaml#/definitions/uint8
description:
@@ -81,6 +87,7 @@ required:
- clocks
- clock-names
- "#dma-cells"
+ - iommus
- qcom,ee
additionalProperties: false
@@ -96,4 +103,8 @@ examples:
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = /bits/ 8 <0>;
+ iommus = <&apps_smmu 0x584 0x0011>,
+ <&apps_smmu 0x586 0x0011>,
+ <&apps_smmu 0x594 0x0011>,
+ <&apps_smmu 0x596 0x0011>;
};
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v3 03/17] dt-bindings: qcom-bam: Add 'iommus' to required properties
2021-05-19 14:36 ` [PATCH v3 03/17] dt-bindings: qcom-bam: Add 'iommus' to required properties Bhupesh Sharma
@ 2021-05-21 1:44 ` Rob Herring
2021-05-21 8:11 ` Stephan Gerhold
1 sibling, 0 replies; 37+ messages in thread
From: Rob Herring @ 2021-05-21 1:44 UTC (permalink / raw)
To: Bhupesh Sharma
Cc: linux-arm-msm, Thara Gopinath, Bjorn Andersson, Andy Gross,
Herbert Xu, David S . Miller, Stephen Boyd, Michael Turquette,
Vinod Koul, dmaengine, linux-clk, linux-crypto, devicetree,
linux-kernel, bhupesh.linux
On Wed, May 19, 2021 at 08:06:46PM +0530, Bhupesh Sharma wrote:
> Add the missing required property - 'iommus' to the
> device-tree binding documentation for qcom-bam DMA IP.
>
> This property describes the phandle(s) to apps_smmu node with sid mask.
>
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Herbert Xu <herbert@gondor.apana.org.au>
> Cc: David S. Miller <davem@davemloft.net>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: dmaengine@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-crypto@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: bhupesh.linux@gmail.com
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
> .../devicetree/bindings/dma/qcom_bam_dma.yaml | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> index d2900616006c..2479862a3654 100644
> --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> @@ -55,6 +55,12 @@ properties:
> interconnect-names:
> const: memory
>
> + iommus:
> + minItems: 1
> + maxItems: 8
> + description: |
> + phandle to apps_smmu node with sid mask.
And what are the other 7 entries?
> +
> qcom,ee:
> $ref: /schemas/types.yaml#/definitions/uint8
> description:
> @@ -81,6 +87,7 @@ required:
> - clocks
> - clock-names
> - "#dma-cells"
> + - iommus
> - qcom,ee
>
> additionalProperties: false
> @@ -96,4 +103,8 @@ examples:
> clock-names = "bam_clk";
> #dma-cells = <1>;
> qcom,ee = /bits/ 8 <0>;
> + iommus = <&apps_smmu 0x584 0x0011>,
> + <&apps_smmu 0x586 0x0011>,
> + <&apps_smmu 0x594 0x0011>,
> + <&apps_smmu 0x596 0x0011>;
> };
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v3 03/17] dt-bindings: qcom-bam: Add 'iommus' to required properties
2021-05-19 14:36 ` [PATCH v3 03/17] dt-bindings: qcom-bam: Add 'iommus' to required properties Bhupesh Sharma
2021-05-21 1:44 ` Rob Herring
@ 2021-05-21 8:11 ` Stephan Gerhold
1 sibling, 0 replies; 37+ messages in thread
From: Stephan Gerhold @ 2021-05-21 8:11 UTC (permalink / raw)
To: Bhupesh Sharma
Cc: linux-arm-msm, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
Hi,
On Wed, May 19, 2021 at 08:06:46PM +0530, Bhupesh Sharma wrote:
> Add the missing required property - 'iommus' to the
> device-tree binding documentation for qcom-bam DMA IP.
>
> This property describes the phandle(s) to apps_smmu node with sid mask.
>
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Herbert Xu <herbert@gondor.apana.org.au>
> Cc: David S. Miller <davem@davemloft.net>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: dmaengine@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-crypto@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: bhupesh.linux@gmail.com
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
> .../devicetree/bindings/dma/qcom_bam_dma.yaml | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> index d2900616006c..2479862a3654 100644
> --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
> @@ -55,6 +55,12 @@ properties:
> interconnect-names:
> const: memory
>
> + iommus:
> + minItems: 1
> + maxItems: 8
> + description: |
> + phandle to apps_smmu node with sid mask.
> +
> qcom,ee:
> $ref: /schemas/types.yaml#/definitions/uint8
> description:
> @@ -81,6 +87,7 @@ required:
> - clocks
> - clock-names
> - "#dma-cells"
> + - iommus
I don't think we can make this required, older SoCs don't use "iommus"
for bam_dma.
arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: dma-controller@7884000: 'iommus' is a required property
From schema: Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml
Stephan
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 04/17] dt-bindings: qcom-qce: Convert bindings to yaml
2021-05-19 14:36 [PATCH v3 00/17] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
` (2 preceding siblings ...)
2021-05-19 14:36 ` [PATCH v3 03/17] dt-bindings: qcom-bam: Add 'iommus' to required properties Bhupesh Sharma
@ 2021-05-19 14:36 ` Bhupesh Sharma
2021-05-21 1:45 ` Rob Herring
2021-05-19 14:36 ` [PATCH v3 05/17] dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to optional properties Bhupesh Sharma
` (13 subsequent siblings)
17 siblings, 1 reply; 37+ messages in thread
From: Bhupesh Sharma @ 2021-05-19 14:36 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
Convert Qualcomm QCE crypto devicetree binding to YAML.
Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: dmaengine@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: bhupesh.linux@gmail.com
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
.../devicetree/bindings/crypto/qcom-qce.txt | 25 -------
.../devicetree/bindings/crypto/qcom-qce.yaml | 69 +++++++++++++++++++
2 files changed, 69 insertions(+), 25 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.txt
create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
deleted file mode 100644
index fdd53b184ba8..000000000000
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Qualcomm crypto engine driver
-
-Required properties:
-
-- compatible : should be "qcom,crypto-v5.1"
-- reg : specifies base physical address and size of the registers map
-- clocks : phandle to clock-controller plus clock-specifier pair
-- clock-names : "iface" clocks register interface
- "bus" clocks data transfer interface
- "core" clocks rest of the crypto block
-- dmas : DMA specifiers for tx and rx dma channels. For more see
- Documentation/devicetree/bindings/dma/dma.txt
-- dma-names : DMA request names should be "rx" and "tx"
-
-Example:
- crypto@fd45a000 {
- compatible = "qcom,crypto-v5.1";
- reg = <0xfd45a000 0x6000>;
- clocks = <&gcc GCC_CE2_AHB_CLK>,
- <&gcc GCC_CE2_AXI_CLK>,
- <&gcc GCC_CE2_CLK>;
- clock-names = "iface", "bus", "core";
- dmas = <&cryptobam 2>, <&cryptobam 3>;
- dma-names = "rx", "tx";
- };
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
new file mode 100644
index 000000000000..a691cd08f372
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm crypto engine driver
+
+maintainers:
+ - Bhupesh Sharma <bhupesh.sharma@linaro.org>
+
+description: |
+ This document defines the binding for the QCE crypto
+ controller found on Qualcomm parts.
+
+properties:
+ compatible:
+ const: qcom,crypto-v5.1
+
+ reg:
+ maxItems: 1
+ description: |
+ Specifies base physical address and size of the registers map.
+
+ clocks:
+ items:
+ - description: iface clocks register interface.
+ - description: bus clocks data transfer interface.
+ - description: core clocks rest of the crypto block.
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+
+ dmas:
+ items:
+ - description: DMA specifiers for tx dma channel.
+ - description: DMA specifiers for rx dma channel.
+
+ dma-names:
+ items:
+ - const: rx
+ - const: tx
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - dmas
+ - dma-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-apq8084.h>
+ crypto-engine@fd45a000 {
+ compatible = "qcom,crypto-v5.1";
+ reg = <0xfd45a000 0x6000>;
+ clocks = <&gcc GCC_CE2_AHB_CLK>,
+ <&gcc GCC_CE2_AXI_CLK>,
+ <&gcc GCC_CE2_CLK>;
+ clock-names = "iface", "bus", "core";
+ dmas = <&cryptobam 2>, <&cryptobam 3>;
+ dma-names = "rx", "tx";
+ };
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v3 04/17] dt-bindings: qcom-qce: Convert bindings to yaml
2021-05-19 14:36 ` [PATCH v3 04/17] dt-bindings: qcom-qce: Convert bindings to yaml Bhupesh Sharma
@ 2021-05-21 1:45 ` Rob Herring
2021-06-04 3:41 ` Bhupesh Sharma
0 siblings, 1 reply; 37+ messages in thread
From: Rob Herring @ 2021-05-21 1:45 UTC (permalink / raw)
To: Bhupesh Sharma
Cc: linux-arm-msm, Thara Gopinath, Bjorn Andersson, Andy Gross,
Herbert Xu, David S . Miller, Stephen Boyd, Michael Turquette,
Vinod Koul, dmaengine, linux-clk, linux-crypto, devicetree,
linux-kernel, bhupesh.linux
On Wed, May 19, 2021 at 08:06:47PM +0530, Bhupesh Sharma wrote:
> Convert Qualcomm QCE crypto devicetree binding to YAML.
>
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Herbert Xu <herbert@gondor.apana.org.au>
> Cc: David S. Miller <davem@davemloft.net>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: dmaengine@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-crypto@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: bhupesh.linux@gmail.com
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
> .../devicetree/bindings/crypto/qcom-qce.txt | 25 -------
> .../devicetree/bindings/crypto/qcom-qce.yaml | 69 +++++++++++++++++++
> 2 files changed, 69 insertions(+), 25 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.txt
> create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml
>
> diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
> deleted file mode 100644
> index fdd53b184ba8..000000000000
> --- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt
> +++ /dev/null
> @@ -1,25 +0,0 @@
> -Qualcomm crypto engine driver
> -
> -Required properties:
> -
> -- compatible : should be "qcom,crypto-v5.1"
> -- reg : specifies base physical address and size of the registers map
> -- clocks : phandle to clock-controller plus clock-specifier pair
> -- clock-names : "iface" clocks register interface
> - "bus" clocks data transfer interface
> - "core" clocks rest of the crypto block
> -- dmas : DMA specifiers for tx and rx dma channels. For more see
> - Documentation/devicetree/bindings/dma/dma.txt
> -- dma-names : DMA request names should be "rx" and "tx"
> -
> -Example:
> - crypto@fd45a000 {
> - compatible = "qcom,crypto-v5.1";
> - reg = <0xfd45a000 0x6000>;
> - clocks = <&gcc GCC_CE2_AHB_CLK>,
> - <&gcc GCC_CE2_AXI_CLK>,
> - <&gcc GCC_CE2_CLK>;
> - clock-names = "iface", "bus", "core";
> - dmas = <&cryptobam 2>, <&cryptobam 3>;
> - dma-names = "rx", "tx";
> - };
> diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> new file mode 100644
> index 000000000000..a691cd08f372
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> @@ -0,0 +1,69 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm crypto engine driver
> +
> +maintainers:
> + - Bhupesh Sharma <bhupesh.sharma@linaro.org>
> +
> +description: |
> + This document defines the binding for the QCE crypto
> + controller found on Qualcomm parts.
> +
> +properties:
> + compatible:
> + const: qcom,crypto-v5.1
> +
> + reg:
> + maxItems: 1
> + description: |
> + Specifies base physical address and size of the registers map.
Yep, that's every 'reg'. Drop.
With that dropped,
Reviewed-by: Rob Herring <robh@kernel.org>
> +
> + clocks:
> + items:
> + - description: iface clocks register interface.
> + - description: bus clocks data transfer interface.
> + - description: core clocks rest of the crypto block.
> +
> + clock-names:
> + items:
> + - const: iface
> + - const: bus
> + - const: core
> +
> + dmas:
> + items:
> + - description: DMA specifiers for tx dma channel.
> + - description: DMA specifiers for rx dma channel.
> +
> + dma-names:
> + items:
> + - const: rx
> + - const: tx
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - dmas
> + - dma-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-apq8084.h>
> + crypto-engine@fd45a000 {
> + compatible = "qcom,crypto-v5.1";
> + reg = <0xfd45a000 0x6000>;
> + clocks = <&gcc GCC_CE2_AHB_CLK>,
> + <&gcc GCC_CE2_AXI_CLK>,
> + <&gcc GCC_CE2_CLK>;
> + clock-names = "iface", "bus", "core";
> + dmas = <&cryptobam 2>, <&cryptobam 3>;
> + dma-names = "rx", "tx";
> + };
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH v3 04/17] dt-bindings: qcom-qce: Convert bindings to yaml
2021-05-21 1:45 ` Rob Herring
@ 2021-06-04 3:41 ` Bhupesh Sharma
0 siblings, 0 replies; 37+ messages in thread
From: Bhupesh Sharma @ 2021-06-04 3:41 UTC (permalink / raw)
To: Rob Herring
Cc: linux-arm-msm, Thara Gopinath, Bjorn Andersson, Andy Gross,
Herbert Xu, David S . Miller, Stephen Boyd, Michael Turquette,
Vinod Koul, dmaengine, linux-clk, linux-crypto, devicetree,
linux-kernel, bhupesh.linux
Hi Rob,
On Fri, 21 May 2021 at 07:15, Rob Herring <robh@kernel.org> wrote:
>
> On Wed, May 19, 2021 at 08:06:47PM +0530, Bhupesh Sharma wrote:
> > Convert Qualcomm QCE crypto devicetree binding to YAML.
> >
> > Cc: Thara Gopinath <thara.gopinath@linaro.org>
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Andy Gross <agross@kernel.org>
> > Cc: Herbert Xu <herbert@gondor.apana.org.au>
> > Cc: David S. Miller <davem@davemloft.net>
> > Cc: Stephen Boyd <sboyd@kernel.org>
> > Cc: Michael Turquette <mturquette@baylibre.com>
> > Cc: Vinod Koul <vkoul@kernel.org>
> > Cc: dmaengine@vger.kernel.org
> > Cc: linux-clk@vger.kernel.org
> > Cc: linux-crypto@vger.kernel.org
> > Cc: devicetree@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> > Cc: bhupesh.linux@gmail.com
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> > .../devicetree/bindings/crypto/qcom-qce.txt | 25 -------
> > .../devicetree/bindings/crypto/qcom-qce.yaml | 69 +++++++++++++++++++
> > 2 files changed, 69 insertions(+), 25 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.txt
> > create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
> > deleted file mode 100644
> > index fdd53b184ba8..000000000000
> > --- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt
> > +++ /dev/null
> > @@ -1,25 +0,0 @@
> > -Qualcomm crypto engine driver
> > -
> > -Required properties:
> > -
> > -- compatible : should be "qcom,crypto-v5.1"
> > -- reg : specifies base physical address and size of the registers map
> > -- clocks : phandle to clock-controller plus clock-specifier pair
> > -- clock-names : "iface" clocks register interface
> > - "bus" clocks data transfer interface
> > - "core" clocks rest of the crypto block
> > -- dmas : DMA specifiers for tx and rx dma channels. For more see
> > - Documentation/devicetree/bindings/dma/dma.txt
> > -- dma-names : DMA request names should be "rx" and "tx"
> > -
> > -Example:
> > - crypto@fd45a000 {
> > - compatible = "qcom,crypto-v5.1";
> > - reg = <0xfd45a000 0x6000>;
> > - clocks = <&gcc GCC_CE2_AHB_CLK>,
> > - <&gcc GCC_CE2_AXI_CLK>,
> > - <&gcc GCC_CE2_CLK>;
> > - clock-names = "iface", "bus", "core";
> > - dmas = <&cryptobam 2>, <&cryptobam 3>;
> > - dma-names = "rx", "tx";
> > - };
> > diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> > new file mode 100644
> > index 000000000000..a691cd08f372
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> > @@ -0,0 +1,69 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm crypto engine driver
> > +
> > +maintainers:
> > + - Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > +
> > +description: |
> > + This document defines the binding for the QCE crypto
> > + controller found on Qualcomm parts.
> > +
> > +properties:
> > + compatible:
> > + const: qcom,crypto-v5.1
> > +
> > + reg:
> > + maxItems: 1
> > + description: |
> > + Specifies base physical address and size of the registers map.
>
> Yep, that's every 'reg'. Drop.
>
> With that dropped,
>
> Reviewed-by: Rob Herring <robh@kernel.org>
Ok, I will drop this in v4.
Thanks,
Bhupesh
> > +
> > + clocks:
> > + items:
> > + - description: iface clocks register interface.
> > + - description: bus clocks data transfer interface.
> > + - description: core clocks rest of the crypto block.
> > +
> > + clock-names:
> > + items:
> > + - const: iface
> > + - const: bus
> > + - const: core
> > +
> > + dmas:
> > + items:
> > + - description: DMA specifiers for tx dma channel.
> > + - description: DMA specifiers for rx dma channel.
> > +
> > + dma-names:
> > + items:
> > + - const: rx
> > + - const: tx
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - clock-names
> > + - dmas
> > + - dma-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/qcom,gcc-apq8084.h>
> > + crypto-engine@fd45a000 {
> > + compatible = "qcom,crypto-v5.1";
> > + reg = <0xfd45a000 0x6000>;
> > + clocks = <&gcc GCC_CE2_AHB_CLK>,
> > + <&gcc GCC_CE2_AXI_CLK>,
> > + <&gcc GCC_CE2_CLK>;
> > + clock-names = "iface", "bus", "core";
> > + dmas = <&cryptobam 2>, <&cryptobam 3>;
> > + dma-names = "rx", "tx";
> > + };
> > --
> > 2.31.1
> >
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 05/17] dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to optional properties
2021-05-19 14:36 [PATCH v3 00/17] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
` (3 preceding siblings ...)
2021-05-19 14:36 ` [PATCH v3 04/17] dt-bindings: qcom-qce: Convert bindings to yaml Bhupesh Sharma
@ 2021-05-19 14:36 ` Bhupesh Sharma
2021-05-19 14:36 ` [PATCH v3 06/17] dt-bindings: qcom-qce: Add 'iommus' to required properties Bhupesh Sharma
` (12 subsequent siblings)
17 siblings, 0 replies; 37+ messages in thread
From: Bhupesh Sharma @ 2021-05-19 14:36 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
Add 'interconnects' and 'interconnect-names' to the device-tree binding
documentation for qcom crypto IP.
These properties describe the interconnect path between crypto and main
memory and the interconnect type respectively.
While at it also move 'clocks' to the optional properties sections,
as crypto IPs on SoCs like sm8150, sm8250, sm8350 (and so on), don't
require linux to setup the clocks (this is already done by the secure
firmware running before linux).
Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: dmaengine@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: bhupesh.linux@gmail.com
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index a691cd08f372..f8d3ea8b0d08 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -34,6 +34,14 @@ properties:
- const: bus
- const: core
+ interconnects:
+ maxItems: 1
+ description: |
+ Interconnect path between qce crypto and main memory.
+
+ interconnect-names:
+ const: memory
+
dmas:
items:
- description: DMA specifiers for tx dma channel.
@@ -47,8 +55,6 @@ properties:
required:
- compatible
- reg
- - clocks
- - clock-names
- dmas
- dma-names
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v3 06/17] dt-bindings: qcom-qce: Add 'iommus' to required properties
2021-05-19 14:36 [PATCH v3 00/17] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
` (4 preceding siblings ...)
2021-05-19 14:36 ` [PATCH v3 05/17] dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to optional properties Bhupesh Sharma
@ 2021-05-19 14:36 ` Bhupesh Sharma
2021-05-19 14:36 ` [PATCH v3 07/17] arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly Bhupesh Sharma
` (11 subsequent siblings)
17 siblings, 0 replies; 37+ messages in thread
From: Bhupesh Sharma @ 2021-05-19 14:36 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
Add the missing required property - 'iommus' to the
device-tree binding documentation for qcom-qce crypto IP.
This property describes the phandle(s) to apps_smmu node with sid mask.
Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: dmaengine@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: bhupesh.linux@gmail.com
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
.../devicetree/bindings/crypto/qcom-qce.yaml | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index f8d3ea8b0d08..4be9ce697123 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -34,6 +34,12 @@ properties:
- const: bus
- const: core
+ iommus:
+ minItems: 1
+ maxItems: 8
+ description: |
+ phandle to apps_smmu node with sid mask.
+
interconnects:
maxItems: 1
description: |
@@ -57,6 +63,7 @@ required:
- reg
- dmas
- dma-names
+ - iommus
additionalProperties: false
@@ -72,4 +79,9 @@ examples:
clock-names = "iface", "bus", "core";
dmas = <&cryptobam 2>, <&cryptobam 3>;
dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x584 0x0011>,
+ <&apps_smmu 0x586 0x0011>,
+ <&apps_smmu 0x594 0x0011>,
+ <&apps_smmu 0x596 0x0011>;
+
};
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v3 07/17] arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly
2021-05-19 14:36 [PATCH v3 00/17] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
` (5 preceding siblings ...)
2021-05-19 14:36 ` [PATCH v3 06/17] dt-bindings: qcom-qce: Add 'iommus' to required properties Bhupesh Sharma
@ 2021-05-19 14:36 ` Bhupesh Sharma
2021-05-21 1:47 ` Thara Gopinath
2021-05-19 14:36 ` [PATCH v3 08/17] dt-bindings: crypto : Add new compatible strings for qcom-qce Bhupesh Sharma
` (10 subsequent siblings)
17 siblings, 1 reply; 37+ messages in thread
From: Bhupesh Sharma @ 2021-05-19 14:36 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
In commit 3e482859f1ef ("dts: qcom: sdm845: Add dt entries
to support crypto engine."), we decided to use the value indicated
by constant RPMH_CE_CLK rather than using it directly.
Now that the same RPMH clock value might be used for other
SoCs (in addition to sdm845), let's use the constant
RPMH_CE_CLK to make sure that this dtsi is compatible with the
other qcom ones.
Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: dmaengine@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: bhupesh.linux@gmail.com
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0a86fe71a66d..2ec4be930fd6 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2316,7 +2316,7 @@ cryptobam: dma@1dc4000 {
compatible = "qcom,bam-v1.7.0";
reg = <0 0x01dc4000 0 0x24000>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rpmhcc 15>;
+ clocks = <&rpmhcc RPMH_CE_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
@@ -2332,7 +2332,7 @@ crypto: crypto@1dfa000 {
reg = <0 0x01dfa000 0 0x6000>;
clocks = <&gcc GCC_CE1_AHB_CLK>,
<&gcc GCC_CE1_AHB_CLK>,
- <&rpmhcc 15>;
+ <&rpmhcc RPMH_CE_CLK>;
clock-names = "iface", "bus", "core";
dmas = <&cryptobam 6>, <&cryptobam 7>;
dma-names = "rx", "tx";
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v3 07/17] arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly
2021-05-19 14:36 ` [PATCH v3 07/17] arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly Bhupesh Sharma
@ 2021-05-21 1:47 ` Thara Gopinath
0 siblings, 0 replies; 37+ messages in thread
From: Thara Gopinath @ 2021-05-21 1:47 UTC (permalink / raw)
To: Bhupesh Sharma, linux-arm-msm
Cc: Bjorn Andersson, Rob Herring, Andy Gross, Herbert Xu,
David S . Miller, Stephen Boyd, Michael Turquette, Vinod Koul,
dmaengine, linux-clk, linux-crypto, devicetree, linux-kernel,
bhupesh.linux
On 5/19/21 10:36 AM, Bhupesh Sharma wrote:
> In commit 3e482859f1ef ("dts: qcom: sdm845: Add dt entries
> to support crypto engine."), we decided to use the value indicated
> by constant RPMH_CE_CLK rather than using it directly.
>
> Now that the same RPMH clock value might be used for other
> SoCs (in addition to sdm845), let's use the constant
> RPMH_CE_CLK to make sure that this dtsi is compatible with the
> other qcom ones.
>
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Herbert Xu <herbert@gondor.apana.org.au>
> Cc: David S. Miller <davem@davemloft.net>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: dmaengine@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-crypto@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: bhupesh.linux@gmail.com
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
Warm Regards
Thara
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 0a86fe71a66d..2ec4be930fd6 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -2316,7 +2316,7 @@ cryptobam: dma@1dc4000 {
> compatible = "qcom,bam-v1.7.0";
> reg = <0 0x01dc4000 0 0x24000>;
> interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&rpmhcc 15>;
> + clocks = <&rpmhcc RPMH_CE_CLK>;
> clock-names = "bam_clk";
> #dma-cells = <1>;
> qcom,ee = <0>;
> @@ -2332,7 +2332,7 @@ crypto: crypto@1dfa000 {
> reg = <0 0x01dfa000 0 0x6000>;
> clocks = <&gcc GCC_CE1_AHB_CLK>,
> <&gcc GCC_CE1_AHB_CLK>,
> - <&rpmhcc 15>;
> + <&rpmhcc RPMH_CE_CLK>;
> clock-names = "iface", "bus", "core";
> dmas = <&cryptobam 6>, <&cryptobam 7>;
> dma-names = "rx", "tx";
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 08/17] dt-bindings: crypto : Add new compatible strings for qcom-qce
2021-05-19 14:36 [PATCH v3 00/17] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
` (6 preceding siblings ...)
2021-05-19 14:36 ` [PATCH v3 07/17] arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly Bhupesh Sharma
@ 2021-05-19 14:36 ` Bhupesh Sharma
2021-05-21 1:46 ` Rob Herring
2021-05-19 14:36 ` [PATCH v3 09/17] arm64/dts: qcom: Use new compatibles for crypto nodes Bhupesh Sharma
` (9 subsequent siblings)
17 siblings, 1 reply; 37+ messages in thread
From: Bhupesh Sharma @ 2021-05-19 14:36 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
Newer qcom chips support newer versions of the qce crypto IP, so add
soc specific compatible strings for qcom-qce instead of using crypto
IP version specific ones.
Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: dmaengine@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: bhupesh.linux@gmail.com
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index 4be9ce697123..7722ac9529bf 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -15,7 +15,12 @@ description: |
properties:
compatible:
- const: qcom,crypto-v5.1
+ enum:
+ - qcom,ipq6018-qce
+ - qcom,sdm845-qce
+ - qcom,sm8150-qce
+ - qcom,sm8250-qce
+ - qcom,sm8350-qce
reg:
maxItems: 1
@@ -71,7 +76,7 @@ examples:
- |
#include <dt-bindings/clock/qcom,gcc-apq8084.h>
crypto-engine@fd45a000 {
- compatible = "qcom,crypto-v5.1";
+ compatible = "qcom,ipq6018-qce";
reg = <0xfd45a000 0x6000>;
clocks = <&gcc GCC_CE2_AHB_CLK>,
<&gcc GCC_CE2_AXI_CLK>,
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v3 08/17] dt-bindings: crypto : Add new compatible strings for qcom-qce
2021-05-19 14:36 ` [PATCH v3 08/17] dt-bindings: crypto : Add new compatible strings for qcom-qce Bhupesh Sharma
@ 2021-05-21 1:46 ` Rob Herring
2021-06-05 8:33 ` Bhupesh Sharma
0 siblings, 1 reply; 37+ messages in thread
From: Rob Herring @ 2021-05-21 1:46 UTC (permalink / raw)
To: Bhupesh Sharma
Cc: linux-arm-msm, Thara Gopinath, Bjorn Andersson, Andy Gross,
Herbert Xu, David S . Miller, Stephen Boyd, Michael Turquette,
Vinod Koul, dmaengine, linux-clk, linux-crypto, devicetree,
linux-kernel, bhupesh.linux
On Wed, May 19, 2021 at 08:06:51PM +0530, Bhupesh Sharma wrote:
> Newer qcom chips support newer versions of the qce crypto IP, so add
> soc specific compatible strings for qcom-qce instead of using crypto
> IP version specific ones.
>
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Herbert Xu <herbert@gondor.apana.org.au>
> Cc: David S. Miller <davem@davemloft.net>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: dmaengine@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-crypto@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: bhupesh.linux@gmail.com
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
> Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> index 4be9ce697123..7722ac9529bf 100644
> --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> @@ -15,7 +15,12 @@ description: |
>
> properties:
> compatible:
> - const: qcom,crypto-v5.1
You can't get rid of the old one.
> + enum:
> + - qcom,ipq6018-qce
> + - qcom,sdm845-qce
> + - qcom,sm8150-qce
> + - qcom,sm8250-qce
> + - qcom,sm8350-qce
>
> reg:
> maxItems: 1
> @@ -71,7 +76,7 @@ examples:
> - |
> #include <dt-bindings/clock/qcom,gcc-apq8084.h>
> crypto-engine@fd45a000 {
> - compatible = "qcom,crypto-v5.1";
> + compatible = "qcom,ipq6018-qce";
> reg = <0xfd45a000 0x6000>;
> clocks = <&gcc GCC_CE2_AHB_CLK>,
> <&gcc GCC_CE2_AXI_CLK>,
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH v3 08/17] dt-bindings: crypto : Add new compatible strings for qcom-qce
2021-05-21 1:46 ` Rob Herring
@ 2021-06-05 8:33 ` Bhupesh Sharma
0 siblings, 0 replies; 37+ messages in thread
From: Bhupesh Sharma @ 2021-06-05 8:33 UTC (permalink / raw)
To: Rob Herring
Cc: linux-arm-msm, Thara Gopinath, Bjorn Andersson, Andy Gross,
Herbert Xu, David S . Miller, Stephen Boyd, Michael Turquette,
Vinod Koul, dmaengine, linux-clk, linux-crypto, devicetree,
linux-kernel, bhupesh.linux
Hi Rob,
On Fri, 21 May 2021 at 07:16, Rob Herring <robh@kernel.org> wrote:
>
> On Wed, May 19, 2021 at 08:06:51PM +0530, Bhupesh Sharma wrote:
> > Newer qcom chips support newer versions of the qce crypto IP, so add
> > soc specific compatible strings for qcom-qce instead of using crypto
> > IP version specific ones.
> >
> > Cc: Thara Gopinath <thara.gopinath@linaro.org>
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Andy Gross <agross@kernel.org>
> > Cc: Herbert Xu <herbert@gondor.apana.org.au>
> > Cc: David S. Miller <davem@davemloft.net>
> > Cc: Stephen Boyd <sboyd@kernel.org>
> > Cc: Michael Turquette <mturquette@baylibre.com>
> > Cc: Vinod Koul <vkoul@kernel.org>
> > Cc: dmaengine@vger.kernel.org
> > Cc: linux-clk@vger.kernel.org
> > Cc: linux-crypto@vger.kernel.org
> > Cc: devicetree@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> > Cc: bhupesh.linux@gmail.com
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> > Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 9 +++++++--
> > 1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> > index 4be9ce697123..7722ac9529bf 100644
> > --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> > +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> > @@ -15,7 +15,12 @@ description: |
> >
> > properties:
> > compatible:
> > - const: qcom,crypto-v5.1
>
> You can't get rid of the old one.
Ok, I will fix it in v4.
Thanks,
Bhupesh
> > + enum:
> > + - qcom,ipq6018-qce
> > + - qcom,sdm845-qce
> > + - qcom,sm8150-qce
> > + - qcom,sm8250-qce
> > + - qcom,sm8350-qce
> >
> > reg:
> > maxItems: 1
> > @@ -71,7 +76,7 @@ examples:
> > - |
> > #include <dt-bindings/clock/qcom,gcc-apq8084.h>
> > crypto-engine@fd45a000 {
> > - compatible = "qcom,crypto-v5.1";
> > + compatible = "qcom,ipq6018-qce";
> > reg = <0xfd45a000 0x6000>;
> > clocks = <&gcc GCC_CE2_AHB_CLK>,
> > <&gcc GCC_CE2_AXI_CLK>,
> > --
> > 2.31.1
> >
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 09/17] arm64/dts: qcom: Use new compatibles for crypto nodes
2021-05-19 14:36 [PATCH v3 00/17] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
` (7 preceding siblings ...)
2021-05-19 14:36 ` [PATCH v3 08/17] dt-bindings: crypto : Add new compatible strings for qcom-qce Bhupesh Sharma
@ 2021-05-19 14:36 ` Bhupesh Sharma
2021-05-19 14:36 ` [PATCH v3 10/17] dma: qcom: bam_dma: Add support to initialize interconnect path Bhupesh Sharma
` (8 subsequent siblings)
17 siblings, 0 replies; 37+ messages in thread
From: Bhupesh Sharma @ 2021-05-19 14:36 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
Since we are using soc specific qce crypto IP compatibles
in the bindings now, use the same in the device tree files
which include the crypto nodes.
Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: dmaengine@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: bhupesh.linux@gmail.com
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 9fa5b028e4f3..978c34f176de 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -205,7 +205,7 @@ cryptobam: dma-controller@704000 {
};
crypto: crypto@73a000 {
- compatible = "qcom,crypto-v5.1";
+ compatible = "qcom,ipq6018-qce";
reg = <0x0 0x0073a000 0x0 0x6000>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
<&gcc GCC_CRYPTO_AXI_CLK>,
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 2ec4be930fd6..6423991fa303 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2328,7 +2328,7 @@ cryptobam: dma@1dc4000 {
};
crypto: crypto@1dfa000 {
- compatible = "qcom,crypto-v5.4";
+ compatible = "qcom,sdm845-qce";
reg = <0 0x01dfa000 0 0x6000>;
clocks = <&gcc GCC_CE1_AHB_CLK>,
<&gcc GCC_CE1_AHB_CLK>,
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v3 10/17] dma: qcom: bam_dma: Add support to initialize interconnect path
2021-05-19 14:36 [PATCH v3 00/17] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
` (8 preceding siblings ...)
2021-05-19 14:36 ` [PATCH v3 09/17] arm64/dts: qcom: Use new compatibles for crypto nodes Bhupesh Sharma
@ 2021-05-19 14:36 ` Bhupesh Sharma
2021-05-19 14:36 ` [PATCH v3 11/17] crypto: qce: core: " Bhupesh Sharma
` (7 subsequent siblings)
17 siblings, 0 replies; 37+ messages in thread
From: Bhupesh Sharma @ 2021-05-19 14:36 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
From: Thara Gopinath <thara.gopinath@linaro.org>
BAM dma engine associated with certain hardware blocks could require
relevant interconnect pieces be initialized prior to the dma engine
initialization. For e.g. crypto bam dma engine on sm8250. Such requirement
is passed on to the bam dma driver from dt via the "interconnects"
property. Add support in bam_dma driver to check whether the interconnect
path is accessible/enabled prior to attempting driver intializations.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: dmaengine@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: bhupesh.linux@gmail.com
Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
[ bhupesh.sharma@linaro.org: Make header file inclusion alphabetical and use devm_of_icc_get() ]
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
drivers/dma/qcom/bam_dma.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
index c8a77b428b52..4b03415b8183 100644
--- a/drivers/dma/qcom/bam_dma.c
+++ b/drivers/dma/qcom/bam_dma.c
@@ -26,6 +26,7 @@
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/init.h>
+#include <linux/interconnect.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/interrupt.h>
@@ -392,6 +393,7 @@ struct bam_device {
const struct reg_offset_data *layout;
struct clk *bamclk;
+ struct icc_path *mem_path;
int irq;
/* dma start transaction tasklet */
@@ -1284,6 +1286,14 @@ static int bam_dma_probe(struct platform_device *pdev)
return ret;
}
+ /* Ensure that interconnects are initialized */
+ bdev->mem_path = devm_of_icc_get(bdev->dev, "memory");
+ if (IS_ERR(bdev->mem_path)) {
+ ret = PTR_ERR(bdev->mem_path);
+ dev_err(bdev->dev, "failed to acquire icc path %d\n", ret);
+ goto err_disable_clk;
+ }
+
ret = bam_init(bdev);
if (ret)
goto err_disable_clk;
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v3 11/17] crypto: qce: core: Add support to initialize interconnect path
2021-05-19 14:36 [PATCH v3 00/17] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
` (9 preceding siblings ...)
2021-05-19 14:36 ` [PATCH v3 10/17] dma: qcom: bam_dma: Add support to initialize interconnect path Bhupesh Sharma
@ 2021-05-19 14:36 ` Bhupesh Sharma
2021-05-19 14:36 ` [PATCH v3 12/17] crypto: qce: Add new compatibles for qce crypto driver Bhupesh Sharma
` (6 subsequent siblings)
17 siblings, 0 replies; 37+ messages in thread
From: Bhupesh Sharma @ 2021-05-19 14:36 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
From: Thara Gopinath <thara.gopinath@linaro.org>
Crypto engine on certain Snapdragon processors like sm8150, sm8250, sm8350
etc. requires interconnect path between the engine and memory to be
explicitly enabled and bandwidth set prior to any operations. Add support
in the qce core to enable the interconnect path appropriately.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: dmaengine@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: bhupesh.linux@gmail.com
Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
[ bhupesh.sharma@linaro.org: Make header file inclusion alphabetical and use devm_of_icc_get() ]
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
drivers/crypto/qce/core.c | 12 ++++++++++++
drivers/crypto/qce/core.h | 1 +
2 files changed, 13 insertions(+)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index 80b75085c265..89a17b677607 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -5,6 +5,7 @@
#include <linux/clk.h>
#include <linux/dma-mapping.h>
+#include <linux/interconnect.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
@@ -21,6 +22,8 @@
#define QCE_MAJOR_VERSION5 0x05
#define QCE_QUEUE_LENGTH 1
+#define QCE_DEFAULT_MEM_BANDWIDTH 393600
+
static const struct qce_algo_ops *qce_ops[] = {
#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
&skcipher_ops,
@@ -202,6 +205,11 @@ static int qce_crypto_probe(struct platform_device *pdev)
if (ret < 0)
return ret;
+ qce->mem_path = devm_of_icc_get(qce->dev, "memory");
+ if (IS_ERR(qce->mem_path))
+ return dev_err_probe(dev, PTR_ERR(qce->mem_path),
+ "Failed to get mem path\n");
+
qce->core = devm_clk_get(qce->dev, "core");
if (IS_ERR(qce->core))
return PTR_ERR(qce->core);
@@ -214,6 +222,10 @@ static int qce_crypto_probe(struct platform_device *pdev)
if (IS_ERR(qce->bus))
return PTR_ERR(qce->bus);
+ ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH);
+ if (ret)
+ return ret;
+
ret = clk_prepare_enable(qce->core);
if (ret)
return ret;
diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h
index 085774cdf641..228fcd69ec51 100644
--- a/drivers/crypto/qce/core.h
+++ b/drivers/crypto/qce/core.h
@@ -35,6 +35,7 @@ struct qce_device {
void __iomem *base;
struct device *dev;
struct clk *core, *iface, *bus;
+ struct icc_path *mem_path;
struct qce_dma_data dma;
int burst_size;
unsigned int pipe_pair_id;
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v3 12/17] crypto: qce: Add new compatibles for qce crypto driver
2021-05-19 14:36 [PATCH v3 00/17] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
` (10 preceding siblings ...)
2021-05-19 14:36 ` [PATCH v3 11/17] crypto: qce: core: " Bhupesh Sharma
@ 2021-05-19 14:36 ` Bhupesh Sharma
2021-05-19 14:36 ` [PATCH v3 13/17] crypto: qce: core: Make clocks optional Bhupesh Sharma
` (5 subsequent siblings)
17 siblings, 0 replies; 37+ messages in thread
From: Bhupesh Sharma @ 2021-05-19 14:36 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
Since we decided to use soc specific compatibles for describing
the qce crypto IP nodes in the device-trees, adapt the driver
now to handle the same.
Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: dmaengine@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: bhupesh.linux@gmail.com
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
drivers/crypto/qce/core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index 89a17b677607..905378906ac7 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -285,8 +285,8 @@ static int qce_crypto_remove(struct platform_device *pdev)
}
static const struct of_device_id qce_crypto_of_match[] = {
- { .compatible = "qcom,crypto-v5.1", },
- { .compatible = "qcom,crypto-v5.4", },
+ { .compatible = "qcom,ipq6018-qce", },
+ { .compatible = "qcom,sdm845-qce", },
{}
};
MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH v3 13/17] crypto: qce: core: Make clocks optional
2021-05-19 14:36 [PATCH v3 00/17] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
` (11 preceding siblings ...)
2021-05-19 14:36 ` [PATCH v3 12/17] crypto: qce: Add new compatibles for qce crypto driver Bhupesh Sharma
@ 2021-05-19 14:36 ` Bhupesh Sharma
2021-05-21 2:11 ` Thara Gopinath
2021-05-19 14:36 ` [PATCH v3 14/17] crypto: qce: Print a failure msg in case probe() fails Bhupesh Sharma
` (4 subsequent siblings)
17 siblings, 1 reply; 37+ messages in thread
From: Bhupesh Sharma @ 2021-05-19 14:36 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
From: Thara Gopinath <thara.gopinath@linaro.org>
On certain Snapdragon processors, the crypto engine clocks are enabled by
default by security firmware and the driver need not handle the
clocks. Make acquiring of all the clocks optional in crypto enginer driver
so that the driver intializes properly even if no clocks are specified in
the dt.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: dmaengine@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: bhupesh.linux@gmail.com
Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
[ bhupesh.sharma@linaro.org: Make clock enablement optional only for qcom parts where
firmware has already initialized them, using a bool variable and fix
error paths ]
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
drivers/crypto/qce/core.c | 89 +++++++++++++++++++++++++--------------
drivers/crypto/qce/core.h | 2 +
2 files changed, 59 insertions(+), 32 deletions(-)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index 905378906ac7..8c3c68ba579e 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -9,6 +9,7 @@
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/types.h>
@@ -184,10 +185,20 @@ static int qce_check_version(struct qce_device *qce)
return 0;
}
+static const struct of_device_id qce_crypto_of_match[] = {
+ { .compatible = "qcom,ipq6018-qce", },
+ { .compatible = "qcom,sdm845-qce", },
+ { .compatible = "qcom,sm8250-qce", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
+
static int qce_crypto_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct qce_device *qce;
+ const struct of_device_id *of_id =
+ of_match_device(qce_crypto_of_match, &pdev->dev);
int ret;
qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL);
@@ -198,45 +209,65 @@ static int qce_crypto_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, qce);
qce->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(qce->base))
- return PTR_ERR(qce->base);
+ if (IS_ERR(qce->base)) {
+ ret = PTR_ERR(qce->base);
+ goto err_out;
+ }
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
if (ret < 0)
- return ret;
+ goto err_out;
qce->mem_path = devm_of_icc_get(qce->dev, "memory");
if (IS_ERR(qce->mem_path))
return dev_err_probe(dev, PTR_ERR(qce->mem_path),
"Failed to get mem path\n");
- qce->core = devm_clk_get(qce->dev, "core");
- if (IS_ERR(qce->core))
- return PTR_ERR(qce->core);
-
- qce->iface = devm_clk_get(qce->dev, "iface");
- if (IS_ERR(qce->iface))
- return PTR_ERR(qce->iface);
-
- qce->bus = devm_clk_get(qce->dev, "bus");
- if (IS_ERR(qce->bus))
- return PTR_ERR(qce->bus);
-
ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH);
if (ret)
- return ret;
+ goto err_out;
- ret = clk_prepare_enable(qce->core);
- if (ret)
- return ret;
+ /* On some qcom parts the crypto clocks are already configured by
+ * the firmware running before linux. In such cases we don't need to
+ * enable/configure them again. Check here for the same.
+ */
+ if (!strcmp(of_id->compatible, "qcom,ipq6018-qce") ||
+ !strcmp(of_id->compatible, "qcom,sdm845-qce"))
+ qce->clks_configured_by_fw = false;
+ else
+ qce->clks_configured_by_fw = true;
+
+ if (!qce->clks_configured_by_fw) {
+ qce->core = devm_clk_get(qce->dev, "core");
+ if (IS_ERR(qce->core)) {
+ ret = PTR_ERR(qce->core);
+ goto err_out;
+ }
+
+ qce->iface = devm_clk_get(qce->dev, "iface");
+ if (IS_ERR(qce->iface)) {
+ ret = PTR_ERR(qce->iface);
+ goto err_out;
+ }
+
+ qce->bus = devm_clk_get(qce->dev, "bus");
+ if (IS_ERR(qce->bus)) {
+ ret = PTR_ERR(qce->bus);
+ goto err_out;
+ }
+
+ ret = clk_prepare_enable(qce->core);
+ if (ret)
+ goto err_out;
- ret = clk_prepare_enable(qce->iface);
- if (ret)
- goto err_clks_core;
+ ret = clk_prepare_enable(qce->iface);
+ if (ret)
+ goto err_clks_core;
- ret = clk_prepare_enable(qce->bus);
- if (ret)
- goto err_clks_iface;
+ ret = clk_prepare_enable(qce->bus);
+ if (ret)
+ goto err_clks_iface;
+ }
ret = qce_dma_request(qce->dev, &qce->dma);
if (ret)
@@ -268,6 +299,7 @@ static int qce_crypto_probe(struct platform_device *pdev)
clk_disable_unprepare(qce->iface);
err_clks_core:
clk_disable_unprepare(qce->core);
+err_out:
return ret;
}
@@ -284,13 +316,6 @@ static int qce_crypto_remove(struct platform_device *pdev)
return 0;
}
-static const struct of_device_id qce_crypto_of_match[] = {
- { .compatible = "qcom,ipq6018-qce", },
- { .compatible = "qcom,sdm845-qce", },
- {}
-};
-MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
-
static struct platform_driver qce_crypto_driver = {
.probe = qce_crypto_probe,
.remove = qce_crypto_remove,
diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h
index 228fcd69ec51..d9bf05babecc 100644
--- a/drivers/crypto/qce/core.h
+++ b/drivers/crypto/qce/core.h
@@ -23,6 +23,7 @@
* @dma: pointer to dma data
* @burst_size: the crypto burst size
* @pipe_pair_id: which pipe pair id the device using
+ * @clks_configured_by_fw: clocks are already configured by fw
* @async_req_enqueue: invoked by every algorithm to enqueue a request
* @async_req_done: invoked by every algorithm to finish its request
*/
@@ -39,6 +40,7 @@ struct qce_device {
struct qce_dma_data dma;
int burst_size;
unsigned int pipe_pair_id;
+ bool clks_configured_by_fw;
int (*async_req_enqueue)(struct qce_device *qce,
struct crypto_async_request *req);
void (*async_req_done)(struct qce_device *qce, int ret);
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v3 13/17] crypto: qce: core: Make clocks optional
2021-05-19 14:36 ` [PATCH v3 13/17] crypto: qce: core: Make clocks optional Bhupesh Sharma
@ 2021-05-21 2:11 ` Thara Gopinath
2021-06-05 8:31 ` Bhupesh Sharma
0 siblings, 1 reply; 37+ messages in thread
From: Thara Gopinath @ 2021-05-21 2:11 UTC (permalink / raw)
To: Bhupesh Sharma, linux-arm-msm
Cc: Bjorn Andersson, Rob Herring, Andy Gross, Herbert Xu,
David S . Miller, Stephen Boyd, Michael Turquette, Vinod Koul,
dmaengine, linux-clk, linux-crypto, devicetree, linux-kernel,
bhupesh.linux
Hi Bhupesh,
On 5/19/21 10:36 AM, Bhupesh Sharma wrote:
> From: Thara Gopinath <thara.gopinath@linaro.org>
>
> On certain Snapdragon processors, the crypto engine clocks are enabled by
> default by security firmware and the driver need not handle the
> clocks. Make acquiring of all the clocks optional in crypto enginer driver
> so that the driver intializes properly even if no clocks are specified in
> the dt.
>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Herbert Xu <herbert@gondor.apana.org.au>
> Cc: David S. Miller <davem@davemloft.net>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: dmaengine@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-crypto@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: bhupesh.linux@gmail.com
> Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
> [ bhupesh.sharma@linaro.org: Make clock enablement optional only for qcom parts where
> firmware has already initialized them, using a bool variable and fix
> error paths ]
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
> drivers/crypto/qce/core.c | 89 +++++++++++++++++++++++++--------------
> drivers/crypto/qce/core.h | 2 +
> 2 files changed, 59 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index 905378906ac7..8c3c68ba579e 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
> @@ -9,6 +9,7 @@
> #include <linux/interrupt.h>
> #include <linux/module.h>
> #include <linux/mod_devicetable.h>
> +#include <linux/of_device.h>
> #include <linux/platform_device.h>
> #include <linux/spinlock.h>
> #include <linux/types.h>
> @@ -184,10 +185,20 @@ static int qce_check_version(struct qce_device *qce)
> return 0;
> }
>
> +static const struct of_device_id qce_crypto_of_match[] = {
> + { .compatible = "qcom,ipq6018-qce", },
> + { .compatible = "qcom,sdm845-qce", },
> + { .compatible = "qcom,sm8250-qce", },
Adding qcom,sm8250-qce does not belong in this patch. It deserves a
separate patch of it's own.
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
> +
> static int qce_crypto_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> struct qce_device *qce;
> + const struct of_device_id *of_id =
> + of_match_device(qce_crypto_of_match, &pdev->dev);
> int ret;
>
> qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL);
> @@ -198,45 +209,65 @@ static int qce_crypto_probe(struct platform_device *pdev)
> platform_set_drvdata(pdev, qce);
>
> qce->base = devm_platform_ioremap_resource(pdev, 0);
> - if (IS_ERR(qce->base))
> - return PTR_ERR(qce->base);
> + if (IS_ERR(qce->base)) {
> + ret = PTR_ERR(qce->base);
> + goto err_out;
> + }
I don't see the reason for change in error handling here or below. But
,for whatever reason this is changed, it has to be a separate patch.
>
> ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
> if (ret < 0)
> - return ret;
> + goto err_out;
>
> qce->mem_path = devm_of_icc_get(qce->dev, "memory");
> if (IS_ERR(qce->mem_path))
> return dev_err_probe(dev, PTR_ERR(qce->mem_path),
> "Failed to get mem path\n");
>
> - qce->core = devm_clk_get(qce->dev, "core");
> - if (IS_ERR(qce->core))
> - return PTR_ERR(qce->core);
> -
> - qce->iface = devm_clk_get(qce->dev, "iface");
> - if (IS_ERR(qce->iface))
> - return PTR_ERR(qce->iface);
> -
> - qce->bus = devm_clk_get(qce->dev, "bus");
> - if (IS_ERR(qce->bus))
> - return PTR_ERR(qce->bus);
> -
> ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH);
> if (ret)
> - return ret;
> + goto err_out;
>
> - ret = clk_prepare_enable(qce->core);
> - if (ret)
> - return ret;
> + /* On some qcom parts the crypto clocks are already configured by
> + * the firmware running before linux. In such cases we don't need to
> + * enable/configure them again. Check here for the same.
> + */
> + if (!strcmp(of_id->compatible, "qcom,ipq6018-qce") ||
> + !strcmp(of_id->compatible, "qcom,sdm845-qce"))
You can avoid this and most of this patch by using
devm_clk_get_optional. This patch can be like just three lines of code
change. clk_prepare_enable returns 0 if the clock is null. There is no
need to check for the compatibles above. Use devm_clk_get_optional
instead of devm_clk_get and everything else can be left as is.
Warm Regards
Thara
> + qce->clks_configured_by_fw = false;
> + else
> + qce->clks_configured_by_fw = true;
> +
> + if (!qce->clks_configured_by_fw) {
> + qce->core = devm_clk_get(qce->dev, "core");
> + if (IS_ERR(qce->core)) {
> + ret = PTR_ERR(qce->core);
> + goto err_out;
> + }
> +
> + qce->iface = devm_clk_get(qce->dev, "iface");
> + if (IS_ERR(qce->iface)) {
> + ret = PTR_ERR(qce->iface);
> + goto err_out;
> + }
> +
> + qce->bus = devm_clk_get(qce->dev, "bus");
> + if (IS_ERR(qce->bus)) {
> + ret = PTR_ERR(qce->bus);
> + goto err_out;
> + }
> +
> + ret = clk_prepare_enable(qce->core);
> + if (ret)
> + goto err_out;
>
> - ret = clk_prepare_enable(qce->iface);
> - if (ret)
> - goto err_clks_core;
> + ret = clk_prepare_enable(qce->iface);
> + if (ret)
> + goto err_clks_core;
>
> - ret = clk_prepare_enable(qce->bus);
> - if (ret)
> - goto err_clks_iface;
> + ret = clk_prepare_enable(qce->bus);
> + if (ret)
> + goto err_clks_iface;
> + }
>
> ret = qce_dma_request(qce->dev, &qce->dma);
> if (ret)
> @@ -268,6 +299,7 @@ static int qce_crypto_probe(struct platform_device *pdev)
> clk_disable_unprepare(qce->iface);
> err_clks_core:
> clk_disable_unprepare(qce->core);
> +err_out:
> return ret;
> }
>
> @@ -284,13 +316,6 @@ static int qce_crypto_remove(struct platform_device *pdev)
> return 0;
> }
>
> -static const struct of_device_id qce_crypto_of_match[] = {
> - { .compatible = "qcom,ipq6018-qce", },
> - { .compatible = "qcom,sdm845-qce", },
> - {}
> -};
> -MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
> -
> static struct platform_driver qce_crypto_driver = {
> .probe = qce_crypto_probe,
> .remove = qce_crypto_remove,
> diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h
> index 228fcd69ec51..d9bf05babecc 100644
> --- a/drivers/crypto/qce/core.h
> +++ b/drivers/crypto/qce/core.h
> @@ -23,6 +23,7 @@
> * @dma: pointer to dma data
> * @burst_size: the crypto burst size
> * @pipe_pair_id: which pipe pair id the device using
> + * @clks_configured_by_fw: clocks are already configured by fw
> * @async_req_enqueue: invoked by every algorithm to enqueue a request
> * @async_req_done: invoked by every algorithm to finish its request
> */
> @@ -39,6 +40,7 @@ struct qce_device {
> struct qce_dma_data dma;
> int burst_size;
> unsigned int pipe_pair_id;
> + bool clks_configured_by_fw;
> int (*async_req_enqueue)(struct qce_device *qce,
> struct crypto_async_request *req);
> void (*async_req_done)(struct qce_device *qce, int ret);
>
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH v3 13/17] crypto: qce: core: Make clocks optional
2021-05-21 2:11 ` Thara Gopinath
@ 2021-06-05 8:31 ` Bhupesh Sharma
0 siblings, 0 replies; 37+ messages in thread
From: Bhupesh Sharma @ 2021-06-05 8:31 UTC (permalink / raw)
To: Thara Gopinath
Cc: linux-arm-msm, Bjorn Andersson, Rob Herring, Andy Gross,
Herbert Xu, David S . Miller, Stephen Boyd, Michael Turquette,
Vinod Koul, dmaengine, linux-clk, linux-crypto, devicetree,
linux-kernel, bhupesh.linux
Hi Thara
On Fri, 21 May 2021 at 07:41, Thara Gopinath <thara.gopinath@linaro.org> wrote:
>
> Hi Bhupesh,
>
> On 5/19/21 10:36 AM, Bhupesh Sharma wrote:
> > From: Thara Gopinath <thara.gopinath@linaro.org>
> >
> > On certain Snapdragon processors, the crypto engine clocks are enabled by
> > default by security firmware and the driver need not handle the
> > clocks. Make acquiring of all the clocks optional in crypto enginer driver
> > so that the driver intializes properly even if no clocks are specified in
> > the dt.
> >
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Andy Gross <agross@kernel.org>
> > Cc: Herbert Xu <herbert@gondor.apana.org.au>
> > Cc: David S. Miller <davem@davemloft.net>
> > Cc: Stephen Boyd <sboyd@kernel.org>
> > Cc: Michael Turquette <mturquette@baylibre.com>
> > Cc: Vinod Koul <vkoul@kernel.org>
> > Cc: dmaengine@vger.kernel.org
> > Cc: linux-clk@vger.kernel.org
> > Cc: linux-crypto@vger.kernel.org
> > Cc: devicetree@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> > Cc: bhupesh.linux@gmail.com
> > Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
> > [ bhupesh.sharma@linaro.org: Make clock enablement optional only for qcom parts where
> > firmware has already initialized them, using a bool variable and fix
> > error paths ]
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> > drivers/crypto/qce/core.c | 89 +++++++++++++++++++++++++--------------
> > drivers/crypto/qce/core.h | 2 +
> > 2 files changed, 59 insertions(+), 32 deletions(-)
> >
> > diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> > index 905378906ac7..8c3c68ba579e 100644
> > --- a/drivers/crypto/qce/core.c
> > +++ b/drivers/crypto/qce/core.c
> > @@ -9,6 +9,7 @@
> > #include <linux/interrupt.h>
> > #include <linux/module.h>
> > #include <linux/mod_devicetable.h>
> > +#include <linux/of_device.h>
> > #include <linux/platform_device.h>
> > #include <linux/spinlock.h>
> > #include <linux/types.h>
> > @@ -184,10 +185,20 @@ static int qce_check_version(struct qce_device *qce)
> > return 0;
> > }
> >
> > +static const struct of_device_id qce_crypto_of_match[] = {
> > + { .compatible = "qcom,ipq6018-qce", },
> > + { .compatible = "qcom,sdm845-qce", },
> > + { .compatible = "qcom,sm8250-qce", },
>
> Adding qcom,sm8250-qce does not belong in this patch. It deserves a
> separate patch of it's own.
Ok, I will fix it in v4.
> > + {}
> > +};
> > +MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
> > +
> > static int qce_crypto_probe(struct platform_device *pdev)
> > {
> > struct device *dev = &pdev->dev;
> > struct qce_device *qce;
> > + const struct of_device_id *of_id =
> > + of_match_device(qce_crypto_of_match, &pdev->dev);
> > int ret;
> >
> > qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL);
> > @@ -198,45 +209,65 @@ static int qce_crypto_probe(struct platform_device *pdev)
> > platform_set_drvdata(pdev, qce);
> >
> > qce->base = devm_platform_ioremap_resource(pdev, 0);
> > - if (IS_ERR(qce->base))
> > - return PTR_ERR(qce->base);
> > + if (IS_ERR(qce->base)) {
> > + ret = PTR_ERR(qce->base);
> > + goto err_out;
> > + }
>
> I don't see the reason for change in error handling here or below. But
> ,for whatever reason this is changed, it has to be a separate patch.
Ok, I will fix it in v4.
> > ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
> > if (ret < 0)
> > - return ret;
> > + goto err_out;
> >
> > qce->mem_path = devm_of_icc_get(qce->dev, "memory");
> > if (IS_ERR(qce->mem_path))
> > return dev_err_probe(dev, PTR_ERR(qce->mem_path),
> > "Failed to get mem path\n");
> >
> > - qce->core = devm_clk_get(qce->dev, "core");
> > - if (IS_ERR(qce->core))
> > - return PTR_ERR(qce->core);
> > -
> > - qce->iface = devm_clk_get(qce->dev, "iface");
> > - if (IS_ERR(qce->iface))
> > - return PTR_ERR(qce->iface);
> > -
> > - qce->bus = devm_clk_get(qce->dev, "bus");
> > - if (IS_ERR(qce->bus))
> > - return PTR_ERR(qce->bus);
> > -
> > ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH);
> > if (ret)
> > - return ret;
> > + goto err_out;
> >
> > - ret = clk_prepare_enable(qce->core);
> > - if (ret)
> > - return ret;
> > + /* On some qcom parts the crypto clocks are already configured by
> > + * the firmware running before linux. In such cases we don't need to
> > + * enable/configure them again. Check here for the same.
> > + */
> > + if (!strcmp(of_id->compatible, "qcom,ipq6018-qce") ||
> > + !strcmp(of_id->compatible, "qcom,sdm845-qce"))
>
> You can avoid this and most of this patch by using
> devm_clk_get_optional. This patch can be like just three lines of code
> change. clk_prepare_enable returns 0 if the clock is null. There is no
> need to check for the compatibles above. Use devm_clk_get_optional
> instead of devm_clk_get and everything else can be left as is.
Ok, I will fix it in v4.
Thanks,
Bhupesh
> Warm Regards
> Thara
>
> > + qce->clks_configured_by_fw = false;
> > + else
> > + qce->clks_configured_by_fw = true;
> > +
> > + if (!qce->clks_configured_by_fw) {
> > + qce->core = devm_clk_get(qce->dev, "core");
> > + if (IS_ERR(qce->core)) {
> > + ret = PTR_ERR(qce->core);
> > + goto err_out;
> > + }
> > +
> > + qce->iface = devm_clk_get(qce->dev, "iface");
> > + if (IS_ERR(qce->iface)) {
> > + ret = PTR_ERR(qce->iface);
> > + goto err_out;
> > + }
> > +
> > + qce->bus = devm_clk_get(qce->dev, "bus");
> > + if (IS_ERR(qce->bus)) {
> > + ret = PTR_ERR(qce->bus);
> > + goto err_out;
> > + }
> > +
> > + ret = clk_prepare_enable(qce->core);
> > + if (ret)
> > + goto err_out;
> >
> > - ret = clk_prepare_enable(qce->iface);
> > - if (ret)
> > - goto err_clks_core;
> > + ret = clk_prepare_enable(qce->iface);
> > + if (ret)
> > + goto err_clks_core;
> >
> > - ret = clk_prepare_enable(qce->bus);
> > - if (ret)
> > - goto err_clks_iface;
> > + ret = clk_prepare_enable(qce->bus);
> > + if (ret)
> > + goto err_clks_iface;
> > + }
> >
> > ret = qce_dma_request(qce->dev, &qce->dma);
> > if (ret)
> > @@ -268,6 +299,7 @@ static int qce_crypto_probe(struct platform_device *pdev)
> > clk_disable_unprepare(qce->iface);
> > err_clks_core:
> > clk_disable_unprepare(qce->core);
> > +err_out:
> > return ret;
> > }
> >
> > @@ -284,13 +316,6 @@ static int qce_crypto_remove(struct platform_device *pdev)
> > return 0;
> > }
> >
> > -static const struct of_device_id qce_crypto_of_match[] = {
> > - { .compatible = "qcom,ipq6018-qce", },
> > - { .compatible = "qcom,sdm845-qce", },
> > - {}
> > -};
> > -MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
> > -
> > static struct platform_driver qce_crypto_driver = {
> > .probe = qce_crypto_probe,
> > .remove = qce_crypto_remove,
> > diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h
> > index 228fcd69ec51..d9bf05babecc 100644
> > --- a/drivers/crypto/qce/core.h
> > +++ b/drivers/crypto/qce/core.h
> > @@ -23,6 +23,7 @@
> > * @dma: pointer to dma data
> > * @burst_size: the crypto burst size
> > * @pipe_pair_id: which pipe pair id the device using
> > + * @clks_configured_by_fw: clocks are already configured by fw
> > * @async_req_enqueue: invoked by every algorithm to enqueue a request
> > * @async_req_done: invoked by every algorithm to finish its request
> > */
> > @@ -39,6 +40,7 @@ struct qce_device {
> > struct qce_dma_data dma;
> > int burst_size;
> > unsigned int pipe_pair_id;
> > + bool clks_configured_by_fw;
> > int (*async_req_enqueue)(struct qce_device *qce,
> > struct crypto_async_request *req);
> > void (*async_req_done)(struct qce_device *qce, int ret);
> >
>
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 14/17] crypto: qce: Print a failure msg in case probe() fails
2021-05-19 14:36 [PATCH v3 00/17] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
` (12 preceding siblings ...)
2021-05-19 14:36 ` [PATCH v3 13/17] crypto: qce: core: Make clocks optional Bhupesh Sharma
@ 2021-05-19 14:36 ` Bhupesh Sharma
2021-05-21 1:55 ` Thara Gopinath
2021-05-19 14:36 ` [PATCH v3 15/17] crypto: qce: Convert the device found dev_dbg() to dev_info() Bhupesh Sharma
` (3 subsequent siblings)
17 siblings, 1 reply; 37+ messages in thread
From: Bhupesh Sharma @ 2021-05-19 14:36 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
Print a failure message (dev_err) in case the qcom qce crypto
driver probe() fails.
Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: dmaengine@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: bhupesh.linux@gmail.com
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
drivers/crypto/qce/core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index 8c3c68ba579e..aecb2cdd79e5 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -300,6 +300,7 @@ static int qce_crypto_probe(struct platform_device *pdev)
err_clks_core:
clk_disable_unprepare(qce->core);
err_out:
+ dev_err(dev, "%s failed : %d\n", __func__, ret);
return ret;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v3 14/17] crypto: qce: Print a failure msg in case probe() fails
2021-05-19 14:36 ` [PATCH v3 14/17] crypto: qce: Print a failure msg in case probe() fails Bhupesh Sharma
@ 2021-05-21 1:55 ` Thara Gopinath
0 siblings, 0 replies; 37+ messages in thread
From: Thara Gopinath @ 2021-05-21 1:55 UTC (permalink / raw)
To: Bhupesh Sharma, linux-arm-msm
Cc: Bjorn Andersson, Rob Herring, Andy Gross, Herbert Xu,
David S . Miller, Stephen Boyd, Michael Turquette, Vinod Koul,
dmaengine, linux-clk, linux-crypto, devicetree, linux-kernel,
bhupesh.linux
On 5/19/21 10:36 AM, Bhupesh Sharma wrote:
> Print a failure message (dev_err) in case the qcom qce crypto
> driver probe() fails.
>
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Herbert Xu <herbert@gondor.apana.org.au>
> Cc: David S. Miller <davem@davemloft.net>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: dmaengine@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-crypto@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: bhupesh.linux@gmail.com
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
I kind of felt you can club patch 14 and 15. But it is upto you..
FWIW,
Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
Warm Regards
Thara
> ---
> drivers/crypto/qce/core.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index 8c3c68ba579e..aecb2cdd79e5 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
> @@ -300,6 +300,7 @@ static int qce_crypto_probe(struct platform_device *pdev)
> err_clks_core:
> clk_disable_unprepare(qce->core);
> err_out:
> + dev_err(dev, "%s failed : %d\n", __func__, ret);
> return ret;
> }
>
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 15/17] crypto: qce: Convert the device found dev_dbg() to dev_info()
2021-05-19 14:36 [PATCH v3 00/17] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
` (13 preceding siblings ...)
2021-05-19 14:36 ` [PATCH v3 14/17] crypto: qce: Print a failure msg in case probe() fails Bhupesh Sharma
@ 2021-05-19 14:36 ` Bhupesh Sharma
2021-05-21 1:50 ` Thara Gopinath
2021-05-19 14:36 ` [PATCH v3 16/17] crypto: qce: Defer probing if BAM dma channel is not yet initialized Bhupesh Sharma
` (2 subsequent siblings)
17 siblings, 1 reply; 37+ messages in thread
From: Bhupesh Sharma @ 2021-05-19 14:36 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
QCE crypto driver is right now too silent even if the probe() is ok
and a valid crypto IP version is found.
Convert the dev_dbg() message to a dev_info() instead.
Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: dmaengine@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: bhupesh.linux@gmail.com
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
drivers/crypto/qce/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index aecb2cdd79e5..8b3e2b4580c2 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -179,7 +179,7 @@ static int qce_check_version(struct qce_device *qce)
*/
qce->pipe_pair_id = qce->dma.rxchan->chan_id >> 1;
- dev_dbg(qce->dev, "Crypto device found, version %d.%d.%d\n",
+ dev_info(qce->dev, "Crypto device found, version %d.%d.%d\n",
major, minor, step);
return 0;
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v3 15/17] crypto: qce: Convert the device found dev_dbg() to dev_info()
2021-05-19 14:36 ` [PATCH v3 15/17] crypto: qce: Convert the device found dev_dbg() to dev_info() Bhupesh Sharma
@ 2021-05-21 1:50 ` Thara Gopinath
0 siblings, 0 replies; 37+ messages in thread
From: Thara Gopinath @ 2021-05-21 1:50 UTC (permalink / raw)
To: Bhupesh Sharma, linux-arm-msm
Cc: Bjorn Andersson, Rob Herring, Andy Gross, Herbert Xu,
David S . Miller, Stephen Boyd, Michael Turquette, Vinod Koul,
dmaengine, linux-clk, linux-crypto, devicetree, linux-kernel,
bhupesh.linux
On 5/19/21 10:36 AM, Bhupesh Sharma wrote:
> QCE crypto driver is right now too silent even if the probe() is ok
> and a valid crypto IP version is found.
>
> Convert the dev_dbg() message to a dev_info() instead.
>
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Herbert Xu <herbert@gondor.apana.org.au>
> Cc: David S. Miller <davem@davemloft.net>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: dmaengine@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-crypto@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: bhupesh.linux@gmail.com
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
Warm Regards
Thara
> ---
> drivers/crypto/qce/core.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index aecb2cdd79e5..8b3e2b4580c2 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
> @@ -179,7 +179,7 @@ static int qce_check_version(struct qce_device *qce)
> */
> qce->pipe_pair_id = qce->dma.rxchan->chan_id >> 1;
>
> - dev_dbg(qce->dev, "Crypto device found, version %d.%d.%d\n",
> + dev_info(qce->dev, "Crypto device found, version %d.%d.%d\n",
> major, minor, step);
>
> return 0;
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 16/17] crypto: qce: Defer probing if BAM dma channel is not yet initialized
2021-05-19 14:36 [PATCH v3 00/17] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
` (14 preceding siblings ...)
2021-05-19 14:36 ` [PATCH v3 15/17] crypto: qce: Convert the device found dev_dbg() to dev_info() Bhupesh Sharma
@ 2021-05-19 14:36 ` Bhupesh Sharma
2021-05-21 1:57 ` Thara Gopinath
2021-05-19 14:37 ` [PATCH v3 17/17] arm64/dts: qcom: sm8250: Add dt entries to support crypto engine Bhupesh Sharma
[not found] ` <162261866806.4130789.17734233133141728573@swboyd.mtv.corp.google.com>
17 siblings, 1 reply; 37+ messages in thread
From: Bhupesh Sharma @ 2021-05-19 14:36 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
Since the Qualcomm qce crypto driver needs the BAM dma driver to be
setup first (to allow crypto operations), it makes sense to defer
the qce crypto driver probing in case the BAM dma driver is not yet
probed.
Move the code leg requesting dma channels earlier in the
probe() flow. This fixes the qce probe failure issues when both qce
and BMA dma are compiled as static part of the kernel.
Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: dmaengine@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: bhupesh.linux@gmail.com
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
drivers/crypto/qce/core.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index 8b3e2b4580c2..207221d5b996 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -218,6 +218,14 @@ static int qce_crypto_probe(struct platform_device *pdev)
if (ret < 0)
goto err_out;
+ /* qce driver requires BAM dma driver to be setup first.
+ * In case the dma channel are not set yet, this check
+ * helps use to return -EPROBE_DEFER earlier.
+ */
+ ret = qce_dma_request(qce->dev, &qce->dma);
+ if (ret)
+ return ret;
+
qce->mem_path = devm_of_icc_get(qce->dev, "memory");
if (IS_ERR(qce->mem_path))
return dev_err_probe(dev, PTR_ERR(qce->mem_path),
@@ -269,10 +277,6 @@ static int qce_crypto_probe(struct platform_device *pdev)
goto err_clks_iface;
}
- ret = qce_dma_request(qce->dev, &qce->dma);
- if (ret)
- goto err_clks;
-
ret = qce_check_version(qce);
if (ret)
goto err_clks;
@@ -287,12 +291,10 @@ static int qce_crypto_probe(struct platform_device *pdev)
ret = qce_register_algs(qce);
if (ret)
- goto err_dma;
+ goto err_clks;
return 0;
-err_dma:
- qce_dma_release(&qce->dma);
err_clks:
clk_disable_unprepare(qce->bus);
err_clks_iface:
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v3 16/17] crypto: qce: Defer probing if BAM dma channel is not yet initialized
2021-05-19 14:36 ` [PATCH v3 16/17] crypto: qce: Defer probing if BAM dma channel is not yet initialized Bhupesh Sharma
@ 2021-05-21 1:57 ` Thara Gopinath
2021-06-05 8:26 ` Bhupesh Sharma
0 siblings, 1 reply; 37+ messages in thread
From: Thara Gopinath @ 2021-05-21 1:57 UTC (permalink / raw)
To: Bhupesh Sharma, linux-arm-msm
Cc: Bjorn Andersson, Rob Herring, Andy Gross, Herbert Xu,
David S . Miller, Stephen Boyd, Michael Turquette, Vinod Koul,
dmaengine, linux-clk, linux-crypto, devicetree, linux-kernel,
bhupesh.linux
On 5/19/21 10:36 AM, Bhupesh Sharma wrote:
> Since the Qualcomm qce crypto driver needs the BAM dma driver to be
> setup first (to allow crypto operations), it makes sense to defer
> the qce crypto driver probing in case the BAM dma driver is not yet
> probed.
>
> Move the code leg requesting dma channels earlier in the
> probe() flow. This fixes the qce probe failure issues when both qce
> and BMA dma are compiled as static part of the kernel.
So, I do not understand what issue you faced with the current code
ordering. When bam dma is not initialized, qce_dma_request will fail and
rest the error path kicks in.
To me the correct ordering for enabling a driver is to turn on clocks
and interconnect before requesting for dma. Unless, there is a specific
issue, I will ask for that order to be maintained.
Warm Regards
Thara
>
> Cc: Thara Gopinath <thara.gopinath@linaro.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Herbert Xu <herbert@gondor.apana.org.au>
> Cc: David S. Miller <davem@davemloft.net>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: dmaengine@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-crypto@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: bhupesh.linux@gmail.com
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
> drivers/crypto/qce/core.c | 16 +++++++++-------
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index 8b3e2b4580c2..207221d5b996 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
> @@ -218,6 +218,14 @@ static int qce_crypto_probe(struct platform_device *pdev)
> if (ret < 0)
> goto err_out;
>
> + /* qce driver requires BAM dma driver to be setup first.
> + * In case the dma channel are not set yet, this check
> + * helps use to return -EPROBE_DEFER earlier.
> + */
> + ret = qce_dma_request(qce->dev, &qce->dma);
> + if (ret)
> + return ret;
> +
> qce->mem_path = devm_of_icc_get(qce->dev, "memory");
> if (IS_ERR(qce->mem_path))
> return dev_err_probe(dev, PTR_ERR(qce->mem_path),
> @@ -269,10 +277,6 @@ static int qce_crypto_probe(struct platform_device *pdev)
> goto err_clks_iface;
> }
>
> - ret = qce_dma_request(qce->dev, &qce->dma);
> - if (ret)
> - goto err_clks;
> -
> ret = qce_check_version(qce);
> if (ret)
> goto err_clks;
> @@ -287,12 +291,10 @@ static int qce_crypto_probe(struct platform_device *pdev)
>
> ret = qce_register_algs(qce);
> if (ret)
> - goto err_dma;
> + goto err_clks;
>
> return 0;
>
> -err_dma:
> - qce_dma_release(&qce->dma);
> err_clks:
> clk_disable_unprepare(qce->bus);
> err_clks_iface:
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v3 16/17] crypto: qce: Defer probing if BAM dma channel is not yet initialized
2021-05-21 1:57 ` Thara Gopinath
@ 2021-06-05 8:26 ` Bhupesh Sharma
0 siblings, 0 replies; 37+ messages in thread
From: Bhupesh Sharma @ 2021-06-05 8:26 UTC (permalink / raw)
To: Thara Gopinath
Cc: linux-arm-msm, Bjorn Andersson, Rob Herring, Andy Gross,
Herbert Xu, David S . Miller, Stephen Boyd, Michael Turquette,
Vinod Koul, dmaengine, linux-clk, linux-crypto, devicetree,
linux-kernel, bhupesh.linux
Hi Thara,
Thanks for the review and sorry for the late reply.
On Fri, 21 May 2021 at 07:27, Thara Gopinath <thara.gopinath@linaro.org> wrote:
>
>
>
> On 5/19/21 10:36 AM, Bhupesh Sharma wrote:
> > Since the Qualcomm qce crypto driver needs the BAM dma driver to be
> > setup first (to allow crypto operations), it makes sense to defer
> > the qce crypto driver probing in case the BAM dma driver is not yet
> > probed.
> >
> > Move the code leg requesting dma channels earlier in the
> > probe() flow. This fixes the qce probe failure issues when both qce
> > and BMA dma are compiled as static part of the kernel.
>
> So, I do not understand what issue you faced with the current code
> ordering. When bam dma is not initialized, qce_dma_request will fail and
> rest the error path kicks in.
> To me the correct ordering for enabling a driver is to turn on clocks
> and interconnect before requesting for dma. Unless, there is a specific
> issue, I will ask for that order to be maintained.
Sure. The problem I faced was the following. Let's consider the
scenario where while the qce crypto driver and the interconnect are
compiled as static parts of the kernel, the bam DMA driver is compiled
as a module, then the -EPROBE_DEFER return leg from the qce crypto
driver is very late in the probe() flow, as we first turn on the
clocks and then the interconnect.
Now the suggested linux deferred probe implementation is to return as
early from the caling driver in case the called driver (subdev) is not
yet ready. SInce the qce crypto driver requires the bam DMA to be set
up first, it makes sense to move 'qce_dma_request' early in the boot
flow. If it's not yet probed(), it probably doesn't make sense to set
up the clks and interconnects yet in the qce driver. We can do it
later when the bam DMA is setup.
I have tested the following combinations with the change I made in
this patchset:
1. qce - static, bam - module, interconnect - module ->
qce_dma_request returned -EPROBE_DEFER
2. qce - static, bam - module, interconnect - static ->
qce_dma_request returned -EPROBE_DEFER
3. qce - static, bam - static, interconnect - module ->
qce_dma_request returned -EPROBE_DEFER
4. qce - static, bam - static, interconnect - static -> no -EPROBE_DEFER
Thanks,
Bhupesh
> > Cc: Thara Gopinath <thara.gopinath@linaro.org>
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Andy Gross <agross@kernel.org>
> > Cc: Herbert Xu <herbert@gondor.apana.org.au>
> > Cc: David S. Miller <davem@davemloft.net>
> > Cc: Stephen Boyd <sboyd@kernel.org>
> > Cc: Michael Turquette <mturquette@baylibre.com>
> > Cc: Vinod Koul <vkoul@kernel.org>
> > Cc: dmaengine@vger.kernel.org
> > Cc: linux-clk@vger.kernel.org
> > Cc: linux-crypto@vger.kernel.org
> > Cc: devicetree@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> > Cc: bhupesh.linux@gmail.com
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> > drivers/crypto/qce/core.c | 16 +++++++++-------
> > 1 file changed, 9 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> > index 8b3e2b4580c2..207221d5b996 100644
> > --- a/drivers/crypto/qce/core.c
> > +++ b/drivers/crypto/qce/core.c
> > @@ -218,6 +218,14 @@ static int qce_crypto_probe(struct platform_device *pdev)
> > if (ret < 0)
> > goto err_out;
> >
> > + /* qce driver requires BAM dma driver to be setup first.
> > + * In case the dma channel are not set yet, this check
> > + * helps use to return -EPROBE_DEFER earlier.
> > + */
> > + ret = qce_dma_request(qce->dev, &qce->dma);
> > + if (ret)
> > + return ret;
> > +
> > qce->mem_path = devm_of_icc_get(qce->dev, "memory");
> > if (IS_ERR(qce->mem_path))
> > return dev_err_probe(dev, PTR_ERR(qce->mem_path),
> > @@ -269,10 +277,6 @@ static int qce_crypto_probe(struct platform_device *pdev)
> > goto err_clks_iface;
> > }
> >
> > - ret = qce_dma_request(qce->dev, &qce->dma);
> > - if (ret)
> > - goto err_clks;
> > -
> > ret = qce_check_version(qce);
> > if (ret)
> > goto err_clks;
> > @@ -287,12 +291,10 @@ static int qce_crypto_probe(struct platform_device *pdev)
> >
> > ret = qce_register_algs(qce);
> > if (ret)
> > - goto err_dma;
> > + goto err_clks;
> >
> > return 0;
> >
> > -err_dma:
> > - qce_dma_release(&qce->dma);
> > err_clks:
> > clk_disable_unprepare(qce->bus);
> > err_clks_iface:
> >
>
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 17/17] arm64/dts: qcom: sm8250: Add dt entries to support crypto engine.
2021-05-19 14:36 [PATCH v3 00/17] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
` (15 preceding siblings ...)
2021-05-19 14:36 ` [PATCH v3 16/17] crypto: qce: Defer probing if BAM dma channel is not yet initialized Bhupesh Sharma
@ 2021-05-19 14:37 ` Bhupesh Sharma
[not found] ` <162261866806.4130789.17734233133141728573@swboyd.mtv.corp.google.com>
17 siblings, 0 replies; 37+ messages in thread
From: Bhupesh Sharma @ 2021-05-19 14:37 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Stephen Boyd,
Michael Turquette, Vinod Koul, dmaengine, linux-clk,
linux-crypto, devicetree, linux-kernel, bhupesh.linux
Add crypto engine (CE) and CE BAM related nodes and definitions to
"sm8250.dtsi".
Cc: Thara Gopinath <thara.gopinath@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: dmaengine@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: bhupesh.linux@gmail.com
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 4c0de12aaba6..6700d609a7b8 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3796,6 +3796,34 @@ cpufreq_hw: cpufreq@18591000 {
#freq-domain-cells = <1>;
};
+
+ cryptobam: dma@1dc4000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0 0x01dc4000 0 0x24000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely = <1>;
+ iommus = <&apps_smmu 0x584 0x0011>,
+ <&apps_smmu 0x586 0x0011>,
+ <&apps_smmu 0x594 0x0011>,
+ <&apps_smmu 0x596 0x0011>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
+ interconnect-names = "memory";
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,sm8250-qce";
+ reg = <0 0x01dfa000 0 0x6000>;
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x584 0x0011>,
+ <&apps_smmu 0x586 0x0011>,
+ <&apps_smmu 0x594 0x0011>,
+ <&apps_smmu 0x596 0x0011>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
+ interconnect-names = "memory";
+ };
};
timer {
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread[parent not found: <162261866806.4130789.17734233133141728573@swboyd.mtv.corp.google.com>]
* Re: [PATCH v3 00/17] Enable Qualcomm Crypto Engine on sm8250
[not found] ` <162261866806.4130789.17734233133141728573@swboyd.mtv.corp.google.com>
@ 2021-06-04 3:18 ` Bhupesh Sharma
0 siblings, 0 replies; 37+ messages in thread
From: Bhupesh Sharma @ 2021-06-04 3:18 UTC (permalink / raw)
To: Stephen Boyd
Cc: linux-arm-msm, Thara Gopinath, Bjorn Andersson, Rob Herring,
Andy Gross, Herbert Xu, David S . Miller, Michael Turquette,
Vinod Koul, dmaengine, linux-clk, linux-crypto, devicetree,
linux-kernel, bhupesh.linux
Hi Stephen,
On Wed, 2 Jun 2021 at 12:54, Stephen Boyd <sboyd@kernel.org> wrote:
>
> Quoting Bhupesh Sharma (2021-05-19 07:36:43)
> >
> > Cc: Thara Gopinath <thara.gopinath@linaro.org>
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Andy Gross <agross@kernel.org>
> > Cc: Herbert Xu <herbert@gondor.apana.org.au>
> > Cc: David S. Miller <davem@davemloft.net>
> > Cc: Stephen Boyd <sboyd@kernel.org>
> > Cc: Michael Turquette <mturquette@baylibre.com>
> > Cc: Vinod Koul <vkoul@kernel.org>
> > Cc: dmaengine@vger.kernel.org
> > Cc: linux-clk@vger.kernel.org
>
> Can you stop Cc-ing the clk list? It puts it into my review queue when
> as far as I can tell there isn't anything really clk related to review
> here. Or do you need an ack on something?
Sure, I will drop the clk-list from Cc-list of future patchset versions.
Since I had a couple of clk driver changes in v1 which were dropped
starting from v2, I thought it would be good to Cc clk-list for v2
(and so on..)
Thanks,
Bhupesh
^ permalink raw reply [flat|nested] 37+ messages in thread