From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B17FC43460 for ; Fri, 21 May 2021 10:42:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4A265613D8 for ; Fri, 21 May 2021 10:42:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231493AbhEUKnZ (ORCPT ); Fri, 21 May 2021 06:43:25 -0400 Received: from mail.kernel.org ([198.145.29.99]:37268 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230480AbhEUKnY (ORCPT ); Fri, 21 May 2021 06:43:24 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 9B4FD6008E; Fri, 21 May 2021 10:41:58 +0000 (UTC) Date: Fri, 21 May 2021 11:41:56 +0100 From: Catalin Marinas To: Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Marc Zyngier , Greg Kroah-Hartman , Peter Zijlstra , Morten Rasmussen , Qais Yousef , Suren Baghdasaryan , Quentin Perret , Tejun Heo , Li Zefan , Johannes Weiner , Ingo Molnar , Juri Lelli , Vincent Guittot , "Rafael J. Wysocki" , kernel-team@android.com Subject: Re: [PATCH v6 02/21] arm64: Allow mismatched 32-bit EL0 support Message-ID: <20210521104155.GC6675@arm.com> References: <20210518094725.7701-1-will@kernel.org> <20210518094725.7701-3-will@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210518094725.7701-3-will@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 18, 2021 at 10:47:06AM +0100, Will Deacon wrote: > +static int enable_mismatched_32bit_el0(unsigned int cpu) > +{ > + struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); > + bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); > + > + if (cpu_32bit) { > + cpumask_set_cpu(cpu, cpu_32bit_el0_mask); > + static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); It may be worth only calling static_branch_enable_cpuslocked() if not already set, in case you try this on a system with lots of CPUs. -- Catalin