From: Michael Walle <michael@walle.cc>
To: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: Tudor Ambarus <tudor.ambarus@microchip.com>,
Michael Walle <michael@walle.cc>, Pratyush Yadav <p.yadav@ti.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>
Subject: [PATCH v4 1/4] mtd: spi-nor: otp: fix access to security registers in 4 byte mode
Date: Fri, 21 May 2021 21:40:31 +0200 [thread overview]
Message-ID: <20210521194034.15249-2-michael@walle.cc> (raw)
In-Reply-To: <20210521194034.15249-1-michael@walle.cc>
The security registers either take a 3 byte or a 4 byte address offset,
depending on the address mode of the flash. Thus just leave the
nor->addr_width as is.
Fixes: cad3193fe9d1 ("mtd: spi-nor: implement OTP support for Winbond and similar flashes")
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
---
drivers/mtd/spi-nor/otp.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/otp.c b/drivers/mtd/spi-nor/otp.c
index 61036c716abb..91a4c510ed51 100644
--- a/drivers/mtd/spi-nor/otp.c
+++ b/drivers/mtd/spi-nor/otp.c
@@ -40,7 +40,6 @@ int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, size_t len, u8 *buf)
rdesc = nor->dirmap.rdesc;
nor->read_opcode = SPINOR_OP_RSECR;
- nor->addr_width = 3;
nor->read_dummy = 8;
nor->read_proto = SNOR_PROTO_1_1_1;
nor->dirmap.rdesc = NULL;
@@ -84,7 +83,6 @@ int spi_nor_otp_write_secr(struct spi_nor *nor, loff_t addr, size_t len,
wdesc = nor->dirmap.wdesc;
nor->program_opcode = SPINOR_OP_PSECR;
- nor->addr_width = 3;
nor->write_proto = SNOR_PROTO_1_1_1;
nor->dirmap.wdesc = NULL;
--
2.20.1
next prev parent reply other threads:[~2021-05-21 19:40 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-21 19:40 [PATCH v4 0/4] mtd: spi-nor: otp: 4 byte mode fix and erase support Michael Walle
2021-05-21 19:40 ` Michael Walle [this message]
2021-05-31 8:27 ` [PATCH v4 1/4] mtd: spi-nor: otp: fix access to security registers in 4 byte mode Tudor.Ambarus
2021-05-21 19:40 ` [PATCH v4 2/4] mtd: spi-nor: otp: use more consistent wording Michael Walle
2021-05-31 8:28 ` Tudor.Ambarus
2021-05-21 19:40 ` [PATCH v4 3/4] mtd: spi-nor: otp: return -EROFS if region is read-only Michael Walle
2021-05-25 19:33 ` Pratyush Yadav
2021-05-26 10:41 ` Michael Walle
2021-05-26 11:13 ` Pratyush Yadav
2021-05-31 8:52 ` Tudor.Ambarus
2021-06-01 13:02 ` Michael Walle
2021-06-03 5:22 ` Tudor.Ambarus
2021-05-21 19:40 ` [PATCH v4 4/4] mtd: spi-nor: otp: implement erase for Winbond and similar flashes Michael Walle
2021-05-25 19:37 ` Pratyush Yadav
2021-05-31 8:56 ` Tudor.Ambarus
2021-06-01 13:30 ` Michael Walle
2021-06-03 5:08 ` Tudor.Ambarus
2021-06-03 5:30 ` Tudor.Ambarus
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