From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: <ira.weiny@intel.com>
Cc: Ben Widawsky <ben.widawsky@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
<linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 1/5] cxl/mem: Introduce cxl_decode_register_block()
Date: Tue, 25 May 2021 10:53:04 +0100 [thread overview]
Message-ID: <20210525105304.000029b8@Huawei.com> (raw)
In-Reply-To: <20210522001154.2680157-2-ira.weiny@intel.com>
On Fri, 21 May 2021 17:11:50 -0700
<ira.weiny@intel.com> wrote:
> From: Ira Weiny <ira.weiny@intel.com>
>
> Each register block located in the DVSEC needs to be decoded from 2
> words, 'register offset high' and 'register offset low'.
>
> Create a function, cxl_decode_register_block() to perform this decode
> and return the bar, offset, and register type of the register block.
>
> Then use the values decoded in cxl_mem_map_regblock() instead of passing
> the raw registers.
>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Makes sense to factor this out.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> ---
> Changes for V2:
> Push this to the start of the series
> ---
> drivers/cxl/pci.c | 26 ++++++++++++++++++--------
> 1 file changed, 18 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 8bdae74d7d78..b2f978954daa 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -922,17 +922,13 @@ static struct cxl_mem *cxl_mem_create(struct pci_dev *pdev)
> return cxlm;
> }
>
> -static void __iomem *cxl_mem_map_regblock(struct cxl_mem *cxlm, u32 reg_lo, u32 reg_hi)
> +static void __iomem *cxl_mem_map_regblock(struct cxl_mem *cxlm,
> + u8 bar, u64 offset)
> {
> struct pci_dev *pdev = cxlm->pdev;
> struct device *dev = &pdev->dev;
> - u64 offset;
> - u8 bar;
> int rc;
>
> - offset = ((u64)reg_hi << 32) | (reg_lo & CXL_REGLOC_ADDR_MASK);
> - bar = FIELD_GET(CXL_REGLOC_BIR_MASK, reg_lo);
> -
> /* Basic sanity check that BAR is big enough */
> if (pci_resource_len(pdev, bar) < offset) {
> dev_err(dev, "BAR%d: %pr: too small (offset: %#llx)\n", bar,
> @@ -974,6 +970,14 @@ static int cxl_mem_dvsec(struct pci_dev *pdev, int dvsec)
> return 0;
> }
>
> +static void cxl_decode_register_block(u32 reg_lo, u32 reg_hi,
> + u8 *bar, u64 *offset, u8 *reg_type)
> +{
> + *offset = ((u64)reg_hi << 32) | (reg_lo & CXL_REGLOC_ADDR_MASK);
> + *bar = FIELD_GET(CXL_REGLOC_BIR_MASK, reg_lo);
> + *reg_type = FIELD_GET(CXL_REGLOC_RBI_MASK, reg_lo);
> +}
> +
> /**
> * cxl_mem_setup_regs() - Setup necessary MMIO.
> * @cxlm: The CXL memory device to communicate with.
> @@ -1009,15 +1013,21 @@ static int cxl_mem_setup_regs(struct cxl_mem *cxlm)
> for (i = 0; i < regblocks; i++, regloc += 8) {
> u32 reg_lo, reg_hi;
> u8 reg_type;
> + u64 offset;
> + u8 bar;
>
> /* "register low and high" contain other bits */
> pci_read_config_dword(pdev, regloc, ®_lo);
> pci_read_config_dword(pdev, regloc + 4, ®_hi);
>
> - reg_type = FIELD_GET(CXL_REGLOC_RBI_MASK, reg_lo);
> + cxl_decode_register_block(reg_lo, reg_hi, &bar, &offset,
> + ®_type);
> +
> + dev_dbg(dev, "Found register block in bar %u @ 0x%llx of type %u\n",
> + bar, offset, reg_type);
>
> if (reg_type == CXL_REGLOC_RBI_MEMDEV) {
> - base = cxl_mem_map_regblock(cxlm, reg_lo, reg_hi);
> + base = cxl_mem_map_regblock(cxlm, bar, offset);
> if (IS_ERR(base))
> return PTR_ERR(base);
> break;
next prev parent reply other threads:[~2021-05-25 9:55 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-22 0:11 [PATCH v2 0/5] Map register blocks individually ira.weiny
2021-05-22 0:11 ` [PATCH v2 1/5] cxl/mem: Introduce cxl_decode_register_block() ira.weiny
2021-05-25 9:53 ` Jonathan Cameron [this message]
2021-05-22 0:11 ` [PATCH v2 2/5] cxl/mem: Reserve all device regions at once ira.weiny
2021-05-25 9:54 ` Jonathan Cameron
2021-05-22 0:11 ` [PATCH v2 3/5] cxl/mem: Map registers based on capabilities ira.weiny
2021-05-25 9:52 ` Jonathan Cameron
2021-05-27 17:53 ` Ira Weiny
2021-05-22 0:11 ` [PATCH v2 4/5] cxl/mem: Reserve individual register block regions ira.weiny
2021-05-25 9:59 ` Jonathan Cameron
2021-05-22 0:11 ` [PATCH v2 5/5] cxl: Add HDM decoder capbilities ira.weiny
2021-05-25 14:28 ` Jonathan Cameron
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