From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A41C3C47084 for ; Tue, 25 May 2021 12:15:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 853CE6141D for ; Tue, 25 May 2021 12:15:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232369AbhEYMQj (ORCPT ); Tue, 25 May 2021 08:16:39 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:37888 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232281AbhEYMQe (ORCPT ); Tue, 25 May 2021 08:16:34 -0400 X-UUID: a44b703372804068bf0c60f5bfe076c5-20210525 X-UUID: a44b703372804068bf0c60f5bfe076c5-20210525 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1469816558; Tue, 25 May 2021 20:14:58 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 25 May 2021 20:14:57 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 25 May 2021 20:14:57 +0800 From: Rex-BC Chen To: , CC: , , , , , Rex-BC Chen , Jitao Shi Subject: [v4,PATCH 2/3] drm/mediatek: config driver data to support dual edge sample Date: Tue, 25 May 2021 20:14:47 +0800 Message-ID: <20210525121448.30075-3-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210525121448.30075-1-rex-bc.chen@mediatek.com> References: <20210525121448.30075-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add output_fmts and num_output_fmts value for all configuration. Signed-off-by: Jitao Shi Signed-off-by: Rex-BC Chen --- drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index d3b883c97aaf..d6a422986efc 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -695,10 +695,21 @@ static unsigned int mt8183_calculate_factor(int clock) return 2; } +static const u32 mt8173_output_fmts[] = { +MEDIA_BUS_FMT_RGB888_1X24, +}; + +static const u32 mt8183_output_fmts[] = { +MEDIA_BUS_FMT_RGB888_2X12_LE, +MEDIA_BUS_FMT_RGB888_2X12_BE, +}; + static const struct mtk_dpi_conf mt8173_conf = { .cal_factor = mt8173_calculate_factor, .reg_h_fre_con = 0xe0, .max_clock_khz = 300000, + .output_fmts = mt8173_output_fmts, + .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), }; static const struct mtk_dpi_conf mt2701_conf = { @@ -706,18 +717,24 @@ static const struct mtk_dpi_conf mt2701_conf = { .reg_h_fre_con = 0xb0, .edge_sel_en = true, .max_clock_khz = 150000, + .output_fmts = mt8173_output_fmts, + .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), }; static const struct mtk_dpi_conf mt8183_conf = { .cal_factor = mt8183_calculate_factor, .reg_h_fre_con = 0xe0, .max_clock_khz = 100000, + .output_fmts = mt8183_output_fmts, + .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), }; static const struct mtk_dpi_conf mt8192_conf = { .cal_factor = mt8183_calculate_factor, .reg_h_fre_con = 0xe0, .max_clock_khz = 150000, + .output_fmts = mt8173_output_fmts, + .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), }; static int mtk_dpi_probe(struct platform_device *pdev) -- 2.18.0