From: Dmitry Osipenko <digetx@gmail.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Michał Mirosław" <mirq-linux@rere.qmqm.pl>,
"Nikola Milosavljević" <mnidza@outlook.com>,
"Ulf Hansson" <ulf.hansson@linaro.org>,
"Peter Geis" <pgwipeout@gmail.com>,
"Nicolas Chauvet" <kwizart@gmail.com>,
"Viresh Kumar" <vireshk@kernel.org>,
"Stephen Boyd" <sboyd@kernel.org>,
"Matt Merhar" <mattmerhar@protonmail.com>,
"Paul Fertser" <fercerpav@gmail.com>,
"Mark Brown" <broonie@kernel.org>,
"Liam Girdwood" <lgirdwood@gmail.com>,
"Krzysztof Kozlowski" <krzysztof.kozlowski@canonical.com>,
"Mikko Perttunen" <mperttunen@nvidia.com>
Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org,
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
Nathan Chancellor <nathan@kernel.org>,
linux-clk@vger.kernel.org
Subject: [PATCH v4 11/14] dt-bindings: soc: tegra-pmc: Document core power domain
Date: Fri, 28 May 2021 00:43:14 +0300 [thread overview]
Message-ID: <20210527214317.31014-12-digetx@gmail.com> (raw)
In-Reply-To: <20210527214317.31014-1-digetx@gmail.com>
All NVIDIA Tegra SoCs have a core power domain where majority of hardware
blocks reside. Document the new core power domain properties.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
.../arm/tegra/nvidia,tegra20-pmc.yaml | 35 +++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index 43fd2f8927d0..0afec83cc723 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -301,6 +301,33 @@ patternProperties:
additionalProperties: false
+ core-domain:
+ type: object
+ description: |
+ The vast majority of hardware blocks of Tegra SoC belong to a
+ Core power domain, which has a dedicated voltage rail that powers
+ the blocks.
+
+ properties:
+ operating-points-v2:
+ description:
+ Should contain level, voltages and opp-supported-hw property.
+ The supported-hw is a bitfield indicating SoC speedo or process
+ ID mask.
+
+ "#power-domain-cells":
+ const: 0
+
+ required:
+ - operating-points-v2
+ - "#power-domain-cells"
+
+ additionalProperties: false
+
+ core-supply:
+ description:
+ Phandle to voltage regulator connected to the SoC Core power rail.
+
required:
- compatible
- reg
@@ -325,6 +352,7 @@ examples:
tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra210-pmc";
reg = <0x7000e400 0x400>;
+ core-supply = <®ulator>;
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
#clock-cells = <1>;
@@ -338,17 +366,24 @@ examples:
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
+ pd_core: core-domain {
+ operating-points-v2 = <&core_opp_table>;
+ #power-domain-cells = <0>;
+ };
+
powergates {
pd_audio: aud {
clocks = <&tegra_car TEGRA210_CLK_APE>,
<&tegra_car TEGRA210_CLK_APB2APE>;
resets = <&tegra_car 198>;
+ power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_xusbss: xusba {
clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
+ power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
};
--
2.30.2
next prev parent reply other threads:[~2021-05-27 21:44 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-27 21:43 [PATCH v4 00/14] NVIDIA Tegra memory and power management changes for 5.14 Dmitry Osipenko
2021-05-27 21:43 ` [PATCH v4 01/14] regulator: core: Add regulator_sync_voltage_rdev() Dmitry Osipenko
2021-05-27 21:43 ` [PATCH v4 02/14] soc/tegra: regulators: Bump voltages on system reboot Dmitry Osipenko
2021-05-27 21:43 ` [PATCH v4 03/14] soc/tegra: Add stub for soc_is_tegra() Dmitry Osipenko
2021-05-27 21:43 ` [PATCH v4 04/14] soc/tegra: Add devm_tegra_core_dev_init_opp_table() Dmitry Osipenko
2021-05-27 21:43 ` [PATCH v4 05/14] soc/tegra: fuse: Add stubs needed for compile-testing Dmitry Osipenko
2021-05-27 21:43 ` [PATCH v4 06/14] clk: tegra: " Dmitry Osipenko
2021-05-27 21:43 ` [PATCH v4 07/14] memory: tegra: Fix compilation warnings on 64bit platforms Dmitry Osipenko
2021-05-27 21:43 ` [PATCH v4 08/14] memory: tegra: Enable compile testing for all drivers Dmitry Osipenko
2021-05-27 21:43 ` [PATCH v4 09/14] memory: tegra20-emc: Use devm_tegra_core_dev_init_opp_table() Dmitry Osipenko
2021-05-27 21:43 ` [PATCH v4 10/14] memory: tegra30-emc: " Dmitry Osipenko
2021-05-27 21:43 ` Dmitry Osipenko [this message]
2021-05-27 21:43 ` [PATCH v4 12/14] soc/tegra: pmc: Add core power domain Dmitry Osipenko
2021-05-27 21:43 ` [PATCH v4 13/14] soc/tegra: pmc: Add driver state syncing Dmitry Osipenko
2021-05-27 21:43 ` [PATCH v4 14/14] soc/tegra: regulators: Support core domain " Dmitry Osipenko
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