From: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
To: jassisinghbrar@gmail.com, robh+dt@kernel.org,
shawnguo@kernel.org, s.hauer@pengutronix.de,
o.rempel@pengutronix.de
Cc: kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com,
linux-imx@nxp.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Peng Fan <peng.fan@nxp.com>
Subject: [PATCH V2 0/4] mailbox: imx: add i.MX8ULP MU support
Date: Fri, 28 May 2021 18:05:59 +0800 [thread overview]
Message-ID: <20210528100603.21759-1-peng.fan@oss.nxp.com> (raw)
From: Peng Fan <peng.fan@nxp.com>
V2:
Add A-b from Rob in patch 1
Fix RXDB for i.MX8ULP in patch 4
i.MX8ULP generic MU is a different IP compared with previous i.MX chips.
It has different register layout and bit position, but the register name
and bit definitions are almost same with previous i.MX MU.
So we extend the current imx-mailbox driver to support i.MX8ULP.
Peng Fan (4):
dt-bindings: mailbox: imx-mu: add i.MX8ULP MU support
mailbox: imx: replace the xTR/xRR array with single register
mailbox: imx: add xSR/xCR register array
mailbox: imx-mailbox: support i.MX8ULP MU
.../devicetree/bindings/mailbox/fsl,mu.yaml | 1 +
drivers/mailbox/imx-mailbox.c | 196 +++++++++++-------
2 files changed, 123 insertions(+), 74 deletions(-)
--
2.30.0
next reply other threads:[~2021-05-28 9:33 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-28 10:05 Peng Fan (OSS) [this message]
2021-05-28 10:06 ` [PATCH V2 1/4] dt-bindings: mailbox: imx-mu: add i.MX8ULP MU support Peng Fan (OSS)
2021-05-28 10:06 ` [PATCH V2 2/4] mailbox: imx: replace the xTR/xRR array with single register Peng Fan (OSS)
2021-05-28 10:06 ` [PATCH V2 3/4] mailbox: imx: add xSR/xCR register array Peng Fan (OSS)
2021-05-28 10:06 ` [PATCH V2 4/4] mailbox: imx-mailbox: support i.MX8ULP MU Peng Fan (OSS)
2021-06-22 1:04 ` [PATCH V2 0/4] mailbox: imx: add i.MX8ULP MU support Peng Fan
2021-06-22 1:07 ` Peng Fan
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