From: Paul Cercueil <paul@crapouillou.net>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: "Rob Herring" <robh+dt@kernel.org>,
周琰杰 <zhouyanjie@wanyeetech.com>,
linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, list@opendingux.net,
"Paul Cercueil" <paul@crapouillou.net>
Subject: [PATCH 1/8] MIPS: mm: XBurst CPU requires sync after DMA
Date: Sun, 30 May 2021 18:17:55 +0100 [thread overview]
Message-ID: <20210530171802.23649-2-paul@crapouillou.net> (raw)
In-Reply-To: <20210530171802.23649-1-paul@crapouillou.net>
I am not sure why this is required, but if this is not enabled, reading
from a buffer in which data has been DMA'd may read incorrect values.
This used to happen for instance in mmc_app_send_scr()
(drivers/mmc/core/sd_ops.c), where data is DMA'd to a buffer then copied
by the CPU to a different location.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
arch/mips/Kconfig | 1 +
arch/mips/mm/dma-noncoherent.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ed51970c08e7..310ce50ad285 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -112,6 +112,7 @@ config MACH_INGENIC
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_ZBOOT
select DMA_NONCOHERENT
+ select ARCH_HAS_SYNC_DMA_FOR_CPU
select IRQ_MIPS_CPU
select PINCTRL
select GPIOLIB
diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
index 212f3ce75a6b..3c4fc97b9f39 100644
--- a/arch/mips/mm/dma-noncoherent.c
+++ b/arch/mips/mm/dma-noncoherent.c
@@ -32,6 +32,7 @@ static inline bool cpu_needs_post_dma_flush(void)
case CPU_R12000:
case CPU_BMIPS5000:
case CPU_LOONGSON2EF:
+ case CPU_XBURST:
return true;
default:
/*
--
2.30.2
next prev parent reply other threads:[~2021-05-30 17:18 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-30 17:17 [PATCH 0/8] Misc Ingenic patches Paul Cercueil
2021-05-30 17:17 ` Paul Cercueil [this message]
2021-05-30 17:17 ` [PATCH 2/8] MIPS: boot: Support specifying UART port on Ingenic SoCs Paul Cercueil
2021-05-30 17:17 ` [PATCH 3/8] MIPS: cpu-probe: Fix FPU detection on Ingenic JZ4760(B) Paul Cercueil
2021-05-30 17:17 ` [PATCH 4/8] MIPS: Kconfig: ingenic: Ensure MACH_INGENIC_GENERIC selects all SoCs Paul Cercueil
2021-05-30 17:17 ` [PATCH 5/8] MIPS: ingenic: Select CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER Paul Cercueil
2021-05-30 17:18 ` [PATCH 6/8] MIPS: ingenic: jz4780: Fix I2C nodes to match DT doc Paul Cercueil
2021-05-30 17:18 ` [PATCH 7/8] MIPS: ingenic: gcw0: Set codec to cap-less mode for FM radio Paul Cercueil
2021-05-30 17:18 ` [PATCH 8/8] MIPS: ingenic: rs90: Add dedicated VRAM memory region Paul Cercueil
2021-06-01 9:49 ` [PATCH 0/8] Misc Ingenic patches Thomas Bogendoerfer
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