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[18.167.84.74]) by smtp.gmail.com with ESMTPSA id u4sm12638544pgl.43.2021.05.31.20.21.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 May 2021 20:21:47 -0700 (PDT) Date: Tue, 1 Jun 2021 11:21:43 +0800 From: Leo Yan To: Peter Zijlstra Cc: Adrian Hunter , Arnaldo Carvalho de Melo , Ingo Molnar , Mark Rutland , Alexander Shishkin , Namhyung Kim , Andi Kleen , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 1/2] perf auxtrace: Change to use SMP memory barriers Message-ID: <20210601032143.GA10026@leoy-ThinkPad-X240s> References: <20210519140319.1673043-1-leo.yan@linaro.org> <3c7dcd5d-fddd-5d3b-81ac-cb7b615b0338@intel.com> <7cdc3578-a50e-89ef-477a-3dc1f84f96bb@intel.com> <20210531145302.GC9324@leoy-ThinkPad-X240s> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, May 31, 2021 at 05:48:03PM +0200, Peter Zijlstra wrote: > On Mon, May 31, 2021 at 10:53:02PM +0800, Leo Yan wrote: > > Hi Peter, Adrian, > > > > On Thu, May 27, 2021 at 11:57:37AM +0200, Peter Zijlstra wrote: > > > On Thu, May 27, 2021 at 12:24:15PM +0300, Adrian Hunter wrote: > > > > > > > > If all we want is a compiler barrier, then shouldn't that be what we use? > > > > > i.e. barrier() > > > > Sorry for a bit late. Just bring up one question before I respin > > this patch set. > > > > > > I guess you are saying we still need to stop potential re-ordering across > > > > CPUs, so please ignore my comments. > > > > > > Right; so the ordering issue is real, consider: > > > > > > CPU0 (kernel) CPU1 (user) > > > > > > write data read head > > > smp_wmb() smp_rmb() > > > write head read data > > > > One thing should be mentioned is the Linux kernel has _not_ used an > > explict "smb_wmb()" between writing AUX trace data and updating header > > "aux_head". Please see the function perf_aux_output_end(): > > I think we pushed that into the driver. There is nothing the generic > code can do here. > > It is the drivers responsibility of ensuring the data is stable before > calling perf_aux_output_end() or something along those lines. Thanks for explaination. I reviewed the drivers, some of them have used memory barriers (e.g. Intel-PT, Arm SPE), but some drivers miss to use memory barriers before calling perf_aux_output_end() (Like Arm CoreSight, Intel-bts). Will address this issue in next patch set. Thanks, Leo