From: Pratyush Yadav <p.yadav@ti.com>
To: Michael Walle <michael@walle.cc>
Cc: Tudor Ambarus <tudor.ambarus@microchip.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Mark Brown <broonie@kernel.org>, <linux-mtd@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>
Subject: Re: [PATCH v2 2/6] mtd: spi-nor: spansion: write 2 bytes when disabling Octal DTR mode
Date: Wed, 2 Jun 2021 13:12:14 +0530 [thread overview]
Message-ID: <20210602074212.o4dmwry747wortsq@ti.com> (raw)
In-Reply-To: <f875025538713a005b1c18f8eb5c24c0@walle.cc>
On 01/06/21 02:47PM, Michael Walle wrote:
> Am 2021-05-31 20:17, schrieb Pratyush Yadav:
> > The Octal DTR configuration is stored in the CFR5V register. This
> > register is 1 byte wide. But 1 byte long transactions are not allowed in
> > 8D-8D-8D mode. Since the next byte address does not contain any
> > register, it is safe to write any value to it. Write a 0 to it.
> >
> > Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> > ---
>
> Can't say much, because there is no public datasheet, is there?
https://www.cypress.com/file/513996/download
>
> But looks sane. Same for patch 3/6.
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
next prev parent reply other threads:[~2021-06-02 7:42 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-31 18:17 [PATCH v2 0/6] Avoid odd length/address read/writes in 8D-8D-8D mode Pratyush Yadav
2021-05-31 18:17 ` [PATCH v2 1/6] mtd: spi-nor: core: use 2 data bytes for template ops Pratyush Yadav
2021-06-01 12:36 ` Michael Walle
2021-05-31 18:17 ` [PATCH v2 2/6] mtd: spi-nor: spansion: write 2 bytes when disabling Octal DTR mode Pratyush Yadav
2021-06-01 12:47 ` Michael Walle
2021-06-02 7:42 ` Pratyush Yadav [this message]
2021-12-23 13:06 ` Tudor.Ambarus
2021-12-23 13:11 ` Tudor.Ambarus
2021-12-23 13:24 ` Tudor.Ambarus
2021-05-31 18:17 ` [PATCH v2 3/6] mtd: spi-nor: micron-st: " Pratyush Yadav
2021-05-31 18:17 ` [PATCH v2 4/6] spi: spi-mem: reject partial cycle transfers in 8D-8D-8D mode Pratyush Yadav
2021-12-23 11:43 ` Tudor.Ambarus
2021-12-23 11:47 ` Pratyush Yadav
2021-05-31 18:17 ` [PATCH v2 5/6] mtd: spi-nor: core: avoid odd length/address reads on " Pratyush Yadav
2021-12-23 12:42 ` Tudor.Ambarus
2021-05-31 18:17 ` [PATCH v2 6/6] mtd: spi-nor: core: avoid odd length/address writes in " Pratyush Yadav
2021-06-01 12:44 ` Michael Walle
2021-12-23 12:59 ` Tudor.Ambarus
2021-12-23 13:31 ` (subset) Re: [PATCH v2 0/6] Avoid odd length/address read/writes " Tudor Ambarus
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