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From: Vladimir Oltean <vladimir.oltean@nxp.com>
To: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
Cc: "Jose.Abreu@synopsys.com" <Jose.Abreu@synopsys.com>,
	"andrew@lunn.ch" <andrew@lunn.ch>,
	"hkallweit1@gmail.com" <hkallweit1@gmail.com>,
	"linux@armlinux.org.uk" <linux@armlinux.org.uk>,
	"kuba@kernel.org" <kuba@kernel.org>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	"peppe.cavallaro@st.com" <peppe.cavallaro@st.com>,
	"alexandre.torgue@foss.st.com" <alexandre.torgue@foss.st.com>,
	"davem@davemloft.net" <davem@davemloft.net>,
	"mcoquelin.stm32@gmail.com" <mcoquelin.stm32@gmail.com>,
	"weifeng.voon@intel.com" <weifeng.voon@intel.com>,
	"boon.leong.ong@intel.com" <boon.leong.ong@intel.com>,
	"tee.min.tan@intel.com" <tee.min.tan@intel.com>,
	"vee.khee.wong@linux.intel.com" <vee.khee.wong@linux.intel.com>,
	"vee.khee.wong@intel.com" <vee.khee.wong@intel.com>,
	"linux-stm32@st-md-mailman.stormreply.com" 
	<linux-stm32@st-md-mailman.stormreply.com>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [RESEND PATCH net-next v5 3/3] net: stmmac: enable Intel mGbE 2.5Gbps link speed
Date: Fri, 4 Jun 2021 12:02:48 +0000	[thread overview]
Message-ID: <20210604120247.gzrjocyw5ivtdhrd@skbuf> (raw)
In-Reply-To: <20210604105733.31092-4-michael.wei.hong.sit@intel.com>

On Fri, Jun 04, 2021 at 06:57:33PM +0800, Michael Sit Wei Hong wrote:
> From: Voon Weifeng <weifeng.voon@intel.com>
> 
> The Intel mGbE supports 2.5Gbps link speed by increasing the clock rate by
> 2.5 times of the original rate. In this mode, the serdes/PHY operates at a
> serial baud rate of 3.125 Gbps and the PCS data path and GMII interface of
> the MAC operate at 312.5 MHz instead of 125 MHz.
> 
> For Intel mGbE, the overclocking of 2.5 times clock rate to support 2.5G is
> only able to be configured in the BIOS during boot time. Kernel driver has
> no access to modify the clock rate for 1Gbps/2.5G mode. The way to
> determined the current 1G/2.5G mode is by reading a dedicated adhoc
> register through mdio bus. In short, after the system boot up, it is either
> in 1G mode or 2.5G mode which not able to be changed on the fly.
> 
> Compared to 1G mode, the 2.5G mode selects the 2500BASEX as PHY interface and
> disables the xpcs_an_inband. This is to cater for some PHYs that only
> supports 2500BASEX PHY interface with no autonegotiation.
> 
> v2: remove MAC supported link speed masking
> v3: Restructure  to introduce intel_speed_mode_2500() to read serdes registers
>     for max speed supported and select the appropritate configuration.
>     Use max_speed to determine the supported link speed mask.
> 
> Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
> Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
> ---

Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>

      reply	other threads:[~2021-06-04 12:02 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-04 10:57 [RESEND PATCH net-next v5 0/3] Enable 2.5Gbps speed for stmmac Michael Sit Wei Hong
2021-06-04 10:57 ` [RESEND PATCH net-next v5 1/3] net: stmmac: split xPCS setup from mdio register Michael Sit Wei Hong
2021-06-04 11:51   ` Vladimir Oltean
2021-06-04 13:08     ` Vladimir Oltean
2021-06-04 10:57 ` [RESEND PATCH net-next v5 2/3] net: pcs: add 2500BASEX support for Intel mGbE controller Michael Sit Wei Hong
2021-06-04 12:00   ` Vladimir Oltean
2021-06-04 10:57 ` [RESEND PATCH net-next v5 3/3] net: stmmac: enable Intel mGbE 2.5Gbps link speed Michael Sit Wei Hong
2021-06-04 12:02   ` Vladimir Oltean [this message]

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