From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3989C4743F for ; Sun, 6 Jun 2021 20:23:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DFD6A613D4 for ; Sun, 6 Jun 2021 20:23:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230212AbhFFUZT (ORCPT ); Sun, 6 Jun 2021 16:25:19 -0400 Received: from smtp-35-i2.italiaonline.it ([213.209.12.35]:44971 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S230155AbhFFUZQ (ORCPT ); Sun, 6 Jun 2021 16:25:16 -0400 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([79.17.119.101]) by smtp-35.iol.local with ESMTPA id pzIbl3WgQsptipzIslrvUr; Sun, 06 Jun 2021 22:23:26 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1623011006; bh=hqdToKdXep6rD2t3+5/OUkGokVRGwUGIXwri9qp4guU=; h=From; b=rPrVsZPbCKhA8xnbWHqplA2YAj+B5Jeu6JF5sFNSKbuwBPTXTyyNAbx8lNIx0Iroy BUKtO4U6rfj6D9LubPySefmaETlbCOl0XZK2ub1tA6z78rYc/cp7xc8GVTdQ5VSmnD J1WKkxYQcgw4sC8VvtQ/fKMXhMmFfE9fcKLBPMCHx9BnOQDfWLEWc5DF4eYl8+k0ao S5n9imbGOyp9NxXuZ9sSPJJVHQR4EIU8vA4FpaJfTo8/LRauCmlt8tIhQJJM7L4ATs WGnxL3KlqsgrlheERcCUEKic6HEq0b18aMhB4fMfPJjHPP8ufy4sXjnWIxZZW/8Z9G ZSKaVkamfk1eA== X-CNFS-Analysis: v=2.4 cv=Bo1Yfab5 c=1 sm=1 tr=0 ts=60bd2ebe cx=a_exe a=do1bHx4A/kh2kuTIUQHSxQ==:117 a=do1bHx4A/kh2kuTIUQHSxQ==:17 a=VwQbUJbxAAAA:8 a=IXkOJODCewQtKEFu2i4A:9 a=5yUOnwQy5QICz8m5uxDm:22 a=AjGcO6oz07-iQ99wixmX:22 a=pHzHmUro8NiASowvMSCR:22 a=xoEH_sTeL_Rfw54TyV31:22 From: Dario Binacchi To: linux-clk@vger.kernel.org Cc: Rob Herring , Tony Lindgren , Michael Turquette , Dario Binacchi , linux-omap@vger.kernel.org, Lee Jones , Stephen Boyd , =?UTF-8?q?Beno=C3=AEt=20Cousson?= , Tero Kristo , linux-kernel@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org Subject: [RESEND PATCH v7 2/5] dt-bindings: ti: dpll: add spread spectrum support Date: Sun, 6 Jun 2021 22:22:50 +0200 Message-Id: <20210606202253.31649-3-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210606202253.31649-1-dariobin@libero.it> References: <20210606202253.31649-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfIxXsTUKj5ZkJsb8xHFyxnlq3udr8fqR5FHUxDoGXjJh/Lry0M7V+ld07KY3wYxW0qiC6dWDvSb9qXGmGBplc3JjoeVokJwGiP2/Ku020CIBgN7KS1oi mr7w3qNsFS7NgDWXKyHvctmXx/93hrhGorAXaFxUWAFPS+pRJ//MRQ4nIvzpCT6TPJiNwDG0sAjOtd4BtTSK4ipEQ8e9R7KEiZXwQUE3FpUTyWTfxHolJykm A0bObYZmm/+2oTLYpf7GjJkW7Mne8Xzeig0CF9GFYGALXg6bin7AlcFvn1gg/kJyK7PkusJFgF/PqYXB+EqxIL2q/dptm8yQbqOr0MRXtwmHz/uJTtuTM/ni mmyYvrRCv6FFkjV6/Z6xwXdcqzEKCVJk+/msflviUNHR0GTHT/NgZItZXQHHitfvBT9W1wr4CTmDsvzXWEXLyqVy8cdZW6SSjH5VAqHUnrpCVlHcKx+B/bec QFSMHuF2mw4C+0XSnIeoMdBJsJj/lyc644bN0U/rN5VugrbAM0ZqK5QHZRIJ8Qy+1rf2I3eH3jD+d8S6V2bCEGOOp7snnf0g2TbrziAOgV/PBzGz1mV8q7De 5QY5XAfkB7dhZVZNguyKHWnYM6vmemnlr/8wI54XXrINzQ== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org DT bindings for enabling and adjusting spread spectrum clocking have been added. Signed-off-by: Dario Binacchi Reviewed-by: Rob Herring --- (no changes since v4) Changes in v4: - Add Rob Herring review tag. Changes in v3: - Add '-hz' suffix to "ti,ssc-modfreq" binding. .../devicetree/bindings/clock/ti/dpll.txt | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt index df57009ff8e7..37a7cb6ad07d 100644 --- a/Documentation/devicetree/bindings/clock/ti/dpll.txt +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt @@ -42,6 +42,11 @@ Required properties: "idlest" - contains the idle status register base address "mult-div1" - contains the multiplier / divider register base address "autoidle" - contains the autoidle register base address (optional) + "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains + the frequency spreading register base address (optional) + "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains + the modulation frequency register base address + (optional) ti,am3-* dpll types do not have autoidle register ti,omap2-* dpll type does not support idlest / autoidle registers @@ -51,6 +56,14 @@ Optional properties: - ti,low-power-stop : DPLL supports low power stop mode, gating output - ti,low-power-bypass : DPLL output matches rate of parent bypass clock - ti,lock : DPLL locks in programmed rate + - ti,min-div : the minimum divisor to start from to round the DPLL + target rate + - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency + spreading in permille (10th of a percent) + - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread + spectrum modulation frequency + - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean + to enable the downspread feature Examples: dpll_core_ck: dpll_core_ck@44e00490 { @@ -83,3 +96,10 @@ Examples: clocks = <&sys_ck>, <&sys_ck>; reg = <0x0500>, <0x0540>; }; + + dpll_disp_ck: dpll_disp_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-no-gate-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; + }; -- 2.17.1