From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCBE2C48BCD for ; Mon, 7 Jun 2021 18:23:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B979261105 for ; Mon, 7 Jun 2021 18:23:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231235AbhFGSYw (ORCPT ); Mon, 7 Jun 2021 14:24:52 -0400 Received: from gate.crashing.org ([63.228.1.57]:33191 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230450AbhFGSYu (ORCPT ); Mon, 7 Jun 2021 14:24:50 -0400 Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id 157IIP9d017401; Mon, 7 Jun 2021 13:18:25 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id 157IINkr017398; Mon, 7 Jun 2021 13:18:23 -0500 X-Authentication-Warning: gate.crashing.org: segher set sender to segher@kernel.crashing.org using -f Date: Mon, 7 Jun 2021 13:18:23 -0500 From: Segher Boessenkool To: Alexander Monakov Cc: Linus Torvalds , Jakub Jelinek , Alan Stern , "Paul E. McKenney" , Peter Zijlstra , Will Deacon , Andrea Parri , Boqun Feng , Nick Piggin , David Howells , Jade Alglave , Luc Maranget , Akira Yokosawa , Linux Kernel Mailing List , linux-toolchains@vger.kernel.org, linux-arch Subject: Re: [RFC] LKMM: Add volatile_if() Message-ID: <20210607181823.GH18427@gate.crashing.org> References: <20210606001418.GH4397@paulmck-ThinkPad-P17-Gen-1> <20210606012903.GA1723421@rowland.harvard.edu> <20210606185922.GF7746@tucnak> <20210607175200.GG18427@gate.crashing.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.3i Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jun 07, 2021 at 09:07:58PM +0300, Alexander Monakov wrote: > On Mon, 7 Jun 2021, Segher Boessenkool wrote: > > > > So the barrier which is a compiler barrier but not a machine barrier is > > > __atomic_signal_fence(model), but internally GCC will not treat it smarter > > > than an asm-with-memory-clobber today. > > > > It will do nothing for relaxed ordering, and do blockage for everything > > else. Can it do anything weaker than that? > > It's a "blockage instruction" after transitioning to RTL, but before that, > on GIMPLE, the compiler sees it properly as a corresponding built-in, and > may optimize according to given memory model. And on RTL, well, if anyone > cares they'll need to invent RTL representation for it, I guess. My question was if anything weaker is *valid* :-) (And if so, why!) Segher