From: Jonathan Marek <jonathan@marek.ca>
To: freedreno@lists.freedesktop.org
Cc: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Jordan Crouse <jordan@cosmicpenguin.net>,
Akhil P Oommen <akhilpo@codeaurora.org>,
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
Eric Anholt <eric@anholt.net>,
Sharat Masetty <smasetty@codeaurora.org>,
Douglas Anderson <dianders@chromium.org>,
linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM
ADRENO GPU),
dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM
ADRENO GPU), linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v3 4/5] drm/msm/a6xx: add missing PC_DBG_ECO_CNTL bit for a640/a650
Date: Tue, 8 Jun 2021 13:27:47 -0400 [thread overview]
Message-ID: <20210608172808.11803-5-jonathan@marek.ca> (raw)
In-Reply-To: <20210608172808.11803-1-jonathan@marek.ca>
See downstream's "disable_tseskip" flag.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 853be7651623..bbbf90d86828 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -844,13 +844,15 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
/* Setting the mem pool size */
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
- /* Setting the primFifo thresholds default values */
+ /* Setting the primFifo thresholds default values,
+ * and vccCacheSkipDis=1 bit (0x200) for A640 and newer
+ */
if (adreno_is_a650(adreno_gpu))
- gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000);
+ gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
else if (adreno_is_a640(adreno_gpu))
- gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000);
+ gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
else
- gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11));
+ gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000);
/* Set the AHB default slave response to "ERROR" */
gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
--
2.26.1
next prev parent reply other threads:[~2021-06-08 17:31 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-08 17:27 [PATCH v3 0/5] drm/msm/a6xx: add support for Adreno 660 GPU Jonathan Marek
2021-06-08 17:27 ` [PATCH v3 1/5] drm/msm: remove unused icc_path/ocmem_icc_path Jonathan Marek
2021-06-08 17:27 ` [PATCH v3 2/5] drm/msm/a6xx: use AOP-initialized PDC for a650 Jonathan Marek
2021-06-08 17:27 ` [PATCH v3 3/5] drm/msm/a6xx: add GMU_CX_GMU_CX_FALNEXT_INTF write " Jonathan Marek
2021-06-08 18:03 ` Jonathan Marek
2021-06-08 17:27 ` Jonathan Marek [this message]
2021-06-08 17:27 ` [PATCH v3 5/5] drm/msm/a6xx: add support for Adreno 660 GPU Jonathan Marek
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