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Date:   Mon, 14 Jun 2021 17:36:03 +0200
From:   Christoph Hellwig <hch@lst.de>
To:     Robin Murphy <robin.murphy@arm.com>
Cc:     Catalin Marinas <catalin.marinas@arm.com>,
        Dong Aisheng <dongas86@gmail.com>,
        Will Deacon <will@kernel.org>,
        Dong Aisheng <aisheng.dong@nxp.com>,
        iommu@lists.linux-foundation.org,
        open list <linux-kernel@vger.kernel.org>, linux-mm@kvack.org,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@lists.infradead.org>,
        Christoph Hellwig <hch@lst.de>,
        Marek Szyprowski <m.szyprowski@samsung.com>
Subject: Re: [PATCH 1/1] dma: coherent: check no-map property for arm64
Message-ID: <20210614153603.GA1998@lst.de>
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On Mon, Jun 14, 2021 at 04:34:05PM +0100, Robin Murphy wrote:
>> Looking at the rmem_dma_device_init() -> dma_init_coherent_memory(), it
>> ends up calling memremap(MEMREMAP_WC) which would warn if it intersects
>> with system RAM regardless of the architecture. If the memory region is
>> nomap, it doesn't end up as IORESOURCE_SYSTEM_RAM, so memremap() won't
>> warn. But why is this specific only to arm (or arm64)?
>
> Didn't some ARMv7 implementations permit unexpected cache hits for the 
> non-cacheable address if the same PA has been speculatively fetched via the 
> cacheable alias?

If we care about that we need to change these platforms to change the
cache attributes of the kernel direct mapping instead of using vmap.
We already have code to do that for openrisc, someone just needs to
write the glue code for other platforms.