From: Chun-Jie Chen <chun-jie.chen@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>
Cc: <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Weiyi Lu <weiyi.lu@mediatek.com>,
Chun-Jie Chen <chun-jie.chen@mediatek.com>
Subject: [PATCH v4 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192
Date: Wed, 16 Jun 2021 09:15:51 +0800 [thread overview]
Message-ID: <20210616011551.29654-3-chun-jie.chen@mediatek.com> (raw)
In-Reply-To: <20210616011551.29654-1-chun-jie.chen@mediatek.com>
infra_uart0 clock is the real one what uart0 uses as bus clock.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 83f71d13ef9d..b51409f516b1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -327,7 +327,7 @@
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
clock-names = "baud", "bus";
status = "disabled";
};
--
2.18.0
prev parent reply other threads:[~2021-06-16 1:18 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20210616011551.29654-1-chun-jie.chen@mediatek.com>
2021-06-16 1:15 ` [PATCH v4 1/2] arm64: dts: mediatek: Add mt8192 clock controllers Chun-Jie Chen
2021-06-17 23:14 ` kernel test robot
2021-06-16 1:15 ` Chun-Jie Chen [this message]
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