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* [PATCH 00/22] Mediatek MT8195 clock support
@ 2021-06-16 22:47 Chun-Jie Chen
  2021-06-16 22:47 ` [PATCH 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock Chun-Jie Chen
                   ` (21 more replies)
  0 siblings, 22 replies; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group

this patch series is based on 5.13-rc3 and depends on [1]
- for makefile dependence (patches 7 ~ 19 in [1])
- for common driver dependence (patches 3 ~ 6 in [1])

[1] https://patchwork.kernel.org/project/linux-mediatek/cover/20210616003643.28648-1-chun-jie.chen@mediatek.com/

Chun-Jie Chen (22):
  dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock
  clk: mediatek: Add dt-bindings of MT8195 clocks
  clk: mediatek: Fix corner case of tuner_en_reg
  clk: mediatek: Add MT8195 basic clocks support
  clk: mediatek: Add MT8195 audio clock support
  clk: mediatek: Add MT8195 audio src clock support
  clk: mediatek: Add MT8195 camsys clock support
  clk: mediatek: Add MT8195 ccusys clock support
  clk: mediatek: Add MT8195 imgsys clock support
  clk: mediatek: Add MT8195 ipesys clock support
  clk: mediatek: Add MT8195 mfgcfg clock support
  clk: mediatek: Add MT8195 scp adsp clock support
  clk: mediatek: Add MT8195 nnasys clock support
  clk: mediatek: Add MT8195 vdecsys clock support
  clk: mediatek: Add MT8195 vdosys0 clock support
  clk: mediatek: Add MT8195 vdosys1 clock support
  clk: mediatek: Add MT8195 vencsys clock support
  clk: mediatek: Add MT8195 vppsys0 clock support
  clk: mediatek: Add MT8195 vppsys1 clock support
  clk: mediatek: Add MT8195 wpesys clock support
  clk: mediatek: Add MT8195 imp i2c wrapper clock support
  clk: mediatek: Add MT8195 apusys clock support

 .../arm/mediatek/mediatek,mt8195-clock.yaml   |  287 +++
 .../mediatek/mediatek,mt8195-sys-clock.yaml   |   66 +
 drivers/clk/mediatek/Kconfig                  |  116 +
 drivers/clk/mediatek/Makefile                 |   19 +
 drivers/clk/mediatek/clk-mt8195-apusys_pll.c  |   84 +
 drivers/clk/mediatek/clk-mt8195-aud.c         |  198 ++
 drivers/clk/mediatek/clk-mt8195-aud_src.c     |   60 +
 drivers/clk/mediatek/clk-mt8195-cam.c         |  144 ++
 drivers/clk/mediatek/clk-mt8195-ccu.c         |   52 +
 drivers/clk/mediatek/clk-mt8195-img.c         |   98 +
 .../clk/mediatek/clk-mt8195-imp_iic_wrap.c    |   68 +
 drivers/clk/mediatek/clk-mt8195-ipe.c         |   53 +
 drivers/clk/mediatek/clk-mt8195-mfg.c         |   49 +
 drivers/clk/mediatek/clk-mt8195-nna.c         |  128 ++
 drivers/clk/mediatek/clk-mt8195-scp_adsp.c    |   49 +
 drivers/clk/mediatek/clk-mt8195-vdec.c        |  106 +
 drivers/clk/mediatek/clk-mt8195-vdo0.c        |  114 +
 drivers/clk/mediatek/clk-mt8195-vdo1.c        |  131 ++
 drivers/clk/mediatek/clk-mt8195-venc.c        |   71 +
 drivers/clk/mediatek/clk-mt8195-vpp0.c        |  112 +
 drivers/clk/mediatek/clk-mt8195-vpp1.c        |  110 +
 drivers/clk/mediatek/clk-mt8195-wpe.c         |  145 ++
 drivers/clk/mediatek/clk-mt8195.c             | 1958 +++++++++++++++++
 drivers/clk/mediatek/clk-pll.c                |    2 +-
 include/dt-bindings/clock/mt8195-clk.h        |  989 +++++++++
 25 files changed, 5208 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
 create mode 100644 drivers/clk/mediatek/clk-mt8195-apusys_pll.c
 create mode 100644 drivers/clk/mediatek/clk-mt8195-aud.c
 create mode 100644 drivers/clk/mediatek/clk-mt8195-aud_src.c
 create mode 100644 drivers/clk/mediatek/clk-mt8195-cam.c
 create mode 100644 drivers/clk/mediatek/clk-mt8195-ccu.c
 create mode 100644 drivers/clk/mediatek/clk-mt8195-img.c
 create mode 100644 drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c
 create mode 100644 drivers/clk/mediatek/clk-mt8195-ipe.c
 create mode 100644 drivers/clk/mediatek/clk-mt8195-mfg.c
 create mode 100644 drivers/clk/mediatek/clk-mt8195-nna.c
 create mode 100644 drivers/clk/mediatek/clk-mt8195-scp_adsp.c
 create mode 100644 drivers/clk/mediatek/clk-mt8195-vdec.c
 create mode 100644 drivers/clk/mediatek/clk-mt8195-vdo0.c
 create mode 100644 drivers/clk/mediatek/clk-mt8195-vdo1.c
 create mode 100644 drivers/clk/mediatek/clk-mt8195-venc.c
 create mode 100644 drivers/clk/mediatek/clk-mt8195-vpp0.c
 create mode 100644 drivers/clk/mediatek/clk-mt8195-vpp1.c
 create mode 100644 drivers/clk/mediatek/clk-mt8195-wpe.c
 create mode 100644 drivers/clk/mediatek/clk-mt8195.c
 create mode 100644 include/dt-bindings/clock/mt8195-clk.h

-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-06-24 21:21   ` Rob Herring
  2021-07-12  9:32   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 02/22] clk: mediatek: Add dt-bindings of MT8195 clocks Chun-Jie Chen
                   ` (20 subsequent siblings)
  21 siblings, 2 replies; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

This patch adds the new binding documentation for system clock
and functional clock on Mediatek MT8195.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 .../arm/mediatek/mediatek,mt8195-clock.yaml   | 287 ++++++++++++++++++
 .../mediatek/mediatek,mt8195-sys-clock.yaml   |  66 ++++
 2 files changed, 353 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
new file mode 100644
index 000000000000..21554b3515cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
@@ -0,0 +1,287 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MediaTek Functional Clock Controller for MT8195
+
+maintainers:
+  - Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+description:
+  The Mediatek functional clock controller provides various clocks on MT8195.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - mediatek,mt8195-nnasys
+              - mediatek,mt8195-scp_adsp
+              - mediatek,mt8195-audsys
+              - mediatek,mt8195-audsys_src
+              - mediatek,mt8195-imp_iic_wrap_s
+              - mediatek,mt8195-imp_iic_wrap_w
+              - mediatek,mt8195-mfgcfg
+              - mediatek,mt8195-vppsys0
+              - mediatek,mt8195-wpesys
+              - mediatek,mt8195-wpesys_vpp0
+              - mediatek,mt8195-wpesys_vpp1
+              - mediatek,mt8195-vppsys1
+              - mediatek,mt8195-imgsys
+              - mediatek,mt8195-imgsys1_dip_top
+              - mediatek,mt8195-imgsys1_dip_nr
+              - mediatek,mt8195-imgsys1_wpe
+              - mediatek,mt8195-ipesys
+              - mediatek,mt8195-camsys
+              - mediatek,mt8195-camsys_rawa
+              - mediatek,mt8195-camsys_yuva
+              - mediatek,mt8195-camsys_rawb
+              - mediatek,mt8195-camsys_yuvb
+              - mediatek,mt8195-camsys_mraw
+              - mediatek,mt8195-ccusys
+              - mediatek,mt8195-vdecsys_soc
+              - mediatek,mt8195-vdecsys
+              - mediatek,mt8195-vdecsys_core1
+              - mediatek,mt8195-apusys_pll
+              - mediatek,mt8195-vencsys
+              - mediatek,mt8195-vencsys_core1
+              - mediatek,mt8195-vdosys0
+              - mediatek,mt8195-vdosys1
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    nnasys: clock-controller@10211000 {
+        compatible = "mediatek,mt8195-nnasys";
+        reg = <0x10211000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    scp_adsp: clock-controller@10720000 {
+        compatible = "mediatek,mt8195-scp_adsp";
+        reg = <0x10720000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    audsys: clock-controller@10890000 {
+        compatible = "mediatek,mt8195-audsys";
+        reg = <0x10890000 0x10000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    audsys_src: clock-controller@108a0000 {
+        compatible = "mediatek,mt8195-audsys_src";
+        reg = <0x108a0000 0x2000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    imp_iic_wrap_s: clock-controller@11d03000 {
+        compatible = "mediatek,mt8195-imp_iic_wrap_s";
+        reg = <0x11d03000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    imp_iic_wrap_w: clock-controller@11e05000 {
+        compatible = "mediatek,mt8195-imp_iic_wrap_w";
+        reg = <0x11e05000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    mfgcfg: clock-controller@13fbf000 {
+        compatible = "mediatek,mt8195-mfgcfg";
+        reg = <0x13fbf000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    vppsys0: clock-controller@14000000 {
+        compatible = "mediatek,mt8195-vppsys0";
+        reg = <0x14000000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    wpesys: clock-controller@14e00000 {
+        compatible = "mediatek,mt8195-wpesys";
+        reg = <0x14e00000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    wpesys_vpp0: clock-controller@14e02000 {
+        compatible = "mediatek,mt8195-wpesys_vpp0";
+        reg = <0x14e02000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    wpesys_vpp1: clock-controller@14e03000 {
+        compatible = "mediatek,mt8195-wpesys_vpp1";
+        reg = <0x14e03000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    vppsys1: clock-controller@14f00000 {
+        compatible = "mediatek,mt8195-vppsys1";
+        reg = <0x14f00000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    imgsys: clock-controller@15000000 {
+        compatible = "mediatek,mt8195-imgsys";
+        reg = <0x15000000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    imgsys1_dip_top: clock-controller@15110000 {
+        compatible = "mediatek,mt8195-imgsys1_dip_top";
+        reg = <0x15110000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    imgsys1_dip_nr: clock-controller@15130000 {
+        compatible = "mediatek,mt8195-imgsys1_dip_nr";
+        reg = <0x15130000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    imgsys1_wpe: clock-controller@15220000 {
+        compatible = "mediatek,mt8195-imgsys1_wpe";
+        reg = <0x15220000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    ipesys: clock-controller@15330000 {
+        compatible = "mediatek,mt8195-ipesys";
+        reg = <0x15330000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    camsys: clock-controller@16000000 {
+        compatible = "mediatek,mt8195-camsys";
+        reg = <0x16000000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    camsys_rawa: clock-controller@1604f000 {
+        compatible = "mediatek,mt8195-camsys_rawa";
+        reg = <0x1604f000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    camsys_yuva: clock-controller@1606f000 {
+        compatible = "mediatek,mt8195-camsys_yuva";
+        reg = <0x1606f000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    camsys_rawb: clock-controller@1608f000 {
+        compatible = "mediatek,mt8195-camsys_rawb";
+        reg = <0x1608f000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    camsys_yuvb: clock-controller@160af000 {
+        compatible = "mediatek,mt8195-camsys_yuvb";
+        reg = <0x160af000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    camsys_mraw: clock-controller@16140000 {
+        compatible = "mediatek,mt8195-camsys_mraw";
+        reg = <0x16140000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    ccusys: clock-controller@17200000 {
+        compatible = "mediatek,mt8195-ccusys";
+        reg = <0x17200000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    vdecsys_soc: clock-controller@1800f000 {
+        compatible = "mediatek,mt8195-vdecsys_soc";
+        reg = <0x1800f000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    vdecsys: clock-controller@1802f000 {
+        compatible = "mediatek,mt8195-vdecsys";
+        reg = <0x1802f000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    vdecsys_core1: clock-controller@1803f000 {
+        compatible = "mediatek,mt8195-vdecsys_core1";
+        reg = <0x1803f000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    apusys_pll: clock-controller@190f3000 {
+        compatible = "mediatek,mt8195-apusys_pll";
+        reg = <0x190f3000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    vencsys: clock-controller@1a000000 {
+        compatible = "mediatek,mt8195-vencsys";
+        reg = <0x1a000000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    vencsys_core1: clock-controller@1b000000 {
+        compatible = "mediatek,mt8195-vencsys_core1";
+        reg = <0x1b000000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    vdosys0: clock-controller@1c01a000 {
+        compatible = "mediatek,mt8195-vdosys0";
+        reg = <0x1c01a000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    vdosys1: clock-controller@1c100000 {
+        compatible = "mediatek,mt8195-vdosys1";
+        reg = <0x1c100000 0x1000>;
+        #clock-cells = <1>;
+    };
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
new file mode 100644
index 000000000000..ea379452ba91
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MediaTek System Clock Controller for MT8195
+
+maintainers:
+  - Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+description:
+  The Mediatek system clock controller provides various clocks and system configuration
+  like reset and bus protection on MT8195.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - mediatek,mt8195-topckgen
+              - mediatek,mt8195-infracfg_ao
+              - mediatek,mt8195-apmixedsys
+              - mediatek,mt8195-pericfg_ao
+          - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    topckgen: syscon@10000000 {
+        compatible = "mediatek,mt8195-topckgen", "syscon";
+        reg = <0x10000000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    infracfg_ao: syscon@10001000 {
+        compatible = "mediatek,mt8195-infracfg_ao", "syscon";
+        reg = <0x10001000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    apmixedsys: syscon@1000c000 {
+        compatible = "mediatek,mt8195-apmixedsys", "syscon";
+        reg = <0x1000c000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+  - |
+    pericfg_ao: syscon@11003000 {
+        compatible = "mediatek,mt8195-pericfg_ao", "syscon";
+        reg = <0x11003000 0x1000>;
+        #clock-cells = <1>;
+    };
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 02/22] clk: mediatek: Add dt-bindings of MT8195 clocks
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
  2021-06-16 22:47 ` [PATCH 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-06-24 21:22   ` Rob Herring
  2021-07-12  9:37   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg Chun-Jie Chen
                   ` (19 subsequent siblings)
  21 siblings, 2 replies; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 clock dt-bindings, include topckgen, apmixedsys,
infracfg_ao, pericfg_ao and subsystem clocks.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 include/dt-bindings/clock/mt8195-clk.h | 989 +++++++++++++++++++++++++
 1 file changed, 989 insertions(+)
 create mode 100644 include/dt-bindings/clock/mt8195-clk.h

diff --git a/include/dt-bindings/clock/mt8195-clk.h b/include/dt-bindings/clock/mt8195-clk.h
new file mode 100644
index 000000000000..c383a9904e76
--- /dev/null
+++ b/include/dt-bindings/clock/mt8195-clk.h
@@ -0,0 +1,989 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8195_H
+#define _DT_BINDINGS_CLK_MT8195_H
+
+/* TOPCKGEN */
+
+#define CLK_TOP_AXI_SEL			0
+#define CLK_TOP_SPM_SEL			1
+#define CLK_TOP_BUS_AXIMEM_SEL		2
+#define CLK_TOP_VPP_SEL			3
+#define CLK_TOP_ETHDR_SEL		4
+#define CLK_TOP_IPE_SEL			5
+#define CLK_TOP_CAM_SEL			6
+#define CLK_TOP_CCU_SEL			7
+#define CLK_TOP_IMG_SEL			8
+#define CLK_TOP_CAMTM_SEL		9
+#define CLK_TOP_DSP_SEL			10
+#define CLK_TOP_DSP1_SEL		11
+#define CLK_TOP_DSP2_SEL		12
+#define CLK_TOP_DSP3_SEL		13
+#define CLK_TOP_DSP4_SEL		14
+#define CLK_TOP_DSP5_SEL		15
+#define CLK_TOP_DSP6_SEL		16
+#define CLK_TOP_DSP7_SEL		17
+#define CLK_TOP_IPU_IF_SEL		18
+#define CLK_TOP_MFG_SEL			19
+#define CLK_TOP_CAMTG_SEL		20
+#define CLK_TOP_CAMTG2_SEL		21
+#define CLK_TOP_CAMTG3_SEL		22
+#define CLK_TOP_CAMTG4_SEL		23
+#define CLK_TOP_CAMTG5_SEL		24
+#define CLK_TOP_UART_SEL		25
+#define CLK_TOP_SPI_SEL			26
+#define CLK_TOP_SPIS_SEL		27
+#define CLK_TOP_MSDC50_0_H_SEL		28
+#define CLK_TOP_MSDC50_0_SEL		29
+#define CLK_TOP_MSDC30_1_SEL		30
+#define CLK_TOP_MSDC30_2_SEL		31
+#define CLK_TOP_INTDIR_SEL		32
+#define CLK_TOP_AUD_INTBUS_SEL		33
+#define CLK_TOP_AUDIO_H_SEL		34
+#define CLK_TOP_PWRAP_ULPOSC_SEL	35
+#define CLK_TOP_ATB_SEL			36
+#define CLK_TOP_PWRMCU_SEL		37
+#define CLK_TOP_DP_SEL			38
+#define CLK_TOP_EDP_SEL			39
+#define CLK_TOP_DPI_SEL			40
+#define CLK_TOP_DISP_PWM0_SEL		41
+#define CLK_TOP_DISP_PWM1_SEL		42
+#define CLK_TOP_USB_SEL			43
+#define CLK_TOP_SSUSB_XHCI_SEL		44
+#define CLK_TOP_USB_1P_SEL		45
+#define CLK_TOP_SSUSB_XHCI_1P_SEL	46
+#define CLK_TOP_USB_2P_SEL		47
+#define CLK_TOP_SSUSB_XHCI_2P_SEL	48
+#define CLK_TOP_USB_3P_SEL		49
+#define CLK_TOP_SSUSB_XHCI_3P_SEL	50
+#define CLK_TOP_I2C_SEL			51
+#define CLK_TOP_SENINF_SEL		52
+#define CLK_TOP_SENINF1_SEL		53
+#define CLK_TOP_SENINF2_SEL		54
+#define CLK_TOP_SENINF3_SEL		55
+#define CLK_TOP_GCPU_SEL		56
+#define CLK_TOP_DXCC_SEL		57
+#define CLK_TOP_DPMAIF_SEL		58
+#define CLK_TOP_AES_UFSFDE_SEL		59
+#define CLK_TOP_UFS_SEL			60
+#define CLK_TOP_UFS_TICK1US_SEL		61
+#define CLK_TOP_UFS_MP_SAP_SEL		62
+#define CLK_TOP_VENC_SEL		63
+#define CLK_TOP_VDEC_SEL		64
+#define CLK_TOP_PWM_SEL			65
+#define CLK_TOP_SPMI_P_MST_SEL		66
+#define CLK_TOP_SPMI_M_MST_SEL		67
+#define CLK_TOP_TL_SEL			68
+#define CLK_TOP_TL_P1_SEL		69
+#define CLK_TOP_AES_MSDCFDE_SEL		70
+#define CLK_TOP_DSI_OCC_SEL		71
+#define CLK_TOP_WPE_VPP_SEL		72
+#define CLK_TOP_HDCP_SEL		73
+#define CLK_TOP_HDCP_24M_SEL		74
+#define CLK_TOP_HD20_DACR_REF_SEL	75
+#define CLK_TOP_HD20_HDCP_C_SEL		76
+#define CLK_TOP_HDMI_XTAL_SEL		77
+#define CLK_TOP_HDMI_APB_SEL		78
+#define CLK_TOP_SNPS_ETH_250M_SEL	79
+#define CLK_TOP_SNPS_ETH_62P4M_PTP_SEL	80
+#define CLK_TOP_SNPS_ETH_50M_RMII_SEL	81
+#define CLK_TOP_DGI_OUT_SEL		82
+#define CLK_TOP_NNA0_SEL		83
+#define CLK_TOP_NNA1_SEL		84
+#define CLK_TOP_ADSP_SEL		85
+#define CLK_TOP_ASM_H_SEL		86
+#define CLK_TOP_ASM_M_SEL		87
+#define CLK_TOP_ASM_L_SEL		88
+#define CLK_TOP_APLL1_SEL		89
+#define CLK_TOP_APLL2_SEL		90
+#define CLK_TOP_APLL3_SEL		91
+#define CLK_TOP_APLL4_SEL		92
+#define CLK_TOP_APLL5_SEL		93
+#define CLK_TOP_I2SO1_M_SEL		94
+#define CLK_TOP_I2SO2_M_SEL		95
+#define CLK_TOP_I2SI1_M_SEL		96
+#define CLK_TOP_I2SI2_M_SEL		97
+#define CLK_TOP_DPTX_M_SEL		98
+#define CLK_TOP_AUD_IEC_SEL		99
+#define CLK_TOP_A1SYS_HP_SEL		100
+#define CLK_TOP_A2SYS_SEL		101
+#define CLK_TOP_A3SYS_SEL		102
+#define CLK_TOP_A4SYS_SEL		103
+#define CLK_TOP_SPINFI_B_SEL		104
+#define CLK_TOP_NFI1X_SEL		105
+#define CLK_TOP_ECC_SEL			106
+#define CLK_TOP_AUDIO_LOCAL_BUS_SEL	107
+#define CLK_TOP_SPINOR_SEL		108
+#define CLK_TOP_DVIO_DGI_REF_SEL	109
+#define CLK_TOP_SRCK_SEL		110
+#define CLK_TOP_RSVD1_SEL		111
+#define CLK_TOP_MFG_FAST_SEL		112
+#define CLK_TOP_CLK26M_D2		113
+#define CLK_TOP_CLK26M_D52		114
+#define CLK_TOP_IN_DGI			115
+#define CLK_TOP_IN_DGI_D2		116
+#define CLK_TOP_IN_DGI_D4		117
+#define CLK_TOP_IN_DGI_D6		118
+#define CLK_TOP_IN_DGI_D8		119
+#define CLK_TOP_MFGPLL_OPP		120
+#define CLK_TOP_MAINPLL			121
+#define CLK_TOP_MAINPLL_D3		122
+#define CLK_TOP_MAINPLL_D4		123
+#define CLK_TOP_MAINPLL_D4_D2		124
+#define CLK_TOP_MAINPLL_D4_D4		125
+#define CLK_TOP_MAINPLL_D4_D8		126
+#define CLK_TOP_MAINPLL_D5		127
+#define CLK_TOP_MAINPLL_D5_D2		128
+#define CLK_TOP_MAINPLL_D5_D4		129
+#define CLK_TOP_MAINPLL_D5_D8		130
+#define CLK_TOP_MAINPLL_D6		131
+#define CLK_TOP_MAINPLL_D6_D2		132
+#define CLK_TOP_MAINPLL_D6_D4		133
+#define CLK_TOP_MAINPLL_D6_D8		134
+#define CLK_TOP_MAINPLL_D7		135
+#define CLK_TOP_MAINPLL_D7_D2		136
+#define CLK_TOP_MAINPLL_D7_D4		137
+#define CLK_TOP_MAINPLL_D7_D8		138
+#define CLK_TOP_MAINPLL_D9		139
+#define CLK_TOP_UNIVPLL			140
+#define CLK_TOP_UNIVPLL_D2		141
+#define CLK_TOP_UNIVPLL_D3		142
+#define CLK_TOP_UNIVPLL_D4		143
+#define CLK_TOP_UNIVPLL_D4_D2		144
+#define CLK_TOP_UNIVPLL_D4_D4		145
+#define CLK_TOP_UNIVPLL_D4_D8		146
+#define CLK_TOP_UNIVPLL_D5		147
+#define CLK_TOP_UNIVPLL_D5_D2		148
+#define CLK_TOP_UNIVPLL_D5_D4		149
+#define CLK_TOP_UNIVPLL_D5_D8		150
+#define CLK_TOP_UNIVPLL_D6		151
+#define CLK_TOP_UNIVPLL_D6_D2		152
+#define CLK_TOP_UNIVPLL_D6_D4		153
+#define CLK_TOP_UNIVPLL_D6_D8		154
+#define CLK_TOP_UNIVPLL_D6_D16		155
+#define CLK_TOP_UNIVPLL_D7		156
+#define CLK_TOP_UNIVPLL_192M		157
+#define CLK_TOP_UNIVPLL_192M_D4		158
+#define CLK_TOP_UNIVPLL_192M_D8		159
+#define CLK_TOP_UNIVPLL_192M_D16	160
+#define CLK_TOP_UNIVPLL_192M_D32	161
+#define CLK_TOP_IMGPLL			162
+#define CLK_TOP_APLL1			163
+#define CLK_TOP_APLL1_D3		164
+#define CLK_TOP_APLL1_D4		165
+#define CLK_TOP_APLL2			166
+#define CLK_TOP_APLL2_D3		167
+#define CLK_TOP_APLL2_D4		168
+#define CLK_TOP_APLL3			169
+#define CLK_TOP_APLL3_D4		170
+#define CLK_TOP_APLL4			171
+#define CLK_TOP_APLL4_D4		172
+#define CLK_TOP_APLL5			173
+#define CLK_TOP_APLL5_D4		174
+#define CLK_TOP_HDMIRX_APLL		175
+#define CLK_TOP_HDMIRX_APLL_D3		176
+#define CLK_TOP_HDMIRX_APLL_D4		177
+#define CLK_TOP_HDMIRX_APLL_D6		178
+#define CLK_TOP_NNAPLL			179
+#define CLK_TOP_MMPLL			180
+#define CLK_TOP_MMPLL_D4		181
+#define CLK_TOP_MMPLL_D4_D2		182
+#define CLK_TOP_MMPLL_D4_D4		183
+#define CLK_TOP_MMPLL_D5		184
+#define CLK_TOP_MMPLL_D5_D2		185
+#define CLK_TOP_MMPLL_D5_D4		186
+#define CLK_TOP_MMPLL_D6		187
+#define CLK_TOP_MMPLL_D6_D2		188
+#define CLK_TOP_MMPLL_D7		189
+#define CLK_TOP_MMPLL_D9		190
+#define CLK_TOP_TVDPLL1			191
+#define CLK_TOP_TVDPLL1_D2		192
+#define CLK_TOP_TVDPLL1_D4		193
+#define CLK_TOP_TVDPLL1_D8		194
+#define CLK_TOP_TVDPLL1_D16		195
+#define CLK_TOP_TVDPLL2			196
+#define CLK_TOP_TVDPLL2_D2		197
+#define CLK_TOP_TVDPLL2_D4		198
+#define CLK_TOP_TVDPLL2_D8		199
+#define CLK_TOP_TVDPLL2_D16		200
+#define CLK_TOP_MSDCPLL			201
+#define CLK_TOP_MSDCPLL_D2		202
+#define CLK_TOP_MSDCPLL_D4		203
+#define CLK_TOP_MSDCPLL_D16		204
+#define CLK_TOP_ETHPLL			205
+#define CLK_TOP_ETHPLL_D2		206
+#define CLK_TOP_ETHPLL_D8		207
+#define CLK_TOP_ETHPLL_D10		208
+#define CLK_TOP_DGIPLL			209
+#define CLK_TOP_DGIPLL_D2		210
+#define CLK_TOP_VDECPLL			211
+#define CLK_TOP_ULPOSC			212
+#define CLK_TOP_ULPOSC_D2		213
+#define CLK_TOP_ULPOSC_D4		214
+#define CLK_TOP_ULPOSC_D7		215
+#define CLK_TOP_ULPOSC_D8		216
+#define CLK_TOP_ULPOSC_D10		217
+#define CLK_TOP_ULPOSC_D16		218
+#define CLK_TOP_ULPOSC2			219
+#define CLK_TOP_ADSPPLL			220
+#define CLK_TOP_ADSPPLL_D2		221
+#define CLK_TOP_ADSPPLL_D4		222
+#define CLK_TOP_ADSPPLL_D8		223
+#define CLK_TOP_MEM_466M		224
+#define CLK_TOP_MPHONE_SLAVE_B		225
+#define CLK_TOP_PEXTP_PIPE		226
+#define CLK_TOP_UFS_RX_SYMBOL		227
+#define CLK_TOP_UFS_TX_SYMBOL		228
+#define CLK_TOP_SSUSB_U3PHY_P1_P_P0	229
+#define CLK_TOP_UFS_RX_SYMBOL1		230
+#define CLK_TOP_FPC			231
+#define CLK_TOP_HDMIRX_P		232
+#define CLK_TOP_APLL12_DIV0		233
+#define CLK_TOP_APLL12_DIV1		234
+#define CLK_TOP_APLL12_DIV2		235
+#define CLK_TOP_APLL12_DIV3		236
+#define CLK_TOP_APLL12_DIV4		237
+#define CLK_TOP_APLL12_DIV9		238
+#define CLK_TOP_CFG_VPP0		239
+#define CLK_TOP_CFG_VPP1		240
+#define CLK_TOP_CFG_VDO0		241
+#define CLK_TOP_CFG_VDO1		242
+#define CLK_TOP_CFG_UNIPLL_SES		243
+#define CLK_TOP_CFG_26M_VPP0		244
+#define CLK_TOP_CFG_26M_VPP1		245
+#define CLK_TOP_CFG_26M_AUD		246
+#define CLK_TOP_CFG_AXI_EAST		247
+#define CLK_TOP_CFG_AXI_EAST_NORTH	248
+#define CLK_TOP_CFG_AXI_NORTH		249
+#define CLK_TOP_CFG_AXI_SOUTH		250
+#define CLK_TOP_CFG_EXT_TEST		251
+#define CLK_TOP_SSUSB_REF		252
+#define CLK_TOP_SSUSB_PHY_REF		253
+#define CLK_TOP_SSUSB_P1_REF		254
+#define CLK_TOP_SSUSB_PHY_P1_REF	255
+#define CLK_TOP_SSUSB_P2_REF		256
+#define CLK_TOP_SSUSB_PHY_P2_REF	257
+#define CLK_TOP_SSUSB_P3_REF		258
+#define CLK_TOP_SSUSB_PHY_P3_REF	259
+#define CLK_TOP_NR_CLK			260
+
+/* INFRACFG_AO */
+
+#define CLK_INFRA_AO_PMIC_TMR		0
+#define CLK_INFRA_AO_PMIC_AP		1
+#define CLK_INFRA_AO_PMIC_MD		2
+#define CLK_INFRA_AO_PMIC_CONN		3
+#define CLK_INFRA_AO_SEJ		4
+#define CLK_INFRA_AO_APXGPT		5
+#define CLK_INFRA_AO_GCE		6
+#define CLK_INFRA_AO_GCE2		7
+#define CLK_INFRA_AO_THERM		8
+#define CLK_INFRA_AO_PWM_H		9
+#define CLK_INFRA_AO_PWM1		10
+#define CLK_INFRA_AO_PWM2		11
+#define CLK_INFRA_AO_PWM3		12
+#define CLK_INFRA_AO_PWM4		13
+#define CLK_INFRA_AO_PWM		14
+#define CLK_INFRA_AO_UART0		15
+#define CLK_INFRA_AO_UART1		16
+#define CLK_INFRA_AO_UART2		17
+#define CLK_INFRA_AO_UART3		18
+#define CLK_INFRA_AO_UART4		19
+#define CLK_INFRA_AO_GCE_26M		20
+#define CLK_INFRA_AO_CQ_DMA_FPC		21
+#define CLK_INFRA_AO_UART5		22
+#define CLK_INFRA_AO_HDMI_26M		23
+#define CLK_INFRA_AO_SPI0		24
+#define CLK_INFRA_AO_MSDC0		25
+#define CLK_INFRA_AO_MSDC1		26
+#define CLK_INFRA_AO_CG1_MSDC2		27
+#define CLK_INFRA_AO_MSDC0_SRC		28
+#define CLK_INFRA_AO_TRNG		29
+#define CLK_INFRA_AO_AUXADC		30
+#define CLK_INFRA_AO_CPUM		31
+#define CLK_INFRA_AO_HDMI_32K		32
+#define CLK_INFRA_AO_CEC_66M_H		33
+#define CLK_INFRA_AO_IRRX		34
+#define CLK_INFRA_AO_PCIE_TL_26M	35
+#define CLK_INFRA_AO_MSDC1_SRC		36
+#define CLK_INFRA_AO_CEC_66M_B		37
+#define CLK_INFRA_AO_PCIE_TL_96M	38
+#define CLK_INFRA_AO_DEVICE_APC		39
+#define CLK_INFRA_AO_ECC_66M_H		40
+#define CLK_INFRA_AO_DEBUGSYS		41
+#define CLK_INFRA_AO_AUDIO		42
+#define CLK_INFRA_AO_PCIE_TL_32K	43
+#define CLK_INFRA_AO_DBG_TRACE		44
+#define CLK_INFRA_AO_DRAMC_F26M		45
+#define CLK_INFRA_AO_IRTX		46
+#define CLK_INFRA_AO_SSUSB		47
+#define CLK_INFRA_AO_DISP_PWM		48
+#define CLK_INFRA_AO_CLDMA_B		49
+#define CLK_INFRA_AO_AUDIO_26M_B	50
+#define CLK_INFRA_AO_SPI1		51
+#define CLK_INFRA_AO_SPI2		52
+#define CLK_INFRA_AO_SPI3		53
+#define CLK_INFRA_AO_UNIPRO_SYS		54
+#define CLK_INFRA_AO_UNIPRO_TICK	55
+#define CLK_INFRA_AO_UFS_MP_SAP_B	56
+#define CLK_INFRA_AO_PWRMCU		57
+#define CLK_INFRA_AO_PWRMCU_BUS_H	58
+#define CLK_INFRA_AO_APDMA_B		59
+#define CLK_INFRA_AO_SPI4		60
+#define CLK_INFRA_AO_SPI5		61
+#define CLK_INFRA_AO_CQ_DMA		62
+#define CLK_INFRA_AO_AES_UFSFDE		63
+#define CLK_INFRA_AO_AES		64
+#define CLK_INFRA_AO_UFS_TICK		65
+#define CLK_INFRA_AO_SSUSB_XHCI		66
+#define CLK_INFRA_AO_MSDC0_SELF		67
+#define CLK_INFRA_AO_MSDC1_SELF		68
+#define CLK_INFRA_AO_MSDC2_SELF		69
+#define CLK_INFRA_AO_I2S_DMA		70
+#define CLK_INFRA_AO_AP_MSDC0		71
+#define CLK_INFRA_AO_MD_MSDC0		72
+#define CLK_INFRA_AO_CG3_MSDC2		73
+#define CLK_INFRA_AO_GCPU		74
+#define CLK_INFRA_AO_PCIE_PERI_26M	75
+#define CLK_INFRA_AO_GCPU_66M_B		76
+#define CLK_INFRA_AO_GCPU_133M_B	77
+#define CLK_INFRA_AO_DISP_PWM1		78
+#define CLK_INFRA_AO_FBIST2FPC		79
+#define CLK_INFRA_AO_DEVICE_APC_SYNC	80
+#define CLK_INFRA_AO_PCIE_P1_PERI_26M	81
+#define CLK_INFRA_AO_SPIS0		82
+#define CLK_INFRA_AO_SPIS1		83
+#define CLK_INFRA_AO_133M_M_PERI	84
+#define CLK_INFRA_AO_66M_M_PERI		85
+#define CLK_INFRA_AO_PCIE_PL_P_250M_P0	86
+#define CLK_INFRA_AO_PCIE_PL_P_250M_P1	87
+#define CLK_INFRA_AO_PCIE_P1_TL_96M	88
+#define CLK_INFRA_AO_AES_MSDCFDE_0P	89
+#define CLK_INFRA_AO_UFS_TX_SYMBOL	90
+#define CLK_INFRA_AO_UFS_RX_SYMBOL	91
+#define CLK_INFRA_AO_UFS_RX_SYMBOL1	92
+#define CLK_INFRA_AO_PERI_UFS_MEM_SUB	93
+#define CLK_INFRA_AO_NR_CLK		94
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_NNAPLL		0
+#define CLK_APMIXED_RESPLL		1
+#define CLK_APMIXED_ETHPLL		2
+#define CLK_APMIXED_MSDCPLL		3
+#define CLK_APMIXED_TVDPLL1		4
+#define CLK_APMIXED_TVDPLL2		5
+#define CLK_APMIXED_MMPLL		6
+#define CLK_APMIXED_MAINPLL		7
+#define CLK_APMIXED_VDECPLL		8
+#define CLK_APMIXED_IMGPLL		9
+#define CLK_APMIXED_UNIVPLL		10
+#define CLK_APMIXED_HDMIPLL1		11
+#define CLK_APMIXED_HDMIPLL2		12
+#define CLK_APMIXED_HDMIRX_APLL		13
+#define CLK_APMIXED_USB1PLL		14
+#define CLK_APMIXED_ADSPPLL		15
+#define CLK_APMIXED_APLL1		16
+#define CLK_APMIXED_APLL2		17
+#define CLK_APMIXED_APLL3		18
+#define CLK_APMIXED_APLL4		19
+#define CLK_APMIXED_APLL5		20
+#define CLK_APMIXED_MFGPLL		21
+#define CLK_APMIXED_DGIPLL		22
+#define CLK_APMIXED_PLL_SSUSB26M	23
+#define CLK_APMIXED_NR_CLK		24
+
+/* NNASYS */
+
+#define CLK_NNA_NNA0			0
+#define CLK_NNA_NNA1			1
+#define CLK_NNA_NNA0_EMI		2
+#define CLK_NNA_CKGEN_MEM		3
+#define CLK_NNA_NNA1_EMI		4
+#define CLK_NNA_NNA0_AXI		5
+#define CLK_NNA_NNA1_AXI		6
+#define CLK_NNA_F26M			7
+#define CLK_NNA_AXI			8
+#define CLK_NNA_NR_CLK			9
+
+/* SCP_ADSP */
+
+#define CLK_SCP_ADSP_AUDIODSP		0
+#define CLK_SCP_ADSP_NR_CLK		1
+
+/* AUDSYS */
+
+#define CLK_AUD_AFE			0
+#define CLK_AUD_LRCK_CNT		1
+#define CLK_AUD_SPDIFIN_TUNER_APLL	2
+#define CLK_AUD_SPDIFIN_TUNER_DBG	3
+#define CLK_AUD_UL_TML			4
+#define CLK_AUD_APLL1_TUNER		5
+#define CLK_AUD_APLL2_TUNER		6
+#define CLK_AUD_TOP0_SPDF		7
+#define CLK_AUD_APLL			8
+#define CLK_AUD_APLL2			9
+#define CLK_AUD_DAC			10
+#define CLK_AUD_DAC_PREDIS		11
+#define CLK_AUD_TML			12
+#define CLK_AUD_ADC			13
+#define CLK_AUD_DAC_HIRES		14
+#define CLK_AUD_A1SYS_HP		15
+#define CLK_AUD_AFE_DMIC1		16
+#define CLK_AUD_AFE_DMIC2		17
+#define CLK_AUD_AFE_DMIC3		18
+#define CLK_AUD_AFE_DMIC4		19
+#define CLK_AUD_AFE_26M_DMIC_TM		20
+#define CLK_AUD_UL_TML_HIRES		21
+#define CLK_AUD_ADC_HIRES		22
+#define CLK_AUD_ADDA6_ADC		23
+#define CLK_AUD_ADDA6_ADC_HIRES		24
+#define CLK_AUD_LINEIN_TUNER		25
+#define CLK_AUD_EARC_TUNER		26
+#define CLK_AUD_I2SIN			27
+#define CLK_AUD_TDM_IN			28
+#define CLK_AUD_I2S_OUT			29
+#define CLK_AUD_TDM_OUT			30
+#define CLK_AUD_HDMI_OUT		31
+#define CLK_AUD_ASRC11			32
+#define CLK_AUD_ASRC12			33
+#define CLK_AUD_MULTI_IN		34
+#define CLK_AUD_INTDIR			35
+#define CLK_AUD_A1SYS			36
+#define CLK_AUD_A2SYS			37
+#define CLK_AUD_PCMIF			38
+#define CLK_AUD_A3SYS			39
+#define CLK_AUD_A4SYS			40
+#define CLK_AUD_MEMIF_UL1		41
+#define CLK_AUD_MEMIF_UL2		42
+#define CLK_AUD_MEMIF_UL3		43
+#define CLK_AUD_MEMIF_UL4		44
+#define CLK_AUD_MEMIF_UL5		45
+#define CLK_AUD_MEMIF_UL6		46
+#define CLK_AUD_MEMIF_UL8		47
+#define CLK_AUD_MEMIF_UL9		48
+#define CLK_AUD_MEMIF_UL10		49
+#define CLK_AUD_MEMIF_DL2		50
+#define CLK_AUD_MEMIF_DL3		51
+#define CLK_AUD_MEMIF_DL6		52
+#define CLK_AUD_MEMIF_DL7		53
+#define CLK_AUD_MEMIF_DL8		54
+#define CLK_AUD_MEMIF_DL10		55
+#define CLK_AUD_MEMIF_DL11		56
+#define CLK_AUD_GASRC0			57
+#define CLK_AUD_GASRC1			58
+#define CLK_AUD_GASRC2			59
+#define CLK_AUD_GASRC3			60
+#define CLK_AUD_GASRC4			61
+#define CLK_AUD_GASRC5			62
+#define CLK_AUD_GASRC6			63
+#define CLK_AUD_GASRC7			64
+#define CLK_AUD_GASRC8			65
+#define CLK_AUD_GASRC9			66
+#define CLK_AUD_GASRC10			67
+#define CLK_AUD_GASRC11			68
+#define CLK_AUD_GASRC12			69
+#define CLK_AUD_GASRC13			70
+#define CLK_AUD_GASRC14			71
+#define CLK_AUD_GASRC15			72
+#define CLK_AUD_GASRC16			73
+#define CLK_AUD_GASRC17			74
+#define CLK_AUD_GASRC18			75
+#define CLK_AUD_GASRC19			76
+#define CLK_AUD_NR_CLK			77
+
+/* AUDSYS_SRC */
+
+#define CLK_AUD_SRC_ASRC0		0
+#define CLK_AUD_SRC_ASRC1		1
+#define CLK_AUD_SRC_ASRC2		2
+#define CLK_AUD_SRC_ASRC3		3
+#define CLK_AUD_SRC_ASRC4		4
+#define CLK_AUD_SRC_ASRC5		5
+#define CLK_AUD_SRC_ASRC6		6
+#define CLK_AUD_SRC_ASRC7		7
+#define CLK_AUD_SRC_ASRC8		8
+#define CLK_AUD_SRC_ASRC9		9
+#define CLK_AUD_SRC_ASRC10		10
+#define CLK_AUD_SRC_ASRC11		11
+#define CLK_AUD_SRC_NR_CLK		12
+
+/* PERICFG_AO */
+
+#define CLK_PERI_AO_ETHERNET		0
+#define CLK_PERI_AO_ETHERNET_BUS	1
+#define CLK_PERI_AO_FLASHIF_BUS		2
+#define CLK_PERI_AO_FLASHIF_FLASH	3
+#define CLK_PERI_AO_SSUSB_1P_BUS	4
+#define CLK_PERI_AO_SSUSB_1P_XHCI	5
+#define CLK_PERI_AO_SSUSB_2P_BUS	6
+#define CLK_PERI_AO_SSUSB_2P_XHCI	7
+#define CLK_PERI_AO_SSUSB_3P_BUS	8
+#define CLK_PERI_AO_SSUSB_3P_XHCI	9
+#define CLK_PERI_AO_SPINFI		10
+#define CLK_PERI_AO_ETHERNET_MAC	11
+#define CLK_PERI_AO_NFI_H		12
+#define CLK_PERI_AO_FNFI1X		13
+#define CLK_PERI_AO_PCIE_P0_MEM		14
+#define CLK_PERI_AO_PCIE_P1_MEM		15
+#define CLK_PERI_AO_NR_CLK		16
+
+/* IMP_IIC_WRAP_S */
+
+#define CLK_IMP_IIC_WRAP_S_I2C5		0
+#define CLK_IMP_IIC_WRAP_S_I2C6		1
+#define CLK_IMP_IIC_WRAP_S_I2C7		2
+#define CLK_IMP_IIC_WRAP_S_NR_CLK	3
+
+/* IMP_IIC_WRAP_W */
+
+#define CLK_IMP_IIC_WRAP_W_I2C0		0
+#define CLK_IMP_IIC_WRAP_W_I2C1		1
+#define CLK_IMP_IIC_WRAP_W_I2C2		2
+#define CLK_IMP_IIC_WRAP_W_I2C3		3
+#define CLK_IMP_IIC_WRAP_W_I2C4		4
+#define CLK_IMP_IIC_WRAP_W_NR_CLK	5
+
+/* MFGCFG */
+
+#define CLK_MFG_BG3D			0
+#define CLK_MFG_NR_CLK			1
+
+/* VPPSYS0 */
+
+#define CLK_VPP0_MDP_FG				0
+#define CLK_VPP0_STITCH				1
+#define CLK_VPP0_PADDING			2
+#define CLK_VPP0_MDP_TCC			3
+#define CLK_VPP0_WARP0_ASYNC_TX			4
+#define CLK_VPP0_WARP1_ASYNC_TX			5
+#define CLK_VPP0_MUTEX				6
+#define CLK_VPP0_VPP02VPP1_RELAY		7
+#define CLK_VPP0_VPP12VPP0_ASYNC		8
+#define CLK_VPP0_MMSYSRAM_TOP			9
+#define CLK_VPP0_MDP_AAL			10
+#define CLK_VPP0_MDP_RSZ			11
+#define CLK_VPP0_SMI_COMMON			12
+#define CLK_VPP0_GALS_VDO0_LARB0		13
+#define CLK_VPP0_GALS_VDO0_LARB1		14
+#define CLK_VPP0_GALS_VENCSYS			15
+#define CLK_VPP0_GALS_VENCSYS_CORE1		16
+#define CLK_VPP0_GALS_INFRA			17
+#define CLK_VPP0_GALS_CAMSYS			18
+#define CLK_VPP0_GALS_VPP1_LARB5		19
+#define CLK_VPP0_GALS_VPP1_LARB6		20
+#define CLK_VPP0_SMI_REORDER			21
+#define CLK_VPP0_SMI_IOMMU			22
+#define CLK_VPP0_GALS_IMGSYS_CAMSYS		23
+#define CLK_VPP0_MDP_RDMA			24
+#define CLK_VPP0_MDP_WROT			25
+#define CLK_VPP0_GALS_EMI0_EMI1			26
+#define CLK_VPP0_SMI_SUB_COMMON_REORDER		27
+#define CLK_VPP0_SMI_RSI			28
+#define CLK_VPP0_SMI_COMMON_LARB4		29
+#define CLK_VPP0_GALS_VDEC_VDEC_CORE1		30
+#define CLK_VPP0_GALS_VPP1_WPE			31
+#define CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1	32
+#define CLK_VPP0_FAKE_ENG			33
+#define CLK_VPP0_MDP_HDR			34
+#define CLK_VPP0_MDP_TDSHP			35
+#define CLK_VPP0_MDP_COLOR			36
+#define CLK_VPP0_MDP_OVL			37
+#define CLK_VPP0_WARP0_RELAY			38
+#define CLK_VPP0_WARP0_MDP_DL_ASYNC		39
+#define CLK_VPP0_WARP1_RELAY			40
+#define CLK_VPP0_WARP1_MDP_DL_ASYNC		41
+#define CLK_VPP0_NR_CLK				42
+
+/* WPESYS */
+
+#define CLK_WPE_VPP0			0
+#define CLK_WPE_VPP1			1
+#define CLK_WPE_SMI_LARB7		2
+#define CLK_WPE_SMI_LARB8		3
+#define CLK_WPE_EVENT_TX		4
+#define CLK_WPE_SMI_LARB7_P		5
+#define CLK_WPE_SMI_LARB8_P		6
+#define CLK_WPE_NR_CLK			7
+
+/* WPESYS_VPP0 */
+
+#define CLK_WPE_VPP0_VECI		0
+#define CLK_WPE_VPP0_VEC2I		1
+#define CLK_WPE_VPP0_VEC3I		2
+#define CLK_WPE_VPP0_WPEO		3
+#define CLK_WPE_VPP0_MSKO		4
+#define CLK_WPE_VPP0_VGEN		5
+#define CLK_WPE_VPP0_EXT		6
+#define CLK_WPE_VPP0_VFC		7
+#define CLK_WPE_VPP0_CACH0_TOP		8
+#define CLK_WPE_VPP0_CACH0_DMA		9
+#define CLK_WPE_VPP0_CACH1_TOP		10
+#define CLK_WPE_VPP0_CACH1_DMA		11
+#define CLK_WPE_VPP0_CACH2_TOP		12
+#define CLK_WPE_VPP0_CACH2_DMA		13
+#define CLK_WPE_VPP0_CACH3_TOP		14
+#define CLK_WPE_VPP0_CACH3_DMA		15
+#define CLK_WPE_VPP0_PSP		16
+#define CLK_WPE_VPP0_PSP2		17
+#define CLK_WPE_VPP0_SYNC		18
+#define CLK_WPE_VPP0_C24		19
+#define CLK_WPE_VPP0_MDP_CROP		20
+#define CLK_WPE_VPP0_ISP_CROP		21
+#define CLK_WPE_VPP0_TOP		22
+#define CLK_WPE_VPP0_NR_CLK		23
+
+/* WPESYS_VPP1 */
+
+#define CLK_WPE_VPP1_VECI		0
+#define CLK_WPE_VPP1_VEC2I		1
+#define CLK_WPE_VPP1_VEC3I		2
+#define CLK_WPE_VPP1_WPEO		3
+#define CLK_WPE_VPP1_MSKO		4
+#define CLK_WPE_VPP1_VGEN		5
+#define CLK_WPE_VPP1_EXT		6
+#define CLK_WPE_VPP1_VFC		7
+#define CLK_WPE_VPP1_CACH0_TOP		8
+#define CLK_WPE_VPP1_CACH0_DMA		9
+#define CLK_WPE_VPP1_CACH1_TOP		10
+#define CLK_WPE_VPP1_CACH1_DMA		11
+#define CLK_WPE_VPP1_CACH2_TOP		12
+#define CLK_WPE_VPP1_CACH2_DMA		13
+#define CLK_WPE_VPP1_CACH3_TOP		14
+#define CLK_WPE_VPP1_CACH3_DMA		15
+#define CLK_WPE_VPP1_PSP		16
+#define CLK_WPE_VPP1_PSP2		17
+#define CLK_WPE_VPP1_SYNC		18
+#define CLK_WPE_VPP1_C24		19
+#define CLK_WPE_VPP1_MDP_CROP		20
+#define CLK_WPE_VPP1_ISP_CROP		21
+#define CLK_WPE_VPP1_TOP		22
+#define CLK_WPE_VPP1_NR_CLK		23
+
+/* VPPSYS1 */
+
+#define CLK_VPP1_SVPP1_MDP_OVL		0
+#define CLK_VPP1_SVPP1_MDP_TCC		1
+#define CLK_VPP1_SVPP1_MDP_WROT		2
+#define CLK_VPP1_SVPP1_VPP_PAD		3
+#define CLK_VPP1_SVPP2_MDP_WROT		4
+#define CLK_VPP1_SVPP2_VPP_PAD		5
+#define CLK_VPP1_SVPP3_MDP_WROT		6
+#define CLK_VPP1_SVPP3_VPP_PAD		7
+#define CLK_VPP1_SVPP1_MDP_RDMA		8
+#define CLK_VPP1_SVPP1_MDP_FG		9
+#define CLK_VPP1_SVPP2_MDP_RDMA		10
+#define CLK_VPP1_SVPP2_MDP_FG		11
+#define CLK_VPP1_SVPP3_MDP_RDMA		12
+#define CLK_VPP1_SVPP3_MDP_FG		13
+#define CLK_VPP1_VPP_SPLIT		14
+#define CLK_VPP1_SVPP2_VDO0_DL_RELAY	15
+#define CLK_VPP1_SVPP1_MDP_TDSHP	16
+#define CLK_VPP1_SVPP1_MDP_COLOR	17
+#define CLK_VPP1_SVPP3_VDO1_DL_RELAY	18
+#define CLK_VPP1_SVPP2_VPP_MERGE	19
+#define CLK_VPP1_SVPP2_MDP_COLOR	20
+#define CLK_VPP1_VPPSYS1_GALS		21
+#define CLK_VPP1_SVPP3_VPP_MERGE	22
+#define CLK_VPP1_SVPP3_MDP_COLOR	23
+#define CLK_VPP1_VPPSYS1_LARB		24
+#define CLK_VPP1_SVPP1_MDP_RSZ		25
+#define CLK_VPP1_SVPP1_MDP_HDR		26
+#define CLK_VPP1_SVPP1_MDP_AAL		27
+#define CLK_VPP1_SVPP2_MDP_HDR		28
+#define CLK_VPP1_SVPP2_MDP_AAL		29
+#define CLK_VPP1_DL_ASYNC		30
+#define CLK_VPP1_LARB5_FAKE_ENG		31
+#define CLK_VPP1_SVPP3_MDP_HDR		32
+#define CLK_VPP1_SVPP3_MDP_AAL		33
+#define CLK_VPP1_SVPP2_VDO1_DL_RELAY	34
+#define CLK_VPP1_LARB6_FAKE_ENG		35
+#define CLK_VPP1_SVPP2_MDP_RSZ		36
+#define CLK_VPP1_SVPP3_MDP_RSZ		37
+#define CLK_VPP1_SVPP3_VDO0_DL_RELAY	38
+#define CLK_VPP1_DISP_MUTEX		39
+#define CLK_VPP1_SVPP2_MDP_TDSHP	40
+#define CLK_VPP1_SVPP3_MDP_TDSHP	41
+#define CLK_VPP1_VPP0_DL1_RELAY		42
+#define CLK_VPP1_HDMI_META		43
+#define CLK_VPP1_VPP_SPLIT_HDMI		44
+#define CLK_VPP1_DGI_IN			45
+#define CLK_VPP1_DGI_OUT		46
+#define CLK_VPP1_VPP_SPLIT_DGI		47
+#define CLK_VPP1_VPP0_DL_ASYNC		48
+#define CLK_VPP1_VPP0_DL_RELAY		49
+#define CLK_VPP1_VPP_SPLIT_26M		50
+#define CLK_VPP1_NR_CLK			51
+
+/* IMGSYS */
+
+#define CLK_IMG_LARB9			0
+#define CLK_IMG_TRAW0			1
+#define CLK_IMG_TRAW1			2
+#define CLK_IMG_TRAW2			3
+#define CLK_IMG_TRAW3			4
+#define CLK_IMG_DIP0			5
+#define CLK_IMG_WPE0			6
+#define CLK_IMG_IPE			7
+#define CLK_IMG_DIP1			8
+#define CLK_IMG_WPE1			9
+#define CLK_IMG_GALS			10
+#define CLK_IMG_NR_CLK			11
+
+/* IMGSYS1_DIP_TOP */
+
+#define CLK_IMG1_DIP_TOP_LARB10		0
+#define CLK_IMG1_DIP_TOP_DIP_TOP	1
+#define CLK_IMG1_DIP_TOP_NR_CLK		2
+
+/* IMGSYS1_DIP_NR */
+
+#define CLK_IMG1_DIP_NR_RESERVE		0
+#define CLK_IMG1_DIP_NR_DIP_NR		1
+#define CLK_IMG1_DIP_NR_NR_CLK		2
+
+/* IMGSYS1_WPE */
+
+#define CLK_IMG1_WPE_LARB11		0
+#define CLK_IMG1_WPE_WPE		1
+#define CLK_IMG1_WPE_NR_CLK		2
+
+/* IPESYS */
+
+#define CLK_IPE_DPE			0
+#define CLK_IPE_FDVT			1
+#define CLK_IPE_ME			2
+#define CLK_IPE_TOP			3
+#define CLK_IPE_SMI_LARB12		4
+#define CLK_IPE_NR_CLK			5
+
+/* CAMSYS */
+
+#define CLK_CAM_LARB13			0
+#define CLK_CAM_LARB14			1
+#define CLK_CAM_MAIN_CAM		2
+#define CLK_CAM_MAIN_CAMTG		3
+#define CLK_CAM_SENINF			4
+#define CLK_CAM_GCAMSVA			5
+#define CLK_CAM_GCAMSVB			6
+#define CLK_CAM_GCAMSVC			7
+#define CLK_CAM_SCAMSA			8
+#define CLK_CAM_SCAMSB			9
+#define CLK_CAM_CAMSV_TOP		10
+#define CLK_CAM_CAMSV_CQ		11
+#define CLK_CAM_ADL			12
+#define CLK_CAM_ASG			13
+#define CLK_CAM_PDA			14
+#define CLK_CAM_FAKE_ENG		15
+#define CLK_CAM_MAIN_MRAW0		16
+#define CLK_CAM_MAIN_MRAW1		17
+#define CLK_CAM_MAIN_MRAW2		18
+#define CLK_CAM_MAIN_MRAW3		19
+#define CLK_CAM_CAM2MM0_GALS		20
+#define CLK_CAM_CAM2MM1_GALS		21
+#define CLK_CAM_CAM2SYS_GALS		22
+#define CLK_CAM_NR_CLK			23
+
+/* CAMSYS_RAWA */
+
+#define CLK_CAM_RAWA_LARBX		0
+#define CLK_CAM_RAWA_CAM		1
+#define CLK_CAM_RAWA_CAMTG		2
+#define CLK_CAM_RAWA_NR_CLK		3
+
+/* CAMSYS_YUVA */
+
+#define CLK_CAM_YUVA_LARBX		0
+#define CLK_CAM_YUVA_CAM		1
+#define CLK_CAM_YUVA_CAMTG		2
+#define CLK_CAM_YUVA_NR_CLK		3
+
+/* CAMSYS_RAWB */
+
+#define CLK_CAM_RAWB_LARBX		0
+#define CLK_CAM_RAWB_CAM		1
+#define CLK_CAM_RAWB_CAMTG		2
+#define CLK_CAM_RAWB_NR_CLK		3
+
+/* CAMSYS_YUVB */
+
+#define CLK_CAM_YUVB_LARBX		0
+#define CLK_CAM_YUVB_CAM		1
+#define CLK_CAM_YUVB_CAMTG		2
+#define CLK_CAM_YUVB_NR_CLK		3
+
+/* CAMSYS_MRAW */
+
+#define CLK_CAM_MRAW_LARBX		0
+#define CLK_CAM_MRAW_CAMTG		1
+#define CLK_CAM_MRAW_MRAW0		2
+#define CLK_CAM_MRAW_MRAW1		3
+#define CLK_CAM_MRAW_MRAW2		4
+#define CLK_CAM_MRAW_MRAW3		5
+#define CLK_CAM_MRAW_NR_CLK		6
+
+/* CCUSYS */
+
+#define CLK_CCU_LARB18			0
+#define CLK_CCU_AHB			1
+#define CLK_CCU_CCU0			2
+#define CLK_CCU_CCU1			3
+#define CLK_CCU_NR_CLK			4
+
+/* VDECSYS_SOC */
+
+#define CLK_VDEC_SOC_LARB1		0
+#define CLK_VDEC_SOC_LAT		1
+#define CLK_VDEC_SOC_VDEC		2
+#define CLK_VDEC_SOC_NR_CLK		3
+
+/* VDECSYS */
+
+#define CLK_VDEC_LARB1			0
+#define CLK_VDEC_LAT			1
+#define CLK_VDEC_VDEC			2
+#define CLK_VDEC_NR_CLK			3
+
+/* VDECSYS_CORE1 */
+
+#define CLK_VDEC_CORE1_LARB1		0
+#define CLK_VDEC_CORE1_LAT		1
+#define CLK_VDEC_CORE1_VDEC		2
+#define CLK_VDEC_CORE1_NR_CLK		3
+
+/* APUSYS_PLL */
+
+#define CLK_APUSYS_PLL_APUPLL		0
+#define CLK_APUSYS_PLL_NPUPLL		1
+#define CLK_APUSYS_PLL_APUPLL1		2
+#define CLK_APUSYS_PLL_APUPLL2		3
+#define CLK_APUSYS_PLL_NR_CLK		4
+
+/* VENCSYS */
+
+#define CLK_VENC_LARB			0
+#define CLK_VENC_VENC			1
+#define CLK_VENC_JPGENC			2
+#define CLK_VENC_JPGDEC			3
+#define CLK_VENC_JPGDEC_C1		4
+#define CLK_VENC_GALS			5
+#define CLK_VENC_NR_CLK			6
+
+/* VENCSYS_CORE1 */
+
+#define CLK_VENC_CORE1_LARB		0
+#define CLK_VENC_CORE1_VENC		1
+#define CLK_VENC_CORE1_JPGENC		2
+#define CLK_VENC_CORE1_JPGDEC		3
+#define CLK_VENC_CORE1_JPGDEC_C1	4
+#define CLK_VENC_CORE1_GALS		5
+#define CLK_VENC_CORE1_NR_CLK		6
+
+/* VDOSYS0 */
+
+#define CLK_VDO0_DISP_OVL0		0
+#define CLK_VDO0_DISP_COLOR0		1
+#define CLK_VDO0_DISP_COLOR1		2
+#define CLK_VDO0_DISP_CCORR0		3
+#define CLK_VDO0_DISP_CCORR1		4
+#define CLK_VDO0_DISP_AAL0		5
+#define CLK_VDO0_DISP_AAL1		6
+#define CLK_VDO0_DISP_GAMMA0		7
+#define CLK_VDO0_DISP_GAMMA1		8
+#define CLK_VDO0_DISP_DITHER0		9
+#define CLK_VDO0_DISP_DITHER1		10
+#define CLK_VDO0_DISP_OVL1		11
+#define CLK_VDO0_DISP_WDMA0		12
+#define CLK_VDO0_DISP_WDMA1		13
+#define CLK_VDO0_DISP_RDMA0		14
+#define CLK_VDO0_DISP_RDMA1		15
+#define CLK_VDO0_DSI0			16
+#define CLK_VDO0_DSI1			17
+#define CLK_VDO0_DSC_WRAP0		18
+#define CLK_VDO0_VPP_MERGE0		19
+#define CLK_VDO0_DP_INTF0		20
+#define CLK_VDO0_DISP_MUTEX0		21
+#define CLK_VDO0_DISP_IL_ROT0		22
+#define CLK_VDO0_APB_BUS		23
+#define CLK_VDO0_FAKE_ENG0		24
+#define CLK_VDO0_FAKE_ENG1		25
+#define CLK_VDO0_DL_ASYNC0		26
+#define CLK_VDO0_DL_ASYNC1		27
+#define CLK_VDO0_DL_ASYNC2		28
+#define CLK_VDO0_DL_ASYNC3		29
+#define CLK_VDO0_DL_ASYNC4		30
+#define CLK_VDO0_DISP_MONITOR0		31
+#define CLK_VDO0_DISP_MONITOR1		32
+#define CLK_VDO0_DISP_MONITOR2		33
+#define CLK_VDO0_DISP_MONITOR3		34
+#define CLK_VDO0_DISP_MONITOR4		35
+#define CLK_VDO0_SMI_GALS		36
+#define CLK_VDO0_SMI_COMMON		37
+#define CLK_VDO0_SMI_EMI		38
+#define CLK_VDO0_SMI_IOMMU		39
+#define CLK_VDO0_SMI_LARB		40
+#define CLK_VDO0_SMI_RSI		41
+#define CLK_VDO0_DSI0_DSI		42
+#define CLK_VDO0_DSI1_DSI		43
+#define CLK_VDO0_DP_INTF0_DP_INTF	44
+#define CLK_VDO0_NR_CLK			45
+
+/* VDOSYS1 */
+
+#define CLK_VDO1_SMI_LARB2			0
+#define CLK_VDO1_SMI_LARB3			1
+#define CLK_VDO1_GALS				2
+#define CLK_VDO1_FAKE_ENG0			3
+#define CLK_VDO1_FAKE_ENG			4
+#define CLK_VDO1_MDP_RDMA0			5
+#define CLK_VDO1_MDP_RDMA1			6
+#define CLK_VDO1_MDP_RDMA2			7
+#define CLK_VDO1_MDP_RDMA3			8
+#define CLK_VDO1_VPP_MERGE0			9
+#define CLK_VDO1_VPP_MERGE1			10
+#define CLK_VDO1_VPP_MERGE2			11
+#define CLK_VDO1_VPP_MERGE3			12
+#define CLK_VDO1_VPP_MERGE4			13
+#define CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC		14
+#define CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC		15
+#define CLK_VDO1_DISP_MUTEX			16
+#define CLK_VDO1_MDP_RDMA4			17
+#define CLK_VDO1_MDP_RDMA5			18
+#define CLK_VDO1_MDP_RDMA6			19
+#define CLK_VDO1_MDP_RDMA7			20
+#define CLK_VDO1_DP_INTF0_MM			21
+#define CLK_VDO1_DPI0_MM			22
+#define CLK_VDO1_DPI1_MM			23
+#define CLK_VDO1_DISP_MONITOR			24
+#define CLK_VDO1_MERGE0_DL_ASYNC		25
+#define CLK_VDO1_MERGE1_DL_ASYNC		26
+#define CLK_VDO1_MERGE2_DL_ASYNC		27
+#define CLK_VDO1_MERGE3_DL_ASYNC		28
+#define CLK_VDO1_MERGE4_DL_ASYNC		29
+#define CLK_VDO1_VDO0_DSC_TO_VDO1_DL_ASYNC	30
+#define CLK_VDO1_VDO0_MERGE_TO_VDO1_DL_ASYNC	31
+#define CLK_VDO1_HDR_VDO_FE0			32
+#define CLK_VDO1_HDR_GFX_FE0			33
+#define CLK_VDO1_HDR_VDO_BE			34
+#define CLK_VDO1_HDR_VDO_FE1			35
+#define CLK_VDO1_HDR_GFX_FE1			36
+#define CLK_VDO1_DISP_MIXER			37
+#define CLK_VDO1_HDR_VDO_FE0_DL_ASYNC		38
+#define CLK_VDO1_HDR_VDO_FE1_DL_ASYNC		39
+#define CLK_VDO1_HDR_GFX_FE0_DL_ASYNC		40
+#define CLK_VDO1_HDR_GFX_FE1_DL_ASYNC		41
+#define CLK_VDO1_HDR_VDO_BE_DL_ASYNC		42
+#define CLK_VDO1_DPI0				43
+#define CLK_VDO1_DISP_MONITOR_DPI0		44
+#define CLK_VDO1_DPI1				45
+#define CLK_VDO1_DISP_MONITOR_DPI1		46
+#define CLK_VDO1_DPINTF				47
+#define CLK_VDO1_DISP_MONITOR_DPINTF		48
+#define CLK_VDO1_26M_SLOW			49
+#define CLK_VDO1_NR_CLK				50
+
+#endif /* _DT_BINDINGS_CLK_MT8195_H */
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
  2021-06-16 22:47 ` [PATCH 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock Chun-Jie Chen
  2021-06-16 22:47 ` [PATCH 02/22] clk: mediatek: Add dt-bindings of MT8195 clocks Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-06-30  7:31   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 04/22] clk: mediatek: Add MT8195 basic clocks support Chun-Jie Chen
                   ` (18 subsequent siblings)
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

On MT8195, tuner_en_reg is moved to register offest 0x0.
If we only judge by tuner_en_reg, it may lead to wrong address.
Add tuner_en_bit to the check condition. And it has been confirmed,
on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by
clock square control.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/clk-pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 7fb001a4e7d8..99ada6e06697 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -332,7 +332,7 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
 		pll->pcw_chg_addr = pll->base_addr + REG_CON1;
 	if (data->tuner_reg)
 		pll->tuner_addr = base + data->tuner_reg;
-	if (data->tuner_en_reg)
+	if (data->tuner_en_reg || data->tuner_en_bit)
 		pll->tuner_en_addr = base + data->tuner_en_reg;
 	if (data->en_reg)
 		pll->en_addr = base + data->en_reg;
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 04/22] clk: mediatek: Add MT8195 basic clocks support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (2 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-07-02 11:44   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 05/22] clk: mediatek: Add MT8195 audio clock support Chun-Jie Chen
                   ` (17 subsequent siblings)
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 basic clock providers, include topckgen, apmixedsys,
infracfg_ao and pericfg_ao.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig      |    8 +
 drivers/clk/mediatek/Makefile     |    1 +
 drivers/clk/mediatek/clk-mt8195.c | 1958 +++++++++++++++++++++++++++++
 3 files changed, 1967 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 576babd86f98..6707aba3d500 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -580,6 +580,14 @@ config COMMON_CLK_MT8192_VENCSYS
 	help
 	  This driver supports MediaTek MT8192 vencsys clocks.
 
+config COMMON_CLK_MT8195
+	bool "Clock driver for MediaTek MT8195"
+	depends on ARM64 || COMPILE_TEST
+	select COMMON_CLK_MEDIATEK
+	default ARM64
+	help
+	  This driver supports MediaTek MT8195 basic clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 15bc045f0b71..f8002d8966e1 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -80,5 +80,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk-mt8192-msdc.o
 obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o
 obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
 obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
+obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c
new file mode 100644
index 000000000000..aea9ebe4c051
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195.c
@@ -0,0 +1,1958 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "clk-mtk.h"
+#include "clk-mux.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static DEFINE_SPINLOCK(mt8195_clk_lock);
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+	FIXED_CLK(CLK_TOP_IN_DGI, "in_dgi", NULL, 165000000),
+	FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 248000000),
+	FIXED_CLK(CLK_TOP_ULPOSC2, "ulposc2", NULL, 326000000),
+	FIXED_CLK(CLK_TOP_MEM_466M, "mem_466m", NULL, 533000000),
+	FIXED_CLK(CLK_TOP_MPHONE_SLAVE_B, "mphone_slave_b", NULL, 49152000),
+	FIXED_CLK(CLK_TOP_PEXTP_PIPE, "pextp_pipe", NULL, 250000000),
+	FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL, "ufs_rx_symbol", NULL, 166000000),
+	FIXED_CLK(CLK_TOP_UFS_TX_SYMBOL, "ufs_tx_symbol", NULL, 166000000),
+	FIXED_CLK(CLK_TOP_SSUSB_U3PHY_P1_P_P0, "ssusb_u3phy_p1_p_p0", NULL, 131000000),
+	FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL1, "ufs_rx_symbol1", NULL, 166000000),
+	FIXED_CLK(CLK_TOP_FPC, "fpc", NULL, 50000000),
+	FIXED_CLK(CLK_TOP_HDMIRX_P, "hdmirx_p", NULL, 594000000),
+};
+
+static const struct mtk_fixed_factor top_early_divs[] = {
+	FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
+};
+
+static const struct mtk_fixed_factor top_divs[] = {
+	FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m", 1, 52),
+	FACTOR(CLK_TOP_IN_DGI_D2, "in_dgi_d2", "in_dgi", 1, 2),
+	FACTOR(CLK_TOP_IN_DGI_D4, "in_dgi_d4", "in_dgi", 1, 4),
+	FACTOR(CLK_TOP_IN_DGI_D6, "in_dgi_d6", "in_dgi", 1, 6),
+	FACTOR(CLK_TOP_IN_DGI_D8, "in_dgi_d8", "in_dgi", 1, 8),
+	FACTOR(CLK_TOP_MFGPLL_OPP, "mfgpll_opp", "mfgpll", 1, 1),
+	FACTOR(CLK_TOP_MAINPLL, "mainpll_ck", "mainpll", 1, 1),
+	FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll_ck", 1, 3),
+	FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll_ck", 1, 4),
+	FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2),
+	FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4),
+	FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8),
+	FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll_ck", 1, 5),
+	FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
+	FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
+	FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8),
+	FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll_ck", 1, 6),
+	FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2),
+	FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4),
+	FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8),
+	FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll_ck", 1, 7),
+	FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
+	FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
+	FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8),
+	FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll_ck", 1, 9),
+	FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1),
+	FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 2),
+	FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1, 3),
+	FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll_ck", 1, 4),
+	FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2),
+	FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4),
+	FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8),
+	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1, 5),
+	FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
+	FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
+	FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
+	FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll_ck", 1, 6),
+	FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2),
+	FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4),
+	FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8),
+	FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16),
+	FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1, 7),
+	FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13),
+	FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
+	FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
+	FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
+	FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
+	FACTOR(CLK_TOP_IMGPLL, "imgpll_ck", "imgpll", 1, 1),
+	FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
+	FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1, 3),
+	FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4),
+	FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
+	FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1, 3),
+	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4),
+	FACTOR(CLK_TOP_APLL3, "apll3_ck", "apll3", 1, 1),
+	FACTOR(CLK_TOP_APLL3_D4, "apll3_d4", "apll3_ck", 1, 4),
+	FACTOR(CLK_TOP_APLL4, "apll4_ck", "apll4", 1, 1),
+	FACTOR(CLK_TOP_APLL4_D4, "apll4_d4", "apll4_ck", 1, 4),
+	FACTOR(CLK_TOP_APLL5, "apll5_ck", "apll5", 1, 1),
+	FACTOR(CLK_TOP_APLL5_D4, "apll5_d4", "apll5_ck", 1, 4),
+	FACTOR(CLK_TOP_HDMIRX_APLL, "hdmirx_apll_ck", "hdmirx_apll", 1, 1),
+	FACTOR(CLK_TOP_HDMIRX_APLL_D3, "hdmirx_apll_d3", "hdmirx_apll_ck", 1, 3),
+	FACTOR(CLK_TOP_HDMIRX_APLL_D4, "hdmirx_apll_d4", "hdmirx_apll_ck", 1, 4),
+	FACTOR(CLK_TOP_HDMIRX_APLL_D6, "hdmirx_apll_d6", "hdmirx_apll_ck", 1, 6),
+	FACTOR(CLK_TOP_NNAPLL, "nnapll_ck", "nnapll", 1, 1),
+	FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
+	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_ck", 1, 4),
+	FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
+	FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
+	FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll_ck", 1, 5),
+	FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
+	FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
+	FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_ck", 1, 6),
+	FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2),
+	FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll_ck", 1, 7),
+	FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll_ck", 1, 9),
+	FACTOR(CLK_TOP_TVDPLL1, "tvdpll1_ck", "tvdpll1", 1, 1),
+	FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1_ck", 1, 2),
+	FACTOR(CLK_TOP_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1_ck", 1, 4),
+	FACTOR(CLK_TOP_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1_ck", 1, 8),
+	FACTOR(CLK_TOP_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1_ck", 1, 16),
+	FACTOR(CLK_TOP_TVDPLL2, "tvdpll2_ck", "tvdpll2", 1, 1),
+	FACTOR(CLK_TOP_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2_ck", 1, 2),
+	FACTOR(CLK_TOP_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2_ck", 1, 4),
+	FACTOR(CLK_TOP_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2_ck", 1, 8),
+	FACTOR(CLK_TOP_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2_ck", 1, 16),
+	FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
+	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
+	FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4),
+	FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll_ck", 1, 16),
+	FACTOR(CLK_TOP_ETHPLL, "ethpll_ck", "ethpll", 1, 1),
+	FACTOR(CLK_TOP_ETHPLL_D2, "ethpll_d2", "ethpll_ck", 1, 2),
+	FACTOR(CLK_TOP_ETHPLL_D8, "ethpll_d8", "ethpll_ck", 1, 8),
+	FACTOR(CLK_TOP_ETHPLL_D10, "ethpll_d10", "ethpll_ck", 1, 10),
+	FACTOR(CLK_TOP_DGIPLL, "dgipll_ck", "dgipll", 1, 1),
+	FACTOR(CLK_TOP_DGIPLL_D2, "dgipll_d2", "dgipll_ck", 1, 2),
+	FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1),
+	FACTOR(CLK_TOP_ULPOSC_D2, "ulposc_d2", "ulposc", 1, 2),
+	FACTOR(CLK_TOP_ULPOSC_D4, "ulposc_d4", "ulposc", 1, 4),
+	FACTOR(CLK_TOP_ULPOSC_D7, "ulposc_d7", "ulposc", 1, 7),
+	FACTOR(CLK_TOP_ULPOSC_D8, "ulposc_d8", "ulposc", 1, 8),
+	FACTOR(CLK_TOP_ULPOSC_D10, "ulposc_d10", "ulposc", 1, 10),
+	FACTOR(CLK_TOP_ULPOSC_D16, "ulposc_d16", "ulposc", 1, 16),
+	FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1),
+	FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll_ck", 1, 2),
+	FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll_ck", 1, 4),
+	FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll_ck", 1, 8),
+};
+
+static const char * const axi_parents[] = {
+	"clk26m",
+	"mainpll_d4_d4",
+	"mainpll_d7_d2",
+	"mainpll_d4_d2",
+	"mainpll_d5_d2",
+	"mainpll_d6_d2",
+	"ulposc_d4"
+};
+
+static const char * const spm_parents[] = {
+	"clk26m",
+	"ulposc_d10",
+	"mainpll_d7_d4",
+	"clk32k"
+};
+
+static const char * const bus_aximem_parents[] = {
+	"clk26m",
+	"mainpll_d7_d2",
+	"mainpll_d4_d2",
+	"mainpll_d5_d2",
+	"mainpll_d6"
+};
+
+static const char * const vpp_parents[] = {
+	"clk26m",
+	"univpll_d6_d2",
+	"mainpll_d5_d2",
+	"mmpll_d6_d2",
+	"univpll_d5_d2",
+	"univpll_d4_d2",
+	"mmpll_d4_d2",
+	"mmpll_d7",
+	"univpll_d6",
+	"mainpll_d4",
+	"mmpll_d5",
+	"tvdpll1_ck",
+	"tvdpll2_ck",
+	"univpll_d4",
+	"mmpll_d4"
+};
+
+static const char * const ethdr_parents[] = {
+	"clk26m",
+	"univpll_d6_d2",
+	"mainpll_d5_d2",
+	"mmpll_d6_d2",
+	"univpll_d5_d2",
+	"univpll_d4_d2",
+	"mmpll_d4_d2",
+	"mmpll_d7",
+	"univpll_d6",
+	"mainpll_d4",
+	"mmpll_d5_d4",
+	"tvdpll1_ck",
+	"tvdpll2_ck",
+	"univpll_d4",
+	"mmpll_d4"
+};
+
+static const char * const ipe_parents[] = {
+	"clk26m",
+	"imgpll_ck",
+	"mainpll_d4",
+	"mmpll_d6",
+	"univpll_d6",
+	"mainpll_d6",
+	"mmpll_d4_d2",
+	"univpll_d4_d2",
+	"mainpll_d4_d2",
+	"mmpll_d6_d2",
+	"univpll_d5_d2"
+};
+
+static const char * const cam_parents[] = {
+	"clk26m",
+	"mainpll_d4",
+	"mmpll_d4",
+	"univpll_d4",
+	"univpll_d5",
+	"univpll_d6",
+	"mmpll_d7",
+	"univpll_d4_d2",
+	"mainpll_d4_d2",
+	"imgpll_ck"
+};
+
+static const char * const ccu_parents[] = {
+	"clk26m",
+	"univpll_d6",
+	"mainpll_d4_d2",
+	"mainpll_d4",
+	"univpll_d5",
+	"mainpll_d6",
+	"mmpll_d6",
+	"mmpll_d7",
+	"univpll_d4_d2",
+	"univpll_d7"
+};
+
+static const char * const img_parents[] = {
+	"clk26m",
+	"imgpll_ck",
+	"univpll_d4",
+	"mainpll_d4",
+	"univpll_d5",
+	"mmpll_d6",
+	"univpll_d6",
+	"mainpll_d6",
+	"mmpll_d4_d2",
+	"univpll_d4_d2",
+	"mainpll_d4_d2",
+	"univpll_d5_d2"
+};
+
+static const char * const camtm_parents[] = {
+	"clk26m",
+	"univpll_d4_d4",
+	"univpll_d6_d2",
+	"univpll_d6_d4"
+};
+
+static const char * const dsp_parents[] = {
+	"clk26m",
+	"univpll_d6_d2",
+	"univpll_d4_d2",
+	"univpll_d5",
+	"univpll_d4",
+	"mmpll_d4",
+	"mainpll_d3",
+	"univpll_d3"
+};
+
+static const char * const dsp1_parents[] = {
+	"clk26m",
+	"univpll_d6_d2",
+	"mainpll_d4_d2",
+	"univpll_d5",
+	"mmpll_d5",
+	"univpll_d4",
+	"mainpll_d3",
+	"univpll_d3"
+};
+
+static const char * const dsp2_parents[] = {
+	"clk26m",
+	"univpll_d6_d2",
+	"mainpll_d4_d2",
+	"univpll_d5",
+	"mmpll_d5",
+	"univpll_d4",
+	"mainpll_d3",
+	"univpll_d3"
+};
+
+static const char * const dsp3_parents[] = {
+	"clk26m",
+	"univpll_d6_d2",
+	"mainpll_d4_d2",
+	"univpll_d5",
+	"mmpll_d5",
+	"univpll_d4",
+	"mainpll_d3",
+	"univpll_d3"
+};
+
+static const char * const dsp4_parents[] = {
+	"clk26m",
+	"univpll_d6_d2",
+	"univpll_d4_d2",
+	"mainpll_d4",
+	"univpll_d4",
+	"mmpll_d4",
+	"mainpll_d3",
+	"univpll_d3"
+};
+
+static const char * const dsp5_parents[] = {
+	"clk26m",
+	"univpll_d6_d2",
+	"univpll_d4_d2",
+	"mainpll_d4",
+	"univpll_d4",
+	"mmpll_d4",
+	"mainpll_d3",
+	"univpll_d3"
+};
+
+static const char * const dsp6_parents[] = {
+	"clk26m",
+	"univpll_d6_d2",
+	"univpll_d4_d2",
+	"mainpll_d4",
+	"univpll_d4",
+	"mmpll_d4",
+	"mainpll_d3",
+	"univpll_d3"
+};
+
+static const char * const dsp7_parents[] = {
+	"clk26m",
+	"univpll_d6_d2",
+	"univpll_d4_d2",
+	"univpll_d5",
+	"univpll_d4",
+	"mmpll_d4",
+	"mainpll_d3",
+	"univpll_d3"
+};
+
+static const char * const ipu_if_parents[] = {
+	"clk26m",
+	"univpll_d6_d2",
+	"univpll_d5_d2",
+	"mainpll_d4_d2",
+	"mainpll_d6",
+	"univpll_d5",
+	"univpll_d4",
+	"mmpll_d4"
+};
+
+static const char * const mfg_parents[] = {
+	"clk26m",
+	"mainpll_d5_d2",
+	"univpll_d6",
+	"univpll_d7"
+};
+
+static const char * const camtg_parents[] = {
+	"clk26m",
+	"univpll_192m_d8",
+	"univpll_d6_d8",
+	"univpll_192m_d4",
+	"univpll_d6_d16",
+	"clk26m_d2",
+	"univpll_192m_d16",
+	"univpll_192m_d32"
+};
+
+static const char * const camtg2_parents[] = {
+	"clk26m",
+	"univpll_192m_d8",
+	"univpll_d6_d8",
+	"univpll_192m_d4",
+	"univpll_d6_d16",
+	"clk26m_d2",
+	"univpll_192m_d16",
+	"univpll_192m_d32"
+};
+
+static const char * const camtg3_parents[] = {
+	"clk26m",
+	"univpll_192m_d8",
+	"univpll_d6_d8",
+	"univpll_192m_d4",
+	"univpll_d6_d16",
+	"clk26m_d2",
+	"univpll_192m_d16",
+	"univpll_192m_d32"
+};
+
+static const char * const camtg4_parents[] = {
+	"clk26m",
+	"univpll_192m_d8",
+	"univpll_d6_d8",
+	"univpll_192m_d4",
+	"univpll_d6_d16",
+	"clk26m_d2",
+	"univpll_192m_d16",
+	"univpll_192m_d32"
+};
+
+static const char * const camtg5_parents[] = {
+	"clk26m",
+	"univpll_192m_d8",
+	"univpll_d6_d8",
+	"univpll_192m_d4",
+	"univpll_d6_d16",
+	"clk26m_d2",
+	"univpll_192m_d16",
+	"univpll_192m_d32"
+};
+
+static const char * const uart_parents[] = {
+	"clk26m",
+	"univpll_d6_d8"
+};
+
+static const char * const spi_parents[] = {
+	"clk26m",
+	"mainpll_d5_d4",
+	"mainpll_d6_d4",
+	"msdcpll_d4",
+	"univpll_d6_d2",
+	"mainpll_d6_d2",
+	"mainpll_d4_d4",
+	"univpll_d5_d4"
+};
+
+static const char * const spis_parents[] = {
+	"clk26m",
+	"univpll_d6",
+	"mainpll_d6",
+	"univpll_d4_d2",
+	"univpll_d6_d2",
+	"univpll_d4_d4",
+	"univpll_d6_d4",
+	"mainpll_d7_d4"
+};
+
+static const char * const msdc50_0_h_parents[] = {
+	"clk26m",
+	"mainpll_d4_d2",
+	"mainpll_d6_d2"
+};
+
+static const char * const msdc50_0_parents[] = {
+	"clk26m",
+	"msdcpll_ck",
+	"msdcpll_d2",
+	"univpll_d4_d4",
+	"mainpll_d6_d2",
+	"univpll_d4_d2"
+};
+
+static const char * const msdc30_1_parents[] = {
+	"clk26m",
+	"univpll_d6_d2",
+	"mainpll_d6_d2",
+	"mainpll_d7_d2",
+	"msdcpll_d2"
+};
+
+static const char * const msdc30_2_parents[] = {
+	"clk26m",
+	"univpll_d6_d2",
+	"mainpll_d6_d2",
+	"mainpll_d7_d2",
+	"msdcpll_d2"
+};
+
+static const char * const intdir_parents[] = {
+	"clk26m",
+	"univpll_d6",
+	"mainpll_d4",
+	"univpll_d4"
+};
+
+static const char * const aud_intbus_parents[] = {
+	"clk26m",
+	"mainpll_d4_d4",
+	"mainpll_d7_d4"
+};
+
+static const char * const audio_h_parents[] = {
+	"clk26m",
+	"univpll_d7",
+	"apll1_ck",
+	"apll2_ck"
+};
+
+static const char * const pwrap_ulposc_parents[] = {
+	"ulposc_d10",
+	"clk26m",
+	"ulposc_d4",
+	"ulposc_d7",
+	"ulposc_d8",
+	"ulposc_d16",
+	"mainpll_d4_d8",
+	"univpll_d5_d8"
+};
+
+static const char * const atb_parents[] = {
+	"clk26m",
+	"mainpll_d4_d2",
+	"mainpll_d5_d2"
+};
+
+static const char * const pwrmcu_parents[] = {
+	"clk26m",
+	"mainpll_d7_d2",
+	"mainpll_d6_d2",
+	"mainpll_d5_d2",
+	"mainpll_d9",
+	"mainpll_d4_d2"
+};
+
+static const char * const dp_parents[] = {
+	"clk26m",
+	"tvdpll1_d2",
+	"tvdpll2_d2",
+	"tvdpll1_d4",
+	"tvdpll2_d4",
+	"tvdpll1_d8",
+	"tvdpll2_d8",
+	"tvdpll1_d16",
+	"tvdpll2_d16"
+};
+
+static const char * const edp_parents[] = {
+	"clk26m",
+	"tvdpll1_d2",
+	"tvdpll2_d2",
+	"tvdpll1_d4",
+	"tvdpll2_d4",
+	"tvdpll1_d8",
+	"tvdpll2_d8",
+	"tvdpll1_d16",
+	"tvdpll2_d16"
+};
+
+static const char * const dpi_parents[] = {
+	"clk26m",
+	"tvdpll1_d2",
+	"tvdpll2_d2",
+	"tvdpll1_d4",
+	"tvdpll2_d4",
+	"tvdpll1_d8",
+	"tvdpll2_d8",
+	"tvdpll1_d16",
+	"tvdpll2_d16"
+};
+
+static const char * const disp_pwm0_parents[] = {
+	"clk26m",
+	"univpll_d6_d4",
+	"ulposc_d2",
+	"ulposc_d4",
+	"ulposc_d16"
+};
+
+static const char * const disp_pwm1_parents[] = {
+	"clk26m",
+	"univpll_d6_d4",
+	"ulposc_d2",
+	"ulposc_d4",
+	"ulposc_d16"
+};
+
+static const char * const usb_parents[] = {
+	"clk26m",
+	"univpll_d5_d4",
+	"univpll_d6_d4",
+	"univpll_d5_d2"
+};
+
+static const char * const ssusb_xhci_parents[] = {
+	"clk26m",
+	"univpll_d5_d4",
+	"univpll_d6_d4",
+	"univpll_d5_d2"
+};
+
+static const char * const usb_1p_parents[] = {
+	"clk26m",
+	"univpll_d5_d4",
+	"univpll_d6_d4",
+	"univpll_d5_d2"
+};
+
+static const char * const ssusb_xhci_1p_parents[] = {
+	"clk26m",
+	"univpll_d5_d4",
+	"univpll_d6_d4",
+	"univpll_d5_d2"
+};
+
+static const char * const usb_2p_parents[] = {
+	"clk26m",
+	"univpll_d5_d4",
+	"univpll_d6_d4",
+	"univpll_d5_d2"
+};
+
+static const char * const ssusb_xhci_2p_parents[] = {
+	"clk26m",
+	"univpll_d5_d4",
+	"univpll_d6_d4",
+	"univpll_d5_d2"
+};
+
+static const char * const usb_3p_parents[] = {
+	"clk26m",
+	"univpll_d5_d4",
+	"univpll_d6_d4",
+	"univpll_d5_d2"
+};
+
+static const char * const ssusb_xhci_3p_parents[] = {
+	"clk26m",
+	"univpll_d5_d4",
+	"univpll_d6_d4",
+	"univpll_d5_d2"
+};
+
+static const char * const i2c_parents[] = {
+	"clk26m",
+	"mainpll_d4_d8",
+	"univpll_d5_d4"
+};
+
+static const char * const seninf_parents[] = {
+	"clk26m",
+	"univpll_d4_d4",
+	"univpll_d6_d2",
+	"univpll_d4_d2",
+	"univpll_d7",
+	"univpll_d6",
+	"mmpll_d6",
+	"univpll_d5"
+};
+
+static const char * const seninf1_parents[] = {
+	"clk26m",
+	"univpll_d4_d4",
+	"univpll_d6_d2",
+	"univpll_d4_d2",
+	"univpll_d7",
+	"univpll_d6",
+	"mmpll_d6",
+	"univpll_d5"
+};
+
+static const char * const seninf2_parents[] = {
+	"clk26m",
+	"univpll_d4_d4",
+	"univpll_d6_d2",
+	"univpll_d4_d2",
+	"univpll_d7",
+	"univpll_d6",
+	"mmpll_d6",
+	"univpll_d5"
+};
+
+static const char * const seninf3_parents[] = {
+	"clk26m",
+	"univpll_d4_d4",
+	"univpll_d6_d2",
+	"univpll_d4_d2",
+	"univpll_d7",
+	"univpll_d6",
+	"mmpll_d6",
+	"univpll_d5"
+};
+
+static const char * const gcpu_parents[] = {
+	"clk26m",
+	"mainpll_d6",
+	"univpll_d4_d2",
+	"mmpll_d5_d2",
+	"univpll_d5_d2"
+};
+
+static const char * const dxcc_parents[] = {
+	"clk26m",
+	"mainpll_d4_d2",
+	"mainpll_d4_d4",
+	"mainpll_d4_d8"
+};
+
+static const char * const dpmaif_parents[] = {
+	"clk26m",
+	"univpll_d4_d4",
+	"mainpll_d6",
+	"mainpll_d4_d2",
+	"univpll_d4_d2"
+};
+
+static const char * const aes_ufsfde_parents[] = {
+	"clk26m",
+	"mainpll_d4_d2",
+	"mainpll_d6",
+	"mainpll_d4_d4",
+	"univpll_d4_d2",
+	"univpll_d6"
+};
+
+static const char * const ufs_parents[] = {
+	"clk26m",
+	"mainpll_d4_d4",
+	"mainpll_d4_d8",
+	"univpll_d4_d4",
+	"mainpll_d6_d2",
+	"univpll_d6_d2",
+	"msdcpll_d2"
+};
+
+static const char * const ufs_tick1us_parents[] = {
+	"clk26m_d52",
+	"clk26m"
+};
+
+static const char * const ufs_mp_sap_parents[] = {
+	"clk26m",
+	"msdcpll_d16"
+};
+
+static const char * const venc_parents[] = {
+	"clk26m",
+	"mmpll_d4_d2",
+	"mainpll_d6",
+	"univpll_d4_d2",
+	"mainpll_d4_d2",
+	"univpll_d6",
+	"mmpll_d6",
+	"mainpll_d5_d2",
+	"mainpll_d6_d2",
+	"mmpll_d9",
+	"univpll_d4_d4",
+	"mainpll_d4",
+	"univpll_d4",
+	"univpll_d5",
+	"univpll_d5_d2",
+	"mainpll_d5"
+};
+
+static const char * const vdec_parents[] = {
+	"clk26m",
+	"mainpll_d5_d2",
+	"mmpll_d6_d2",
+	"univpll_d4_d2",
+	"mmpll_d4_d2",
+	"mainpll_d5",
+	"mmpll_d6",
+	"mmpll_d5",
+	"vdecpll_ck",
+	"univpll_d4",
+	"mmpll_d4",
+	"univpll_d6_d2",
+	"mmpll_d9",
+	"univpll_d6",
+	"univpll_d5",
+	"mainpll_d4"
+};
+
+static const char * const pwm_parents[] = {
+	"clk26m",
+	"univpll_d4_d8"
+};
+
+static const char * const spmi_p_mst_parents[] = {
+	"clk26m",
+	"clk26m_d2",
+	"ulposc_d8",
+	"ulposc_d10",
+	"ulposc_d16",
+	"ulposc_d7",
+	"clk32k",
+	"mainpll_d7_d8",
+	"mainpll_d6_d8",
+	"mainpll_d5_d8"
+};
+
+static const char * const spmi_m_mst_parents[] = {
+	"clk26m",
+	"clk26m_d2",
+	"ulposc_d8",
+	"ulposc_d10",
+	"ulposc_d16",
+	"ulposc_d7",
+	"clk32k",
+	"mainpll_d7_d8",
+	"mainpll_d6_d8",
+	"mainpll_d5_d8"
+};
+
+static const char * const tl_parents[] = {
+	"clk26m",
+	"univpll_d5_d4",
+	"mainpll_d4_d4"
+};
+
+static const char * const tl_p1_parents[] = {
+	"clk26m",
+	"univpll_d5_d4",
+	"mainpll_d4_d4"
+};
+
+static const char * const aes_msdcfde_parents[] = {
+	"clk26m",
+	"mainpll_d4_d2",
+	"mainpll_d6",
+	"mainpll_d4_d4",
+	"univpll_d4_d2",
+	"univpll_d6"
+};
+
+static const char * const dsi_occ_parents[] = {
+	"clk26m",
+	"mainpll_d6_d2",
+	"univpll_d5_d2",
+	"univpll_d4_d2"
+};
+
+static const char * const wpe_vpp_parents[] = {
+	"clk26m",
+	"mainpll_d5_d2",
+	"mmpll_d6_d2",
+	"univpll_d5_d2",
+	"mainpll_d4_d2",
+	"univpll_d4_d2",
+	"mmpll_d4_d2",
+	"mainpll_d6",
+	"mmpll_d7",
+	"univpll_d6",
+	"mainpll_d5",
+	"univpll_d5",
+	"mainpll_d4",
+	"tvdpll1_ck",
+	"univpll_d4"
+};
+
+static const char * const hdcp_parents[] = {
+	"clk26m",
+	"univpll_d4_d8",
+	"mainpll_d5_d8",
+	"univpll_d6_d4"
+};
+
+static const char * const hdcp_24m_parents[] = {
+	"clk26m",
+	"univpll_192m_d4",
+	"univpll_192m_d8",
+	"univpll_d6_d8"
+};
+
+static const char * const hd20_dacr_ref_parents[] = {
+	"clk26m",
+	"univpll_d4_d2",
+	"univpll_d4_d4",
+	"univpll_d4_d8"
+};
+
+static const char * const hd20_hdcp_c_parents[] = {
+	"clk26m",
+	"msdcpll_d4",
+	"univpll_d4_d8",
+	"univpll_d6_d8"
+};
+
+static const char * const hdmi_xtal_parents[] = {
+	"clk26m",
+	"clk26m_d2"
+};
+
+static const char * const hdmi_apb_parents[] = {
+	"clk26m",
+	"univpll_d6_d4",
+	"msdcpll_d2"
+};
+
+static const char * const snps_eth_250m_parents[] = {
+	"clk26m",
+	"ethpll_d2"
+};
+
+static const char * const snps_eth_62p4m_ptp_parents[] = {
+	"apll2_d3",
+	"apll1_d3",
+	"clk26m",
+	"ethpll_d8"
+};
+
+static const char * const snps_eth_50m_rmii_parents[] = {
+	"clk26m",
+	"ethpll_d10"
+};
+
+static const char * const dgi_out_parents[] = {
+	"clk26m",
+	"dgipll_ck",
+	"dgipll_d2",
+	"in_dgi",
+	"in_dgi_d2",
+	"mmpll_d4_d4"
+};
+
+static const char * const nna0_parents[] = {
+	"clk26m",
+	"nnapll_ck",
+	"univpll_d4",
+	"mainpll_d4",
+	"univpll_d5",
+	"mmpll_d6",
+	"univpll_d6",
+	"mainpll_d6",
+	"mmpll_d4_d2",
+	"univpll_d4_d2",
+	"mainpll_d4_d2",
+	"mmpll_d6_d2"
+};
+
+static const char * const nna1_parents[] = {
+	"clk26m",
+	"nnapll_ck",
+	"univpll_d4",
+	"mainpll_d4",
+	"univpll_d5",
+	"mmpll_d6",
+	"univpll_d6",
+	"mainpll_d6",
+	"mmpll_d4_d2",
+	"univpll_d4_d2",
+	"mainpll_d4_d2",
+	"mmpll_d6_d2"
+};
+
+static const char * const adsp_parents[] = {
+	"clk26m",
+	"clk26m_d2",
+	"mainpll_d6",
+	"mainpll_d5_d2",
+	"univpll_d4_d4",
+	"univpll_d4",
+	"univpll_d6",
+	"ulposc",
+	"adsppll_ck",
+	"adsppll_d2",
+	"adsppll_d4",
+	"adsppll_d8"
+};
+
+static const char * const asm_h_parents[] = {
+	"clk26m",
+	"univpll_d6_d4",
+	"univpll_d6_d2",
+	"mainpll_d5_d2"
+};
+
+static const char * const asm_m_parents[] = {
+	"clk26m",
+	"univpll_d6_d4",
+	"univpll_d6_d2",
+	"mainpll_d5_d2"
+};
+
+static const char * const asm_l_parents[] = {
+	"clk26m",
+	"univpll_d6_d4",
+	"univpll_d6_d2",
+	"mainpll_d5_d2"
+};
+
+static const char * const apll1_parents[] = {
+	"clk26m",
+	"apll1_d4"
+};
+
+static const char * const apll2_parents[] = {
+	"clk26m",
+	"apll2_d4"
+};
+
+static const char * const apll3_parents[] = {
+	"clk26m",
+	"apll3_d4"
+};
+
+static const char * const apll4_parents[] = {
+	"clk26m",
+	"apll4_d4"
+};
+
+static const char * const apll5_parents[] = {
+	"clk26m",
+	"apll5_d4"
+};
+
+static const char * const i2so1_m_parents[] = {
+	"clk26m",
+	"apll1_ck",
+	"apll2_ck",
+	"apll3_ck",
+	"apll4_ck",
+	"apll5_ck",
+	"hdmirx_apll_ck"
+};
+
+static const char * const i2so2_m_parents[] = {
+	"clk26m",
+	"apll1_ck",
+	"apll2_ck",
+	"apll3_ck",
+	"apll4_ck",
+	"apll5_ck",
+	"hdmirx_apll_ck"
+};
+
+static const char * const i2si1_m_parents[] = {
+	"clk26m",
+	"apll1_ck",
+	"apll2_ck",
+	"apll3_ck",
+	"apll4_ck",
+	"apll5_ck",
+	"hdmirx_apll_ck"
+};
+
+static const char * const i2si2_m_parents[] = {
+	"clk26m",
+	"apll1_ck",
+	"apll2_ck",
+	"apll3_ck",
+	"apll4_ck",
+	"apll5_ck",
+	"hdmirx_apll_ck"
+};
+
+static const char * const dptx_m_parents[] = {
+	"clk26m",
+	"apll1_ck",
+	"apll2_ck",
+	"apll3_ck",
+	"apll4_ck",
+	"apll5_ck",
+	"hdmirx_apll_ck"
+};
+
+static const char * const aud_iec_parents[] = {
+	"clk26m",
+	"apll1_ck",
+	"apll2_ck",
+	"apll3_ck",
+	"apll4_ck",
+	"apll5_ck",
+	"hdmirx_apll_ck"
+};
+
+static const char * const a1sys_hp_parents[] = {
+	"clk26m",
+	"apll1_d4"
+};
+
+static const char * const a2sys_parents[] = {
+	"clk26m",
+	"apll2_d4"
+};
+
+static const char * const a3sys_parents[] = {
+	"clk26m",
+	"apll3_d4",
+	"apll4_d4",
+	"apll5_d4",
+	"hdmirx_apll_d3",
+	"hdmirx_apll_d4",
+	"hdmirx_apll_d6"
+};
+
+static const char * const a4sys_parents[] = {
+	"clk26m",
+	"apll3_d4",
+	"apll4_d4",
+	"apll5_d4",
+	"hdmirx_apll_d3",
+	"hdmirx_apll_d4",
+	"hdmirx_apll_d6"
+};
+
+static const char * const spinfi_b_parents[] = {
+	"clk26m",
+	"univpll_d6_d8",
+	"univpll_d5_d8",
+	"mainpll_d4_d8",
+	"mainpll_d7_d4",
+	"mainpll_d6_d4",
+	"univpll_d6_d4",
+	"univpll_d5_d4"
+};
+
+static const char * const nfi1x_parents[] = {
+	"clk26m",
+	"univpll_d5_d4",
+	"mainpll_d7_d4",
+	"mainpll_d6_d4",
+	"univpll_d6_d4",
+	"mainpll_d4_d4",
+	"mainpll_d7_d2",
+	"mainpll_d6_d2"
+};
+
+static const char * const ecc_parents[] = {
+	"clk26m",
+	"mainpll_d4_d4",
+	"mainpll_d5_d2",
+	"mainpll_d4_d2",
+	"mainpll_d6",
+	"univpll_d6"
+};
+
+static const char * const audio_local_bus_parents[] = {
+	"clk26m",
+	"clk26m_d2",
+	"mainpll_d4_d4",
+	"mainpll_d7_d2",
+	"mainpll_d4_d2",
+	"mainpll_d5_d2",
+	"mainpll_d6_d2",
+	"mainpll_d7",
+	"univpll_d6",
+	"ulposc",
+	"ulposc_d4",
+	"ulposc_d2"
+};
+
+static const char * const spinor_parents[] = {
+	"clk26m",
+	"clk26m_d2",
+	"mainpll_d7_d8",
+	"univpll_d6_d8"
+};
+
+static const char * const dvio_dgi_ref_parents[] = {
+	"clk26m",
+	"in_dgi",
+	"in_dgi_d2",
+	"in_dgi_d4",
+	"in_dgi_d6",
+	"in_dgi_d8",
+	"mmpll_d4_d4"
+};
+
+static const char * const srck_parents[] = {
+	"ulposc_d10",
+	"clk26m"
+};
+
+static const char * const rsvd1_parents[] = {
+	"clk26m",
+	"mainpll_d4_d4",
+	"mainpll_d5_d4",
+	"mainpll_d6_d4",
+	"mainpll_d7_d4",
+	"univpll_d6_d4",
+	"ulposc",
+	"ulposc2"
+};
+
+static const char * const mfg_fast_parents[] = {
+	"mfg_sel",
+	"mfgpll_opp"
+};
+
+static const struct mtk_mux top_mtk_muxes[] = {
+	/* CLK_CFG_0 */
+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel",
+		axi_parents, 0x020, 0x024, 0x028, 0, 3, 7, 0x04, 0, CLK_IS_CRITICAL),
+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel",
+		spm_parents, 0x020, 0x024, 0x028, 8, 2, 15, 0x04, 1, CLK_IS_CRITICAL),
+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM_SEL, "bus_aximem_sel",
+		bus_aximem_parents, 0x020, 0x024, 0x028, 24, 3, 31, 0x04, 3, CLK_IS_CRITICAL),
+	/* CLK_CFG_1 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP_SEL, "vpp_sel",
+		vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR_SEL, "ethdr_sel",
+		ethdr_parents, 0x02C, 0x030, 0x034, 8, 4, 15, 0x04, 5),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel",
+		ipe_parents, 0x02C, 0x030, 0x034, 16, 4, 23, 0x04, 6),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel",
+		cam_parents, 0x02C, 0x030, 0x034, 24, 4, 31, 0x04, 7),
+	/* CLK_CFG_2 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel",
+		ccu_parents, 0x038, 0x03C, 0x040, 0, 4, 7, 0x04, 8),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG_SEL, "img_sel",
+		img_parents, 0x038, 0x03C, 0x040, 8, 4, 15, 0x04, 9),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel",
+		camtm_parents, 0x038, 0x03C, 0x040, 16, 2, 23, 0x04, 10),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel",
+		dsp_parents, 0x038, 0x03C, 0x040, 24, 3, 31, 0x04, 11),
+	/* CLK_CFG_3 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1_SEL, "dsp1_sel",
+		dsp1_parents, 0x044, 0x048, 0x04C, 0, 3, 7, 0x04, 12),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2_SEL, "dsp2_sel",
+		dsp2_parents, 0x044, 0x048, 0x04C, 8, 3, 15, 0x04, 13),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3_SEL, "dsp3_sel",
+		dsp3_parents, 0x044, 0x048, 0x04C, 16, 3, 23, 0x04, 14),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP4_SEL, "dsp4_sel",
+		dsp4_parents, 0x044, 0x048, 0x04C, 24, 3, 31, 0x04, 15),
+	/* CLK_CFG_4 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5_SEL, "dsp5_sel",
+		dsp5_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x04, 16),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP6_SEL, "dsp6_sel",
+		dsp6_parents, 0x050, 0x054, 0x058, 8, 3, 15, 0x04, 17),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel",
+		dsp7_parents, 0x050, 0x054, 0x058, 16, 3, 23, 0x04, 18),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF_SEL, "ipu_if_sel",
+		ipu_if_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x04, 19),
+	/* CLK_CFG_5 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel",
+		mfg_parents, 0x05C, 0x060, 0x064, 0, 2, 7, 0x04, 20),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
+		camtg_parents, 0x05C, 0x060, 0x064, 8, 3, 15, 0x04, 21),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
+		camtg2_parents, 0x05C, 0x060, 0x064, 16, 3, 23, 0x04, 22),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel",
+		camtg3_parents, 0x05C, 0x060, 0x064, 24, 3, 31, 0x04, 23),
+	/* CLK_CFG_6 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4_SEL, "camtg4_sel",
+		camtg4_parents, 0x068, 0x06C, 0x070, 0, 3, 7, 0x04, 24),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5_SEL, "camtg5_sel",
+		camtg5_parents, 0x068, 0x06C, 0x070, 8, 3, 15, 0x04, 25),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel",
+		uart_parents, 0x068, 0x06C, 0x070, 16, 1, 23, 0x04, 26),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel",
+		spi_parents, 0x068, 0x06C, 0x070, 24, 3, 31, 0x04, 27),
+	/* CLK_CFG_7 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIS_SEL, "spis_sel",
+		spis_parents, 0x074, 0x078, 0x07C, 0, 3, 7, 0x04, 28),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel",
+		msdc50_0_h_parents, 0x074, 0x078, 0x07C, 8, 2, 15, 0x04, 29),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
+		msdc50_0_parents, 0x074, 0x078, 0x07C, 16, 3, 23, 0x04, 30),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
+		msdc30_1_parents, 0x074, 0x078, 0x07C, 24, 3, 31, 0x04, 31),
+	/* CLK_CFG_8 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
+		msdc30_2_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x08, 0),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR_SEL, "intdir_sel",
+		intdir_parents, 0x080, 0x084, 0x088, 8, 2, 15, 0x08, 1),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
+		aud_intbus_parents, 0x080, 0x084, 0x088, 16, 2, 23, 0x08, 2),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, "audio_h_sel",
+		audio_h_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x08, 3),
+	/* CLK_CFG_9 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL, "pwrap_ulposc_sel",
+		pwrap_ulposc_parents, 0x08C, 0x090, 0x094, 0, 3, 7, 0x08, 4),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel",
+		atb_parents, 0x08C, 0x090, 0x094, 8, 2, 15, 0x08, 5),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRMCU_SEL, "pwrmcu_sel",
+		pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DP_SEL, "dp_sel",
+		dp_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7),
+	/* CLK_CFG_10 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP_SEL, "edp_sel",
+		edp_parents, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI_SEL, "dpi_sel",
+		dpi_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0_SEL, "disp_pwm0_sel",
+		disp_pwm0_parents, 0x098, 0x09C, 0x0A0, 16, 3, 23, 0x08, 10),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM1_SEL, "disp_pwm1_sel",
+		disp_pwm1_parents, 0x098, 0x09C, 0x0A0, 24, 3, 31, 0x08, 11),
+	/* CLK_CFG_11 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SEL, "usb_sel",
+		usb_parents, 0x0A4, 0x0A8, 0x0AC, 0, 2, 7, 0x08, 12),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel",
+		ssusb_xhci_parents, 0x0A4, 0x0A8, 0x0AC, 8, 2, 15, 0x08, 13),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_1P_SEL, "usb_1p_sel",
+		usb_1p_parents, 0x0A4, 0x0A8, 0x0AC, 16, 2, 23, 0x08, 14),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_1P_SEL, "ssusb_xhci_1p_sel",
+		ssusb_xhci_1p_parents, 0x0A4, 0x0A8, 0x0AC, 24, 2, 31, 0x08, 15),
+	/* CLK_CFG_12 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_2P_SEL, "usb_2p_sel",
+		usb_2p_parents, 0x0B0, 0x0B4, 0x0B8, 0, 2, 7, 0x08, 16),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P_SEL, "ssusb_xhci_2p_sel",
+		ssusb_xhci_2p_parents, 0x0B0, 0x0B4, 0x0B8, 8, 2, 15, 0x08, 17),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_3P_SEL, "usb_3p_sel",
+		usb_3p_parents, 0x0B0, 0x0B4, 0x0B8, 16, 2, 23, 0x08, 18),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P_SEL, "ssusb_xhci_3p_sel",
+		ssusb_xhci_3p_parents, 0x0B0, 0x0B4, 0x0B8, 24, 2, 31, 0x08, 19),
+	/* CLK_CFG_13 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel",
+		i2c_parents, 0x0BC, 0x0C0, 0x0C4, 0, 2, 7, 0x08, 20),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel",
+		seninf_parents, 0x0BC, 0x0C0, 0x0C4, 8, 3, 15, 0x08, 21),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, "seninf1_sel",
+		seninf1_parents, 0x0BC, 0x0C0, 0x0C4, 16, 3, 23, 0x08, 22),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2_SEL, "seninf2_sel",
+		seninf2_parents, 0x0BC, 0x0C0, 0x0C4, 24, 3, 31, 0x08, 23),
+	/* CLK_CFG_14 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3_SEL, "seninf3_sel",
+		seninf3_parents, 0x0C8, 0x0CC, 0x0D0, 0, 3, 7, 0x08, 24),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, "gcpu_sel",
+		gcpu_parents, 0x0C8, 0x0CC, 0x0D0, 8, 3, 15, 0x08, 25),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel",
+		dxcc_parents, 0x0C8, 0x0CC, 0x0D0, 16, 2, 23, 0x08, 26),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_SEL, "dpmaif_sel",
+		dpmaif_parents, 0x0C8, 0x0CC, 0x0D0, 24, 3, 31, 0x08, 27),
+	/* CLK_CFG_15 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, "aes_ufsfde_sel",
+		aes_ufsfde_parents, 0x0D4, 0x0D8, 0x0DC, 0, 3, 7, 0x08, 28),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_SEL, "ufs_sel",
+		ufs_parents, 0x0D4, 0x0D8, 0x0DC, 8, 3, 15, 0x08, 29),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_TICK1US_SEL, "ufs_tick1us_sel",
+		ufs_tick1us_parents, 0x0D4, 0x0D8, 0x0DC, 16, 1, 23, 0x08, 30),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_MP_SAP_SEL, "ufs_mp_sap_sel",
+		ufs_mp_sap_parents, 0x0D4, 0x0D8, 0x0DC, 24, 1, 31, 0x08, 31),
+	/* CLK_CFG_16 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel",
+		venc_parents, 0x0E0, 0x0E4, 0x0E8, 0, 4, 7, 0x0C, 0),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel",
+		vdec_parents, 0x0E0, 0x0E4, 0x0E8, 8, 4, 15, 0x0C, 1),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel",
+		pwm_parents, 0x0E0, 0x0E4, 0x0E8, 16, 1, 23, 0x0C, 2),
+	/* CLK_CFG_17 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST_SEL, "spmi_p_mst_sel",
+		spmi_p_mst_parents, 0x0EC, 0x0F0, 0x0F4, 0, 4, 7, 0x0C, 4),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST_SEL, "spmi_m_mst_sel",
+		spmi_m_mst_parents, 0x0EC, 0x0F0, 0x0F4, 8, 4, 15, 0x0C, 5),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_SEL, "tl_sel",
+		tl_parents, 0x0EC, 0x0F0, 0x0F4, 24, 2, 31, 0x0C, 7),
+	/* CLK_CFG_18 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_P1_SEL, "tl_p1_sel",
+		tl_p1_parents, 0x0F8, 0x0FC, 0x0100, 0, 2, 7, 0x0C, 8),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel",
+		aes_msdcfde_parents, 0x0F8, 0x0FC, 0x0100, 8, 3, 15, 0x0C, 9),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC_SEL, "dsi_occ_sel",
+		dsi_occ_parents, 0x0F8, 0x0FC, 0x0100, 16, 2, 23, 0x0C, 10),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE_VPP_SEL, "wpe_vpp_sel",
+		wpe_vpp_parents, 0x0F8, 0x0FC, 0x0100, 24, 4, 31, 0x0C, 11),
+	/* CLK_CFG_19 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_SEL, "hdcp_sel",
+		hdcp_parents, 0x0104, 0x0108, 0x010C, 0, 2, 7, 0x0C, 12),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel",
+		hdcp_24m_parents, 0x0104, 0x0108, 0x010C, 8, 2, 15, 0x0C, 13),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_HD20_DACR_REF_SEL, "hd20_dacr_ref_sel",
+		hd20_dacr_ref_parents, 0x0104, 0x0108, 0x010C, 16, 2, 23, 0x0C, 14),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_HD20_HDCP_C_SEL, "hd20_hdcp_c_sel",
+		hd20_hdcp_c_parents, 0x0104, 0x0108, 0x010C, 24, 2, 31, 0x0C, 15),
+	/* CLK_CFG_20 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_XTAL_SEL, "hdmi_xtal_sel",
+		hdmi_xtal_parents, 0x0110, 0x0114, 0x0118, 0, 1, 7, 0x0C, 16),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_APB_SEL, "hdmi_apb_sel",
+		hdmi_apb_parents, 0x0110, 0x0114, 0x0118, 8, 2, 15, 0x0C, 17),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M_SEL, "snps_eth_250m_sel",
+		snps_eth_250m_parents, 0x0110, 0x0114, 0x0118, 16, 1, 23, 0x0C, 18),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP_SEL, "snps_eth_62p4m_ptp_sel",
+		snps_eth_62p4m_ptp_parents, 0x0110, 0x0114, 0x0118, 24, 2, 31, 0x0C, 19),
+	/* CLK_CFG_21 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII_SEL, "snps_eth_50m_rmii_sel",
+		snps_eth_50m_rmii_parents, 0x011C, 0x0120, 0x0124, 0, 1, 7, 0x0C, 20),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DGI_OUT_SEL, "dgi_out_sel",
+		dgi_out_parents, 0x011C, 0x0120, 0x0124, 8, 3, 15, 0x0C, 21),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA0_SEL, "nna0_sel",
+		nna0_parents, 0x011C, 0x0120, 0x0124, 16, 4, 23, 0x0C, 22),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA1_SEL, "nna1_sel",
+		nna1_parents, 0x011C, 0x0120, 0x0124, 24, 4, 31, 0x0C, 23),
+	/* CLK_CFG_22 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_SEL, "adsp_sel",
+		adsp_parents, 0x0128, 0x012C, 0x0130, 0, 4, 7, 0x0C, 24),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_H_SEL, "asm_h_sel",
+		asm_h_parents, 0x0128, 0x012C, 0x0130, 8, 2, 15, 0x0C, 25),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_M_SEL, "asm_m_sel",
+		asm_m_parents, 0x0128, 0x012C, 0x0130, 16, 2, 23, 0x0C, 26),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_L_SEL, "asm_l_sel",
+		asm_l_parents, 0x0128, 0x012C, 0x0130, 24, 2, 31, 0x0C, 27),
+	/* CLK_CFG_23 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1_SEL, "apll1_sel",
+		apll1_parents, 0x0134, 0x0138, 0x013C, 0, 1, 7, 0x0C, 28),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2_SEL, "apll2_sel",
+		apll2_parents, 0x0134, 0x0138, 0x013C, 8, 1, 15, 0x0C, 29),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL3_SEL, "apll3_sel",
+		apll3_parents, 0x0134, 0x0138, 0x013C, 16, 1, 23, 0x0C, 30),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL4_SEL, "apll4_sel",
+		apll4_parents, 0x0134, 0x0138, 0x013C, 24, 1, 31, 0x0C, 31),
+	/* CLK_CFG_24 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5_SEL, "apll5_sel",
+		apll5_parents, 0x0140, 0x0144, 0x0148, 0, 1, 7, 0x010, 0),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1_M_SEL, "i2so1_m_sel",
+		i2so1_m_parents, 0x0140, 0x0144, 0x0148, 8, 3, 15, 0x010, 1),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2_M_SEL, "i2so2_m_sel",
+		i2so2_m_parents, 0x0140, 0x0144, 0x0148, 16, 3, 23, 0x010, 2),
+	/* CLK_CFG_25 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1_M_SEL, "i2si1_m_sel",
+		i2si1_m_parents, 0x014C, 0x0150, 0x0154, 8, 3, 15, 0x010, 5),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2_M_SEL, "i2si2_m_sel",
+		i2si2_m_parents, 0x014C, 0x0150, 0x0154, 16, 3, 23, 0x010, 6),
+	/* CLK_CFG_26 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX_M_SEL, "dptx_m_sel",
+		dptx_m_parents, 0x0158, 0x015C, 0x0160, 8, 3, 15, 0x010, 9),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC_SEL, "aud_iec_sel",
+		aud_iec_parents, 0x0158, 0x015C, 0x0160, 16, 3, 23, 0x010, 10),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel",
+		a1sys_hp_parents, 0x0158, 0x015C, 0x0160, 24, 1, 31, 0x010, 11),
+	/* CLK_CFG_27 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS_SEL, "a2sys_sel",
+		a2sys_parents, 0x0164, 0x0168, 0x016C, 0, 1, 7, 0x010, 12),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS_SEL, "a3sys_sel",
+		a3sys_parents, 0x0164, 0x0168, 0x016C, 8, 3, 15, 0x010, 13),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS_SEL, "a4sys_sel",
+		a4sys_parents, 0x0164, 0x0168, 0x016C, 16, 3, 23, 0x010, 14),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_B_SEL, "spinfi_b_sel",
+		spinfi_b_parents, 0x0164, 0x0168, 0x016C, 24, 3, 31, 0x010, 15),
+	/* CLK_CFG_28 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel",
+		nfi1x_parents, 0x0170, 0x0174, 0x0178, 0, 3, 7, 0x010, 16),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, "ecc_sel",
+		ecc_parents, 0x0170, 0x0174, 0x0178, 8, 3, 15, 0x010, 17),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS_SEL, "audio_local_bus_sel",
+		audio_local_bus_parents, 0x0170, 0x0174, 0x0178, 16, 4, 23, 0x010, 18),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR_SEL, "spinor_sel",
+		spinor_parents, 0x0170, 0x0174, 0x0178, 24, 2, 31, 0x010, 19),
+	/* CLK_CFG_29 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DVIO_DGI_REF_SEL, "dvio_dgi_ref_sel",
+		dvio_dgi_ref_parents, 0x017C, 0x0180, 0x0184, 0, 3, 7, 0x010, 20),
+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK_SEL, "srck_sel",
+		srck_parents, 0x017C, 0x0180, 0x0184, 24, 1, 31, 0x010, 23, CLK_IS_CRITICAL),
+	/* CLK_CFG_37 */
+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_RSVD1_SEL, "rsvd1_sel",
+		rsvd1_parents, 0x01DC, 0x01E0, 0x01E4, 0, 3, 7, 0x014, 20, CLK_IS_CRITICAL),
+};
+
+static struct mtk_composite top_muxes[] = {
+	/* CLK_MISC_CFG_3 */
+	MUX(CLK_TOP_MFG_FAST_SEL, "mfg_fast_sel", mfg_fast_parents, 0x0250, 8, 1),
+};
+
+static const struct mtk_composite top_adj_divs[] = {
+	DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2si1_m_sel", 0x0320, 0, 0x0328, 8, 0),
+	DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2si2_m_sel", 0x0320, 1, 0x0328, 8, 8),
+	DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "i2so1_m_sel", 0x0320, 2, 0x0328, 8, 16),
+	DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "i2so2_m_sel", 0x0320, 3, 0x0328, 8, 24),
+	DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "aud_iec_sel", 0x0320, 4, 0x0334, 8, 0),
+	DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "dptx_m_sel", 0x0320, 9, 0x0338, 8, 8),
+};
+
+static const struct mtk_gate_regs infra_ao0_cg_regs = {
+	.set_ofs = 0x80,
+	.clr_ofs = 0x84,
+	.sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs infra_ao1_cg_regs = {
+	.set_ofs = 0x88,
+	.clr_ofs = 0x8c,
+	.sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs infra_ao2_cg_regs = {
+	.set_ofs = 0xa4,
+	.clr_ofs = 0xa8,
+	.sta_ofs = 0xac,
+};
+
+static const struct mtk_gate_regs infra_ao3_cg_regs = {
+	.set_ofs = 0xc0,
+	.clr_ofs = 0xc4,
+	.sta_ofs = 0xc8,
+};
+
+static const struct mtk_gate_regs infra_ao4_cg_regs = {
+	.set_ofs = 0xe0,
+	.clr_ofs = 0xe4,
+	.sta_ofs = 0xe8,
+};
+
+#define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag)                \
+	GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
+		&mtk_clk_gate_ops_setclr, _flag)
+
+#define GATE_INFRA_AO0(_id, _name, _parent, _shift)	\
+	GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag)		\
+	GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift,	\
+		&mtk_clk_gate_ops_setclr, _flag)
+
+#define GATE_INFRA_AO1(_id, _name, _parent, _shift)	\
+	GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_INFRA_AO2(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag)		\
+	GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift,	\
+		&mtk_clk_gate_ops_setclr, _flag)
+
+#define GATE_INFRA_AO3(_id, _name, _parent, _shift)	\
+	GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag)		\
+	GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao4_cg_regs, _shift,	\
+		&mtk_clk_gate_ops_setclr, _flag)
+
+#define GATE_INFRA_AO4(_id, _name, _parent, _shift)	\
+	GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, 0)
+
+static const struct mtk_gate infra_ao_clks[] = {
+	/* INFRA_AO0 */
+	GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, "infra_ao_pmic_tmr", "pwrap_ulposc_sel", 0),
+	GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, "infra_ao_pmic_ap", "pwrap_ulposc_sel", 1),
+	GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, "infra_ao_pmic_md", "pwrap_ulposc_sel", 2),
+	GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, "infra_ao_pmic_conn", "pwrap_ulposc_sel", 3),
+	GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ, "infra_ao_sej", "axi_sel", 5, CLK_IS_CRITICAL),
+	GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, "infra_ao_apxgpt", "axi_sel", 6),
+	GATE_INFRA_AO0(CLK_INFRA_AO_GCE, "infra_ao_gce", "axi_sel", 8),
+	GATE_INFRA_AO0(CLK_INFRA_AO_GCE2, "infra_ao_gce2", "axi_sel", 9),
+	GATE_INFRA_AO0(CLK_INFRA_AO_THERM, "infra_ao_therm", "axi_sel", 10),
+	GATE_INFRA_AO0(CLK_INFRA_AO_PWM_H, "infra_ao_pwm_h", "axi_sel", 15),
+	GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, "infra_ao_pwm1", "pwm_sel", 16),
+	GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, "infra_ao_pwm2", "pwm_sel", 17),
+	GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, "infra_ao_pwm3", "pwm_sel", 18),
+	GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, "infra_ao_pwm4", "pwm_sel", 19),
+	GATE_INFRA_AO0(CLK_INFRA_AO_PWM, "infra_ao_pwm", "pwm_sel", 21),
+	GATE_INFRA_AO0(CLK_INFRA_AO_UART0, "infra_ao_uart0", "uart_sel", 22),
+	GATE_INFRA_AO0(CLK_INFRA_AO_UART1, "infra_ao_uart1", "uart_sel", 23),
+	GATE_INFRA_AO0(CLK_INFRA_AO_UART2, "infra_ao_uart2", "uart_sel", 24),
+	GATE_INFRA_AO0(CLK_INFRA_AO_UART3, "infra_ao_uart3", "uart_sel", 25),
+	GATE_INFRA_AO0(CLK_INFRA_AO_UART4, "infra_ao_uart4", "uart_sel", 26),
+	GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, "infra_ao_gce_26m", "clk26m", 27),
+	GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_cq_dma_fpc", "fpc", 28),
+	GATE_INFRA_AO0(CLK_INFRA_AO_UART5, "infra_ao_uart5", "uart_sel", 29),
+	/* INFRA_AO1 */
+	GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "clk26m", 0),
+	GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 1),
+	GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "msdc50_0_h_sel", 2),
+	GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "axi_sel", 4),
+	GATE_INFRA_AO1(CLK_INFRA_AO_CG1_MSDC2, "infra_ao_cg1_msdc2", "axi_sel", 5),
+	GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, "infra_ao_msdc0_src", "msdc50_0_sel", 6),
+	GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, "infra_ao_trng", "axi_sel", 9),
+	GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, "infra_ao_auxadc", "clk26m", 10),
+	GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, "infra_ao_cpum", "axi_sel", 11),
+	GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_32K, "infra_ao_hdmi_32k", "clk32k", 12),
+	GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_H, "infra_ao_cec_66m_h", "axi_sel", 13),
+	GATE_INFRA_AO1(CLK_INFRA_AO_IRRX, "infra_ao_irrx", "axi_sel", 14),
+	GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_26M, "infra_ao_pcie_tl_26m", "clk26m", 15),
+	GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, "infra_ao_msdc1_src", "msdc30_1_sel", 16),
+	GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_B, "infra_ao_cec_66m_b", "axi_sel", 17),
+	GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, "infra_ao_pcie_tl_96m", "tl_sel", 18),
+	GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DEVICE_APC, "infra_ao_device_apc", "axi_sel", 20,
+		CLK_IS_CRITICAL),
+	GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_H, "infra_ao_ecc_66m_h", "axi_sel", 23),
+	GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, "infra_ao_debugsys", "axi_sel", 24),
+	GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, "infra_ao_audio", "axi_sel", 25),
+	GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_32K, "infra_ao_pcie_tl_32k", "clk32k", 26),
+	GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, "infra_ao_dbg_trace", "axi_sel", 29),
+	GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, "infra_ao_dramc_f26m", "clk26m", 31),
+	/* INFRA_AO2 */
+	GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, "infra_ao_irtx", "axi_sel", 0),
+	GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB, "infra_ao_ssusb", "usb_sel", 1),
+	GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, "infra_ao_disp_pwm", "disp_pwm0_sel", 2),
+	GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_B, "infra_ao_cldma_b", "axi_sel", 3),
+	GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_B, "infra_ao_audio_26m_b", "clk26m", 4),
+	GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spi_sel", 6),
+	GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, "infra_ao_spi2", "spi_sel", 9),
+	GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, "infra_ao_spi3", "spi_sel", 10),
+	GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_SYS, "infra_ao_unipro_sys", "ufs_sel", 11),
+	GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_TICK, "infra_ao_unipro_tick", "ufs_tick1us_sel", 12),
+	GATE_INFRA_AO2(CLK_INFRA_AO_UFS_MP_SAP_B, "infra_ao_ufs_mp_sap_b", "ufs_mp_sap_sel", 13),
+	GATE_INFRA_AO2(CLK_INFRA_AO_PWRMCU, "infra_ao_pwrmcu", "pwrmcu_sel", 15),
+	GATE_INFRA_AO2(CLK_INFRA_AO_PWRMCU_BUS_H, "infra_ao_pwrmcu_bus_h", "axi_sel", 17),
+	GATE_INFRA_AO2(CLK_INFRA_AO_APDMA_B, "infra_ao_apdma_b", "axi_sel", 18),
+	GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "spi_sel", 25),
+	GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "spi_sel", 26),
+	GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, "infra_ao_cq_dma", "axi_sel", 27),
+	GATE_INFRA_AO2(CLK_INFRA_AO_AES_UFSFDE, "infra_ao_aes_ufsfde", "ufs_sel", 28),
+	GATE_INFRA_AO2(CLK_INFRA_AO_AES, "infra_ao_aes", "aes_ufsfde_sel", 29),
+	GATE_INFRA_AO2(CLK_INFRA_AO_UFS_TICK, "infra_ao_ufs_tick", "ufs_tick1us_sel", 30),
+	GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_XHCI, "infra_ao_ssusb_xhci", "ssusb_xhci_sel", 31),
+	/* INFRA_AO3 */
+	GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, "infra_ao_msdc0_self", "msdc50_0_sel", 0),
+	GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SELF, "infra_ao_msdc1_self", "msdc50_0_sel", 1),
+	GATE_INFRA_AO3(CLK_INFRA_AO_MSDC2_SELF, "infra_ao_msdc2_self", "msdc50_0_sel", 2),
+	GATE_INFRA_AO3(CLK_INFRA_AO_I2S_DMA, "infra_ao_i2s_dma", "axi_sel", 5),
+	GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, "infra_ao_ap_msdc0", "msdc50_0_sel", 7),
+	GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, "infra_ao_md_msdc0", "msdc50_0_sel", 8),
+	GATE_INFRA_AO3(CLK_INFRA_AO_CG3_MSDC2, "infra_ao_cg3_msdc2", "msdc30_2_sel", 9),
+	GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, "infra_ao_gcpu", "gcpu_sel", 10),
+	GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_PERI_26M, "infra_ao_pcie_peri_26m", "clk26m", 15),
+	GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_B, "infra_ao_gcpu_66m_b", "axi_sel", 16),
+	GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_B, "infra_ao_gcpu_133m_b", "axi_sel", 17),
+	GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, "infra_ao_disp_pwm1", "disp_pwm1_sel", 20),
+	GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, "infra_ao_fbist2fpc", "msdc50_0_sel", 24),
+	GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_DEVICE_APC_SYNC, "infra_ao_device_apc_sync", "axi_sel",
+		25, CLK_IS_CRITICAL),
+	GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_P1_PERI_26M, "infra_ao_pcie_p1_peri_26m", "clk26m", 26),
+	GATE_INFRA_AO3(CLK_INFRA_AO_SPIS0, "infra_ao_spis0", "spis_sel", 28),
+	GATE_INFRA_AO3(CLK_INFRA_AO_SPIS1, "infra_ao_spis1", "spis_sel", 29),
+	/* INFRA_AO4 */
+	GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_133M_M_PERI, "infra_ao_133m_m_peri", "axi_sel", 0,
+		CLK_IS_CRITICAL),
+	GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_66M_M_PERI, "infra_ao_66m_m_peri", "spi_sel", 1,
+		CLK_IS_CRITICAL),
+	GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P0, "infra_ao_pcie_pl_p_250m_p0", "pextp_pipe",
+		7),
+	GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P1, "infra_ao_pcie_pl_p_250m_p1",
+		"ssusb_u3phy_p1_p_p0", 8),
+	GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_P1_TL_96M, "infra_ao_pcie_p1_tl_96m", "tl_p1_sel", 17),
+	GATE_INFRA_AO4(CLK_INFRA_AO_AES_MSDCFDE_0P, "infra_ao_aes_msdcfde_0p", "aes_msdcfde_sel",
+		18),
+	GATE_INFRA_AO4(CLK_INFRA_AO_UFS_TX_SYMBOL, "infra_ao_ufs_tx_symbol", "ufs_tx_symbol", 22),
+	GATE_INFRA_AO4(CLK_INFRA_AO_UFS_RX_SYMBOL, "infra_ao_ufs_rx_symbol", "ufs_rx_symbol", 23),
+	GATE_INFRA_AO4(CLK_INFRA_AO_UFS_RX_SYMBOL1, "infra_ao_ufs_rx_symbol1", "ufs_rx_symbol1",
+		24),
+	GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31),
+};
+
+static const struct mtk_gate_regs peri_ao_cg_regs = {
+	.set_ofs = 0x10,
+	.clr_ofs = 0x14,
+	.sta_ofs = 0x18,
+};
+
+#define GATE_PERI_AO(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &peri_ao_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate peri_ao_clks[] = {
+	GATE_PERI_AO(CLK_PERI_AO_ETHERNET, "peri_ao_ethernet", "axi_sel", 0),
+	GATE_PERI_AO(CLK_PERI_AO_ETHERNET_BUS, "peri_ao_ethernet_bus", "axi_sel", 1),
+	GATE_PERI_AO(CLK_PERI_AO_FLASHIF_BUS, "peri_ao_flashif_bus", "axi_sel", 3),
+	GATE_PERI_AO(CLK_PERI_AO_FLASHIF_FLASH, "peri_ao_flashif_flash", "spinor_sel", 5),
+	GATE_PERI_AO(CLK_PERI_AO_SSUSB_1P_BUS, "peri_ao_ssusb_1p_bus", "usb_1p_sel", 7),
+	GATE_PERI_AO(CLK_PERI_AO_SSUSB_1P_XHCI, "peri_ao_ssusb_1p_xhci", "ssusb_xhci_1p_sel", 8),
+	GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_BUS, "peri_ao_ssusb_2p_bus", "usb_2p_sel", 9),
+	GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_XHCI, "peri_ao_ssusb_2p_xhci", "ssusb_xhci_2p_sel", 10),
+	GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_BUS, "peri_ao_ssusb_3p_bus", "usb_3p_sel", 11),
+	GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_XHCI, "peri_ao_ssusb_3p_xhci", "ssusb_xhci_3p_sel", 12),
+	GATE_PERI_AO(CLK_PERI_AO_SPINFI, "peri_ao_spinfi", "spinfi_b_sel", 15),
+	GATE_PERI_AO(CLK_PERI_AO_ETHERNET_MAC, "peri_ao_ethernet_mac", "snps_eth_250m_sel", 16),
+	GATE_PERI_AO(CLK_PERI_AO_NFI_H, "peri_ao_nfi_h", "axi_sel", 19),
+	GATE_PERI_AO(CLK_PERI_AO_FNFI1X, "peri_ao_fnfi1x", "nfi1x_sel", 20),
+	GATE_PERI_AO(CLK_PERI_AO_PCIE_P0_MEM, "peri_ao_pcie_p0_mem", "mem_466m", 24),
+	GATE_PERI_AO(CLK_PERI_AO_PCIE_P1_MEM, "peri_ao_pcie_p1_mem", "mem_466m", 25),
+};
+
+static const struct mtk_gate_regs top0_cg_regs = {
+	.set_ofs = 0x238,
+	.clr_ofs = 0x238,
+	.sta_ofs = 0x238,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+	.set_ofs = 0x250,
+	.clr_ofs = 0x250,
+	.sta_ofs = 0x250,
+};
+
+#define GATE_TOP0_FLAGS(_id, _name, _parent, _shift, _flag)		\
+	GATE_MTK_FLAGS(_id, _name, _parent, &top0_cg_regs, _shift,	\
+		&mtk_clk_gate_ops_no_setclr_inv, _flag)
+
+#define GATE_TOP0(_id, _name, _parent, _shift)			\
+	GATE_TOP0_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_TOP1(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+static const struct mtk_gate top_clks[] = {
+	/* TOP0 */
+	GATE_TOP0(CLK_TOP_CFG_VPP0, "cfg_vpp0", "vpp_sel", 0),
+	GATE_TOP0(CLK_TOP_CFG_VPP1, "cfg_vpp1", "vpp_sel", 1),
+	GATE_TOP0(CLK_TOP_CFG_VDO0, "cfg_vdo0", "vpp_sel", 2),
+	GATE_TOP0(CLK_TOP_CFG_VDO1, "cfg_vdo1", "vpp_sel", 3),
+	GATE_TOP0(CLK_TOP_CFG_UNIPLL_SES, "cfg_unipll_ses", "univpll_d2", 4),
+	GATE_TOP0(CLK_TOP_CFG_26M_VPP0, "cfg_26m_vpp0", "clk26m", 5),
+	GATE_TOP0(CLK_TOP_CFG_26M_VPP1, "cfg_26m_vpp1", "clk26m", 6),
+	GATE_TOP0(CLK_TOP_CFG_26M_AUD, "cfg_26m_aud", "clk26m", 9),
+	GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST, "cfg_axi_east", "axi_sel", 10, CLK_IS_CRITICAL),
+	GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST_NORTH, "cfg_axi_east_north", "axi_sel", 11,
+		CLK_IS_CRITICAL),
+	GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_NORTH, "cfg_axi_north", "axi_sel", 12, CLK_IS_CRITICAL),
+	GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_SOUTH, "cfg_axi_south", "axi_sel", 13, CLK_IS_CRITICAL),
+	GATE_TOP0(CLK_TOP_CFG_EXT_TEST, "cfg_ext_test", "msdcpll_d2", 15),
+	/* TOP1 */
+	GATE_TOP1(CLK_TOP_SSUSB_REF, "ssusb_ref", "clk26m", 0),
+	GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 1),
+	GATE_TOP1(CLK_TOP_SSUSB_P1_REF, "ssusb_p1_ref", "clk26m", 2),
+	GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, "ssusb_phy_p1_ref", "clk26m", 3),
+	GATE_TOP1(CLK_TOP_SSUSB_P2_REF, "ssusb_p2_ref", "clk26m", 4),
+	GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, "ssusb_phy_p2_ref", "clk26m", 5),
+	GATE_TOP1(CLK_TOP_SSUSB_P3_REF, "ssusb_p3_ref", "clk26m", 6),
+	GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, "ssusb_phy_p3_ref", "clk26m", 7),
+};
+
+static const struct mtk_gate_regs apmixed_cg_regs = {
+	.set_ofs = 0x8,
+	.clr_ofs = 0x8,
+	.sta_ofs = 0x8,
+};
+
+#define GATE_APMIXED(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+static const struct mtk_gate apmixed_clks[] = {
+	GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M, "pll_ssusb26m", "clk26m", 1),
+};
+
+#define MT8195_PLL_FMAX		(3800UL * MHZ)
+#define MT8195_PLL_FMIN		(1500UL * MHZ)
+#define MT8195_INTEGER_BITS	8
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags,	\
+			_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift,	\
+			_tuner_reg, _tuner_en_reg, _tuner_en_bit,	\
+			_pcw_reg, _pcw_shift, _pcw_chg_reg,				\
+			_en_reg, _pll_en_bit) {					\
+		.id = _id,						\
+		.name = _name,						\
+		.reg = _reg,						\
+		.pwr_reg = _pwr_reg,					\
+		.en_mask = _en_mask,					\
+		.flags = _flags,					\
+		.rst_bar_mask = _rst_bar_mask,				\
+		.fmax = MT8195_PLL_FMAX,				\
+		.fmin = MT8195_PLL_FMIN,				\
+		.pcwbits = _pcwbits,					\
+		.pcwibits = MT8195_INTEGER_BITS,			\
+		.pd_reg = _pd_reg,					\
+		.pd_shift = _pd_shift,					\
+		.tuner_reg = _tuner_reg,				\
+		.tuner_en_reg = _tuner_en_reg,				\
+		.tuner_en_bit = _tuner_en_bit,				\
+		.pcw_reg = _pcw_reg,					\
+		.pcw_shift = _pcw_shift,				\
+		.pcw_chg_reg = _pcw_chg_reg,				\
+		.en_reg = _en_reg,					\
+		.pll_en_bit = _pll_en_bit,				\
+	}
+
+static const struct mtk_pll_data plls[] = {
+	PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0, 0,
+		0, 0, 22, 0x0398, 24, 0, 0, 0, 0x0398, 0, 0x0398, 0, 9),
+	PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320, 0,
+		0, 0, 22, 0x0198, 24, 0, 0, 0, 0x0198, 0, 0x0198, 0, 9),
+	PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370, 0,
+		0, 0, 22, 0x0368, 24, 0, 0, 0, 0x0368, 0, 0x0368, 0, 9),
+	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
+		0, 0, 22, 0x0718, 24, 0, 0, 0, 0x0718, 0, 0x0718, 0, 9),
+	PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x00a0, 0x00b0, 0,
+		0, 0, 22, 0x00a8, 24, 0, 0, 0, 0x00a8, 0, 0x00a8, 0, 9),
+	PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x00c0, 0x00d0, 0,
+		0, 0, 22, 0x00c8, 24, 0, 0, 0, 0x00c8, 0, 0x00c8, 0, 9),
+	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x00e0, 0x00f0, 0xff000000,
+		HAVE_RST_BAR, BIT(23), 22, 0x00e8, 24, 0, 0, 0, 0x00e8, 0, 0x00e8, 0, 9),
+	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x01d0, 0x01e0, 0xff000000,
+		HAVE_RST_BAR, BIT(23), 22, 0x01d8, 24, 0, 0, 0, 0x01d8, 0, 0x01d8, 0, 9),
+	PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x0890, 0x08a0, 0,
+		0, 0, 22, 0x0898, 24, 0, 0, 0, 0x0898, 0, 0x0898, 0, 9),
+	PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0100, 0x0110, 0,
+		0, 0, 22, 0x0108, 24, 0, 0, 0, 0x0108, 0, 0x0108, 0, 9),
+	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x01f0, 0x0700, 0xff000000,
+		HAVE_RST_BAR, BIT(23), 22, 0x01f8, 24, 0, 0, 0, 0x01f8, 0, 0x01f8, 0, 9),
+	PLL(CLK_APMIXED_HDMIPLL1, "hdmipll1", 0x08c0, 0x08d0, 0,
+		0, 0, 22, 0x08c8, 24, 0, 0, 0, 0x08c8, 0, 0x08c8, 0, 9),
+	PLL(CLK_APMIXED_HDMIPLL2, "hdmipll2", 0x0870, 0x0880, 0,
+		0, 0, 22, 0x0878, 24, 0, 0, 0, 0x0878, 0, 0x0878, 0, 9),
+	PLL(CLK_APMIXED_HDMIRX_APLL, "hdmirx_apll", 0x08e0, 0x0dd4, 0,
+		0, 0, 32, 0x08e8, 24, 0, 0, 0, 0x08ec, 0, 0x08e8, 0, 9),
+	PLL(CLK_APMIXED_USB1PLL, "usb1pll", 0x01a0, 0x01b0, 0,
+		0, 0, 22, 0x01a8, 24, 0, 0, 0, 0x01a8, 0, 0x01a8, 0, 9),
+	PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x07e0, 0x07f0, 0,
+		0, 0, 22, 0x07e8, 24, 0, 0, 0, 0x07e8, 0, 0x07e8, 0, 9),
+	PLL(CLK_APMIXED_APLL1, "apll1", 0x07c0, 0x0dc0, 0,
+		0, 0, 32, 0x07c8, 24, 0x0470, 0x0000, 12, 0x07cc, 0, 0x07c8, 0, 9),
+	PLL(CLK_APMIXED_APLL2, "apll2", 0x0780, 0x0dc4, 0,
+		0, 0, 32, 0x0788, 24, 0x0474, 0x0000, 13, 0x078c, 0, 0x0788, 0, 9),
+	PLL(CLK_APMIXED_APLL3, "apll3", 0x0760, 0x0dc8, 0,
+		0, 0, 32, 0x0768, 24, 0x0478, 0x0000, 14, 0x076c, 0, 0x0768, 0, 9),
+	PLL(CLK_APMIXED_APLL4, "apll4", 0x0740, 0x0dcc, 0,
+		0, 0, 32, 0x0748, 24, 0x047C, 0x0000, 15, 0x074c, 0, 0x0748, 0, 9),
+	PLL(CLK_APMIXED_APLL5, "apll5", 0x07a0, 0x0dd0, 0x100000,
+		0, 0, 32, 0x07a8, 24, 0x0480, 0x0000, 16, 0x07ac, 0, 0x07a8, 0, 9),
+	PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x0350, 0,
+		0, 0, 22, 0x0348, 24, 0, 0, 0, 0x0348, 0, 0x0348, 0, 9),
+	PLL(CLK_APMIXED_DGIPLL, "dgipll", 0x0150, 0x0160, 0,
+		0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0, 0x0158, 0, 9),
+};
+
+static struct clk_onecell_data *top_clk_data;
+
+static void clk_mt8195_top_init_early(struct device_node *node)
+{
+	int i;
+
+	top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+	if (!top_clk_data)
+		return;
+
+	for (i = 0; i < CLK_TOP_NR_CLK; i++)
+		top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
+
+	mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data);
+
+	of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
+}
+
+CLK_OF_DECLARE_DRIVER(mt8195_topckgen, "mediatek,mt8195-topckgen",
+			clk_mt8195_top_init_early);
+
+static int clk_mt8195_top_probe(struct platform_device *pdev)
+{
+	struct device_node *node = pdev->dev.of_node;
+	int r;
+	void __iomem *base;
+
+	base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
+			top_clk_data);
+	mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data);
+	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
+	mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node,
+			&mt8195_clk_lock, top_clk_data);
+	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
+			&mt8195_clk_lock, top_clk_data);
+	mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
+			&mt8195_clk_lock, top_clk_data);
+	r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data);
+	if (r)
+		return r;
+
+	return of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
+}
+
+static int clk_mt8195_infra_ao_probe(struct platform_device *pdev)
+{
+	struct clk_onecell_data *clk_data;
+	struct device_node *node = pdev->dev.of_node;
+	int r;
+
+	clk_data = mtk_alloc_clk_data(CLK_INFRA_AO_NR_CLK);
+	if (!clk_data)
+		return -ENOMEM;
+
+	r = mtk_clk_register_gates(node, infra_ao_clks, ARRAY_SIZE(infra_ao_clks), clk_data);
+	if (r)
+		return r;
+
+	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
+{
+	struct clk_onecell_data *clk_data;
+	struct device_node *node = pdev->dev.of_node;
+	int r;
+
+	clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+	if (!clk_data)
+		return -ENOMEM;
+
+	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+	r = mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
+	if (r)
+		return r;
+
+	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static int clk_mt8195_peri_ao_probe(struct platform_device *pdev)
+{
+	struct clk_onecell_data *clk_data;
+	struct device_node *node = pdev->dev.of_node;
+	int r;
+
+	clk_data = mtk_alloc_clk_data(CLK_PERI_AO_NR_CLK);
+	if (!clk_data)
+		return -ENOMEM;
+
+	r = mtk_clk_register_gates(node, peri_ao_clks, ARRAY_SIZE(peri_ao_clks), clk_data);
+	if (r)
+		return r;
+
+	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8195[] = {
+	{
+		.compatible = "mediatek,mt8195-apmixedsys",
+		.data = clk_mt8195_apmixed_probe,
+	}, {
+		.compatible = "mediatek,mt8195-topckgen",
+		.data = clk_mt8195_top_probe,
+	}, {
+		.compatible = "mediatek,mt8195-infracfg_ao",
+		.data = clk_mt8195_infra_ao_probe,
+	}, {
+		.compatible = "mediatek,mt8195-pericfg_ao",
+		.data = clk_mt8195_peri_ao_probe,
+	}, {
+		/* sentinel */
+	}
+};
+
+static int clk_mt8195_probe(struct platform_device *pdev)
+{
+	int (*clk_probe)(struct platform_device *pdev);
+	int r;
+
+	clk_probe = of_device_get_match_data(&pdev->dev);
+	if (!clk_probe)
+		return -EINVAL;
+
+	r = clk_probe(pdev);
+	if (r)
+		dev_err(&pdev->dev,
+			"could not register clock provider: %s: %d\n",
+			pdev->name, r);
+
+	return r;
+}
+
+static struct platform_driver clk_mt8195_drv = {
+	.probe = clk_mt8195_probe,
+	.driver = {
+		.name = "clk-mt8195",
+		.of_match_table = of_match_clk_mt8195,
+	},
+};
+
+static int __init clk_mt8195_init(void)
+{
+	return platform_driver_register(&clk_mt8195_drv);
+}
+
+arch_initcall(clk_mt8195_init);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 05/22] clk: mediatek: Add MT8195 audio clock support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (3 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 04/22] clk: mediatek: Add MT8195 basic clocks support Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-07-05  9:03   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 06/22] clk: mediatek: Add MT8195 audio src " Chun-Jie Chen
                   ` (16 subsequent siblings)
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 audio clock provider

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig          |   6 +
 drivers/clk/mediatek/Makefile         |   1 +
 drivers/clk/mediatek/clk-mt8195-aud.c | 198 ++++++++++++++++++++++++++
 3 files changed, 205 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-aud.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 6707aba3d500..e2bae9d490a4 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -588,6 +588,12 @@ config COMMON_CLK_MT8195
 	help
 	  This driver supports MediaTek MT8195 basic clocks.
 
+config COMMON_CLK_MT8195_AUDSYS
+	bool "Clock driver for MediaTek MT8195 audsys"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 audsys clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index f8002d8966e1..f27c04314186 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -81,5 +81,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o
 obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
 obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
 obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195.o
+obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS) += clk-mt8195-aud.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-aud.c b/drivers/clk/mediatek/clk-mt8195-aud.c
new file mode 100644
index 000000000000..db5f80d41de0
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-aud.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static const struct mtk_gate_regs aud0_cg_regs = {
+	.set_ofs = 0x0,
+	.clr_ofs = 0x0,
+	.sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs aud1_cg_regs = {
+	.set_ofs = 0x10,
+	.clr_ofs = 0x10,
+	.sta_ofs = 0x10,
+};
+
+static const struct mtk_gate_regs aud2_cg_regs = {
+	.set_ofs = 0x14,
+	.clr_ofs = 0x14,
+	.sta_ofs = 0x14,
+};
+
+static const struct mtk_gate_regs aud3_cg_regs = {
+	.set_ofs = 0x18,
+	.clr_ofs = 0x18,
+	.sta_ofs = 0x18,
+};
+
+static const struct mtk_gate_regs aud4_cg_regs = {
+	.set_ofs = 0x4,
+	.clr_ofs = 0x4,
+	.sta_ofs = 0x4,
+};
+
+static const struct mtk_gate_regs aud5_cg_regs = {
+	.set_ofs = 0xc,
+	.clr_ofs = 0xc,
+	.sta_ofs = 0xc,
+};
+
+#define GATE_AUD0(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &aud0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
+
+#define GATE_AUD1(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &aud1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
+
+#define GATE_AUD2(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &aud2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
+
+#define GATE_AUD3(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &aud3_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
+
+#define GATE_AUD4(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &aud4_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
+
+#define GATE_AUD5(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &aud5_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
+
+static const struct mtk_gate aud_clks[] = {
+	/* AUD0 */
+	GATE_AUD0(CLK_AUD_AFE, "aud_afe", "a1sys_hp_sel", 2),
+	GATE_AUD0(CLK_AUD_LRCK_CNT, "aud_lrck_cnt", "a1sys_hp_sel", 4),
+	GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_APLL, "aud_spdifin_tuner_apll", "apll4_sel", 10),
+	GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_DBG, "aud_spdifin_tuner_dbg", "apll4_sel", 11),
+	GATE_AUD0(CLK_AUD_UL_TML, "aud_ul_tml", "a1sys_hp_sel", 18),
+	GATE_AUD0(CLK_AUD_APLL1_TUNER, "aud_apll1_tuner", "apll1_sel", 19),
+	GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "apll2_sel", 20),
+	GATE_AUD0(CLK_AUD_TOP0_SPDF, "aud_top0_spdf", "aud_iec_sel", 21),
+	GATE_AUD0(CLK_AUD_APLL, "aud_apll", "apll1_sel", 23),
+	GATE_AUD0(CLK_AUD_APLL2, "aud_apll2", "apll2_sel", 24),
+	GATE_AUD0(CLK_AUD_DAC, "aud_dac", "a1sys_hp_sel", 25),
+	GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "a1sys_hp_sel", 26),
+	GATE_AUD0(CLK_AUD_TML, "aud_tml", "a1sys_hp_sel", 27),
+	GATE_AUD0(CLK_AUD_ADC, "aud_adc", "a1sys_hp_sel", 28),
+	GATE_AUD0(CLK_AUD_DAC_HIRES, "aud_dac_hires", "audio_h_sel", 31),
+	/* AUD1 */
+	GATE_AUD1(CLK_AUD_I2SIN, "aud_i2sin", "a1sys_hp_sel", 0),
+	GATE_AUD1(CLK_AUD_TDM_IN, "aud_tdm_in", "a1sys_hp_sel", 1),
+	GATE_AUD1(CLK_AUD_I2S_OUT, "aud_i2s_out", "a1sys_hp_sel", 6),
+	GATE_AUD1(CLK_AUD_TDM_OUT, "aud_tdm_out", "a1sys_hp_sel", 7),
+	GATE_AUD1(CLK_AUD_HDMI_OUT, "aud_hdmi_out", "a1sys_hp_sel", 8),
+	GATE_AUD1(CLK_AUD_ASRC11, "aud_asrc11", "a1sys_hp_sel", 16),
+	GATE_AUD1(CLK_AUD_ASRC12, "aud_asrc12", "a1sys_hp_sel", 17),
+	GATE_AUD1(CLK_AUD_MULTI_IN, "aud_multi_in", "mphone_slave_b", 19),
+	GATE_AUD1(CLK_AUD_INTDIR, "aud_intdir", "intdir_sel", 20),
+	GATE_AUD1(CLK_AUD_A1SYS, "aud_a1sys", "a1sys_hp_sel", 21),
+	GATE_AUD1(CLK_AUD_A2SYS, "aud_a2sys", "a2sys_sel", 22),
+	GATE_AUD1(CLK_AUD_PCMIF, "aud_pcmif", "a1sys_hp_sel", 24),
+	GATE_AUD1(CLK_AUD_A3SYS, "aud_a3sys", "a3sys_sel", 30),
+	GATE_AUD1(CLK_AUD_A4SYS, "aud_a4sys", "a4sys_sel", 31),
+	/* AUD2 */
+	GATE_AUD2(CLK_AUD_MEMIF_UL1, "aud_memif_ul1", "a1sys_hp_sel", 0),
+	GATE_AUD2(CLK_AUD_MEMIF_UL2, "aud_memif_ul2", "a1sys_hp_sel", 1),
+	GATE_AUD2(CLK_AUD_MEMIF_UL3, "aud_memif_ul3", "a1sys_hp_sel", 2),
+	GATE_AUD2(CLK_AUD_MEMIF_UL4, "aud_memif_ul4", "a1sys_hp_sel", 3),
+	GATE_AUD2(CLK_AUD_MEMIF_UL5, "aud_memif_ul5", "a1sys_hp_sel", 4),
+	GATE_AUD2(CLK_AUD_MEMIF_UL6, "aud_memif_ul6", "a1sys_hp_sel", 5),
+	GATE_AUD2(CLK_AUD_MEMIF_UL8, "aud_memif_ul8", "a1sys_hp_sel", 7),
+	GATE_AUD2(CLK_AUD_MEMIF_UL9, "aud_memif_ul9", "a1sys_hp_sel", 8),
+	GATE_AUD2(CLK_AUD_MEMIF_UL10, "aud_memif_ul10", "a1sys_hp_sel", 9),
+	GATE_AUD2(CLK_AUD_MEMIF_DL2, "aud_memif_dl2", "a1sys_hp_sel", 18),
+	GATE_AUD2(CLK_AUD_MEMIF_DL3, "aud_memif_dl3", "a1sys_hp_sel", 19),
+	GATE_AUD2(CLK_AUD_MEMIF_DL6, "aud_memif_dl6", "a1sys_hp_sel", 22),
+	GATE_AUD2(CLK_AUD_MEMIF_DL7, "aud_memif_dl7", "a1sys_hp_sel", 23),
+	GATE_AUD2(CLK_AUD_MEMIF_DL8, "aud_memif_dl8", "a1sys_hp_sel", 24),
+	GATE_AUD2(CLK_AUD_MEMIF_DL10, "aud_memif_dl10", "a1sys_hp_sel", 26),
+	GATE_AUD2(CLK_AUD_MEMIF_DL11, "aud_memif_dl11", "a1sys_hp_sel", 27),
+	/* AUD3 */
+	GATE_AUD3(CLK_AUD_GASRC0, "aud_gasrc0", "asm_h_sel", 0),
+	GATE_AUD3(CLK_AUD_GASRC1, "aud_gasrc1", "asm_h_sel", 1),
+	GATE_AUD3(CLK_AUD_GASRC2, "aud_gasrc2", "asm_h_sel", 2),
+	GATE_AUD3(CLK_AUD_GASRC3, "aud_gasrc3", "asm_h_sel", 3),
+	GATE_AUD3(CLK_AUD_GASRC4, "aud_gasrc4", "asm_h_sel", 4),
+	GATE_AUD3(CLK_AUD_GASRC5, "aud_gasrc5", "asm_h_sel", 5),
+	GATE_AUD3(CLK_AUD_GASRC6, "aud_gasrc6", "asm_h_sel", 6),
+	GATE_AUD3(CLK_AUD_GASRC7, "aud_gasrc7", "asm_h_sel", 7),
+	GATE_AUD3(CLK_AUD_GASRC8, "aud_gasrc8", "asm_h_sel", 8),
+	GATE_AUD3(CLK_AUD_GASRC9, "aud_gasrc9", "asm_h_sel", 9),
+	GATE_AUD3(CLK_AUD_GASRC10, "aud_gasrc10", "asm_h_sel", 10),
+	GATE_AUD3(CLK_AUD_GASRC11, "aud_gasrc11", "asm_h_sel", 11),
+	GATE_AUD3(CLK_AUD_GASRC12, "aud_gasrc12", "asm_h_sel", 12),
+	GATE_AUD3(CLK_AUD_GASRC13, "aud_gasrc13", "asm_h_sel", 13),
+	GATE_AUD3(CLK_AUD_GASRC14, "aud_gasrc14", "asm_h_sel", 14),
+	GATE_AUD3(CLK_AUD_GASRC15, "aud_gasrc15", "asm_h_sel", 15),
+	GATE_AUD3(CLK_AUD_GASRC16, "aud_gasrc16", "asm_h_sel", 16),
+	GATE_AUD3(CLK_AUD_GASRC17, "aud_gasrc17", "asm_h_sel", 17),
+	GATE_AUD3(CLK_AUD_GASRC18, "aud_gasrc18", "asm_h_sel", 18),
+	GATE_AUD3(CLK_AUD_GASRC19, "aud_gasrc19", "asm_h_sel", 19),
+	/* AUD4 */
+	GATE_AUD4(CLK_AUD_A1SYS_HP, "aud_a1sys_hp", "a1sys_hp_sel", 2),
+	GATE_AUD4(CLK_AUD_AFE_DMIC1, "aud_afe_dmic1", "a1sys_hp_sel", 10),
+	GATE_AUD4(CLK_AUD_AFE_DMIC2, "aud_afe_dmic2", "a1sys_hp_sel", 11),
+	GATE_AUD4(CLK_AUD_AFE_DMIC3, "aud_afe_dmic3", "a1sys_hp_sel", 12),
+	GATE_AUD4(CLK_AUD_AFE_DMIC4, "aud_afe_dmic4", "a1sys_hp_sel", 13),
+	GATE_AUD4(CLK_AUD_AFE_26M_DMIC_TM, "aud_afe_26m_dmic_tm", "a1sys_hp_sel", 14),
+	GATE_AUD4(CLK_AUD_UL_TML_HIRES, "aud_ul_tml_hires", "audio_h_sel", 16),
+	GATE_AUD4(CLK_AUD_ADC_HIRES, "aud_adc_hires", "audio_h_sel", 17),
+	GATE_AUD4(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "a1sys_hp_sel", 18),
+	GATE_AUD4(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "audio_h_sel", 19),
+	/* AUD5 */
+	GATE_AUD5(CLK_AUD_LINEIN_TUNER, "aud_linein_tuner", "apll5_sel", 5),
+	GATE_AUD5(CLK_AUD_EARC_TUNER, "aud_earc_tuner", "apll3_sel", 7),
+};
+
+static int clk_mt8195_aud_probe(struct platform_device *pdev)
+{
+	struct clk_onecell_data *clk_data;
+	struct device_node *node = pdev->dev.of_node;
+	int r;
+
+	clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
+	if (!clk_data)
+		return -ENOMEM;
+
+	r = mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);
+	if (r)
+		return r;
+
+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+	if (r)
+		goto err_clk_provider;
+
+	r = devm_of_platform_populate(&pdev->dev);
+	if (r)
+		goto err_plat_populate;
+
+	return 0;
+
+err_plat_populate:
+	of_clk_del_provider(node);
+err_clk_provider:
+	return r;
+}
+
+static const struct of_device_id of_match_clk_mt8195_aud[] = {
+	{ .compatible = "mediatek,mt8195-audsys", },
+	{}
+};
+
+static struct platform_driver clk_mt8195_aud_drv = {
+	.probe = clk_mt8195_aud_probe,
+	.driver = {
+		.name = "clk-mt8195-aud",
+		.of_match_table = of_match_clk_mt8195_aud,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_aud_drv);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 06/22] clk: mediatek: Add MT8195 audio src clock support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (4 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 05/22] clk: mediatek: Add MT8195 audio clock support Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-07-05 10:07   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 07/22] clk: mediatek: Add MT8195 camsys " Chun-Jie Chen
                   ` (15 subsequent siblings)
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 audio src source clock provider

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig              |  6 +++
 drivers/clk/mediatek/Makefile             |  1 +
 drivers/clk/mediatek/clk-mt8195-aud_src.c | 60 +++++++++++++++++++++++
 3 files changed, 67 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-aud_src.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index e2bae9d490a4..62dd02bc2755 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -594,6 +594,12 @@ config COMMON_CLK_MT8195_AUDSYS
 	help
 	  This driver supports MediaTek MT8195 audsys clocks.
 
+config COMMON_CLK_MT8195_AUDSYS_SRC
+	bool "Clock driver for MediaTek MT8195 audsys_src"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 audsys_src clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index f27c04314186..52a5d3f49ff0 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -82,5 +82,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
 obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
 obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195.o
 obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS) += clk-mt8195-aud.o
+obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS_SRC) += clk-mt8195-aud_src.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-aud_src.c b/drivers/clk/mediatek/clk-mt8195-aud_src.c
new file mode 100644
index 000000000000..7cabe0d68825
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-aud_src.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static const struct mtk_gate_regs aud_src_cg_regs = {
+	.set_ofs = 0x1004,
+	.clr_ofs = 0x1004,
+	.sta_ofs = 0x1004,
+};
+
+#define GATE_AUD_SRC(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &aud_src_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
+
+static const struct mtk_gate aud_src_clks[] = {
+	GATE_AUD_SRC(CLK_AUD_SRC_ASRC0, "aud_src_asrc0", "asm_h_sel", 0),
+	GATE_AUD_SRC(CLK_AUD_SRC_ASRC1, "aud_src_asrc1", "asm_h_sel", 1),
+	GATE_AUD_SRC(CLK_AUD_SRC_ASRC2, "aud_src_asrc2", "asm_h_sel", 2),
+	GATE_AUD_SRC(CLK_AUD_SRC_ASRC3, "aud_src_asrc3", "asm_h_sel", 3),
+	GATE_AUD_SRC(CLK_AUD_SRC_ASRC4, "aud_src_asrc4", "asm_h_sel", 4),
+	GATE_AUD_SRC(CLK_AUD_SRC_ASRC5, "aud_src_asrc5", "asm_h_sel", 5),
+	GATE_AUD_SRC(CLK_AUD_SRC_ASRC6, "aud_src_asrc6", "asm_h_sel", 6),
+	GATE_AUD_SRC(CLK_AUD_SRC_ASRC7, "aud_src_asrc7", "asm_h_sel", 7),
+	GATE_AUD_SRC(CLK_AUD_SRC_ASRC8, "aud_src_asrc8", "asm_h_sel", 8),
+	GATE_AUD_SRC(CLK_AUD_SRC_ASRC9, "aud_src_asrc9", "asm_h_sel", 9),
+	GATE_AUD_SRC(CLK_AUD_SRC_ASRC10, "aud_src_asrc10", "asm_h_sel", 10),
+	GATE_AUD_SRC(CLK_AUD_SRC_ASRC11, "aud_src_asrc11", "asm_h_sel", 11),
+};
+
+static const struct mtk_clk_desc aud_src_desc = {
+	.clks = aud_src_clks,
+	.num_clks = ARRAY_SIZE(aud_src_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8195_aud_src[] = {
+	{
+		.compatible = "mediatek,mt8195-audsys_src",
+		.data = &aud_src_desc,
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver clk_mt8195_aud_src_drv = {
+	.probe = mtk_clk_simple_probe,
+	.driver = {
+		.name = "clk-mt8195-aud_src",
+		.of_match_table = of_match_clk_mt8195_aud_src,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_aud_src_drv);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 07/22] clk: mediatek: Add MT8195 camsys clock support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (5 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 06/22] clk: mediatek: Add MT8195 audio src " Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-07-06  8:53   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 08/22] clk: mediatek: Add MT8195 ccusys " Chun-Jie Chen
                   ` (14 subsequent siblings)
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 camsys clock providers

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig          |   6 ++
 drivers/clk/mediatek/Makefile         |   1 +
 drivers/clk/mediatek/clk-mt8195-cam.c | 144 ++++++++++++++++++++++++++
 3 files changed, 151 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-cam.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 62dd02bc2755..515155f3d185 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -600,6 +600,12 @@ config COMMON_CLK_MT8195_AUDSYS_SRC
 	help
 	  This driver supports MediaTek MT8195 audsys_src clocks.
 
+config COMMON_CLK_MT8195_CAMSYS
+	bool "Clock driver for MediaTek MT8195 camsys"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 camsys clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 52a5d3f49ff0..421064e7418c 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -83,5 +83,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
 obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195.o
 obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS) += clk-mt8195-aud.o
 obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS_SRC) += clk-mt8195-aud_src.o
+obj-$(CONFIG_COMMON_CLK_MT8195_CAMSYS) += clk-mt8195-cam.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-cam.c b/drivers/clk/mediatek/clk-mt8195-cam.c
new file mode 100644
index 000000000000..41f48d4b7de6
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-cam.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static const struct mtk_gate_regs cam_cg_regs = {
+	.set_ofs = 0x4,
+	.clr_ofs = 0x8,
+	.sta_ofs = 0x0,
+};
+
+#define GATE_CAM(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate cam_clks[] = {
+	GATE_CAM(CLK_CAM_LARB13, "cam_larb13", "cam_sel", 0),
+	GATE_CAM(CLK_CAM_LARB14, "cam_larb14", "cam_sel", 1),
+	GATE_CAM(CLK_CAM_MAIN_CAM, "cam_main_cam", "cam_sel", 3),
+	GATE_CAM(CLK_CAM_MAIN_CAMTG, "cam_main_camtg", "cam_sel", 4),
+	GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "cam_sel", 5),
+	GATE_CAM(CLK_CAM_GCAMSVA, "cam_gcamsva", "cam_sel", 6),
+	GATE_CAM(CLK_CAM_GCAMSVB, "cam_gcamsvb", "cam_sel", 7),
+	GATE_CAM(CLK_CAM_GCAMSVC, "cam_gcamsvc", "cam_sel", 8),
+	GATE_CAM(CLK_CAM_SCAMSA, "cam_scamsa", "cam_sel", 9),
+	GATE_CAM(CLK_CAM_SCAMSB, "cam_scamsb", "cam_sel", 10),
+	GATE_CAM(CLK_CAM_CAMSV_TOP, "cam_camsv_top", "cam_sel", 11),
+	GATE_CAM(CLK_CAM_CAMSV_CQ, "cam_camsv_cq", "cam_sel", 12),
+	GATE_CAM(CLK_CAM_ADL, "cam_adl", "cam_sel", 16),
+	GATE_CAM(CLK_CAM_ASG, "cam_asg", "cam_sel", 17),
+	GATE_CAM(CLK_CAM_PDA, "cam_pda", "cam_sel", 18),
+	GATE_CAM(CLK_CAM_FAKE_ENG, "cam_fake_eng", "cam_sel", 19),
+	GATE_CAM(CLK_CAM_MAIN_MRAW0, "cam_main_mraw0", "cam_sel", 20),
+	GATE_CAM(CLK_CAM_MAIN_MRAW1, "cam_main_mraw1", "cam_sel", 21),
+	GATE_CAM(CLK_CAM_MAIN_MRAW2, "cam_main_mraw2", "cam_sel", 22),
+	GATE_CAM(CLK_CAM_MAIN_MRAW3, "cam_main_mraw3", "cam_sel", 23),
+	GATE_CAM(CLK_CAM_CAM2MM0_GALS, "cam_cam2mm0_gals", "cam_sel", 24),
+	GATE_CAM(CLK_CAM_CAM2MM1_GALS, "cam_cam2mm1_gals", "cam_sel", 25),
+	GATE_CAM(CLK_CAM_CAM2SYS_GALS, "cam_cam2sys_gals", "cam_sel", 26),
+};
+
+static const struct mtk_gate cam_mraw_clks[] = {
+	GATE_CAM(CLK_CAM_MRAW_LARBX, "cam_mraw_larbx", "cam_sel", 0),
+	GATE_CAM(CLK_CAM_MRAW_CAMTG, "cam_mraw_camtg", "cam_sel", 2),
+	GATE_CAM(CLK_CAM_MRAW_MRAW0, "cam_mraw_mraw0", "cam_sel", 3),
+	GATE_CAM(CLK_CAM_MRAW_MRAW1, "cam_mraw_mraw1", "cam_sel", 4),
+	GATE_CAM(CLK_CAM_MRAW_MRAW2, "cam_mraw_mraw2", "cam_sel", 5),
+	GATE_CAM(CLK_CAM_MRAW_MRAW3, "cam_mraw_mraw3", "cam_sel", 6),
+};
+
+static const struct mtk_gate cam_rawa_clks[] = {
+	GATE_CAM(CLK_CAM_RAWA_LARBX, "cam_rawa_larbx", "cam_sel", 0),
+	GATE_CAM(CLK_CAM_RAWA_CAM, "cam_rawa_cam", "cam_sel", 1),
+	GATE_CAM(CLK_CAM_RAWA_CAMTG, "cam_rawa_camtg", "cam_sel", 2),
+};
+
+static const struct mtk_gate cam_rawb_clks[] = {
+	GATE_CAM(CLK_CAM_RAWB_LARBX, "cam_rawb_larbx", "cam_sel", 0),
+	GATE_CAM(CLK_CAM_RAWB_CAM, "cam_rawb_cam", "cam_sel", 1),
+	GATE_CAM(CLK_CAM_RAWB_CAMTG, "cam_rawb_camtg", "cam_sel", 2),
+};
+
+static const struct mtk_gate cam_yuva_clks[] = {
+	GATE_CAM(CLK_CAM_YUVA_LARBX, "cam_yuva_larbx", "cam_sel", 0),
+	GATE_CAM(CLK_CAM_YUVA_CAM, "cam_yuva_cam", "cam_sel", 1),
+	GATE_CAM(CLK_CAM_YUVA_CAMTG, "cam_yuva_camtg", "cam_sel", 2),
+};
+
+static const struct mtk_gate cam_yuvb_clks[] = {
+	GATE_CAM(CLK_CAM_YUVB_LARBX, "cam_yuvb_larbx", "cam_sel", 0),
+	GATE_CAM(CLK_CAM_YUVB_CAM, "cam_yuvb_cam", "cam_sel", 1),
+	GATE_CAM(CLK_CAM_YUVB_CAMTG, "cam_yuvb_camtg", "cam_sel", 2),
+};
+
+static const struct mtk_clk_desc cam_desc = {
+	.clks = cam_clks,
+	.num_clks = ARRAY_SIZE(cam_clks),
+};
+
+static const struct mtk_clk_desc cam_mraw_desc = {
+	.clks = cam_mraw_clks,
+	.num_clks = ARRAY_SIZE(cam_mraw_clks),
+};
+
+static const struct mtk_clk_desc cam_rawa_desc = {
+	.clks = cam_rawa_clks,
+	.num_clks = ARRAY_SIZE(cam_rawa_clks),
+};
+
+static const struct mtk_clk_desc cam_rawb_desc = {
+	.clks = cam_rawb_clks,
+	.num_clks = ARRAY_SIZE(cam_rawb_clks),
+};
+
+static const struct mtk_clk_desc cam_yuva_desc = {
+	.clks = cam_yuva_clks,
+	.num_clks = ARRAY_SIZE(cam_yuva_clks),
+};
+
+static const struct mtk_clk_desc cam_yuvb_desc = {
+	.clks = cam_yuvb_clks,
+	.num_clks = ARRAY_SIZE(cam_yuvb_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8195_cam[] = {
+	{
+		.compatible = "mediatek,mt8195-camsys",
+		.data = &cam_desc,
+	}, {
+		.compatible = "mediatek,mt8195-camsys_mraw",
+		.data = &cam_mraw_desc,
+	}, {
+		.compatible = "mediatek,mt8195-camsys_rawa",
+		.data = &cam_rawa_desc,
+	}, {
+		.compatible = "mediatek,mt8195-camsys_rawb",
+		.data = &cam_rawb_desc,
+	}, {
+		.compatible = "mediatek,mt8195-camsys_yuva",
+		.data = &cam_yuva_desc,
+	}, {
+		.compatible = "mediatek,mt8195-camsys_yuvb",
+		.data = &cam_yuvb_desc,
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver clk_mt8195_cam_drv = {
+	.probe = mtk_clk_simple_probe,
+	.driver = {
+		.name = "clk-mt8195-cam",
+		.of_match_table = of_match_clk_mt8195_cam,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_cam_drv);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 08/22] clk: mediatek: Add MT8195 ccusys clock support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (6 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 07/22] clk: mediatek: Add MT8195 camsys " Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-07-06  9:00   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 09/22] clk: mediatek: Add MT8195 imgsys " Chun-Jie Chen
                   ` (13 subsequent siblings)
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 ccusys clock provider

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig          |  6 ++++
 drivers/clk/mediatek/Makefile         |  1 +
 drivers/clk/mediatek/clk-mt8195-ccu.c | 52 +++++++++++++++++++++++++++
 3 files changed, 59 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-ccu.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 515155f3d185..6a6e496d08a4 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -606,6 +606,12 @@ config COMMON_CLK_MT8195_CAMSYS
 	help
 	  This driver supports MediaTek MT8195 camsys clocks.
 
+config COMMON_CLK_MT8195_CCUSYS
+	bool "Clock driver for MediaTek MT8195 ccusys"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 ccusys clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 421064e7418c..bb8aac6f9185 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -84,5 +84,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195.o
 obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS) += clk-mt8195-aud.o
 obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS_SRC) += clk-mt8195-aud_src.o
 obj-$(CONFIG_COMMON_CLK_MT8195_CAMSYS) += clk-mt8195-cam.o
+obj-$(CONFIG_COMMON_CLK_MT8195_CCUSYS) += clk-mt8195-ccu.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-ccu.c b/drivers/clk/mediatek/clk-mt8195-ccu.c
new file mode 100644
index 000000000000..6d8c657bedb3
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-ccu.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static const struct mtk_gate_regs ccu_cg_regs = {
+	.set_ofs = 0x4,
+	.clr_ofs = 0x8,
+	.sta_ofs = 0x0,
+};
+
+#define GATE_CCU(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &ccu_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate ccu_clks[] = {
+	GATE_CCU(CLK_CCU_LARB18, "ccu_larb18", "ccu_sel", 0),
+	GATE_CCU(CLK_CCU_AHB, "ccu_ahb", "ccu_sel", 1),
+	GATE_CCU(CLK_CCU_CCU0, "ccu_ccu0", "ccu_sel", 2),
+	GATE_CCU(CLK_CCU_CCU1, "ccu_ccu1", "ccu_sel", 3),
+};
+
+static const struct mtk_clk_desc ccu_desc = {
+	.clks = ccu_clks,
+	.num_clks = ARRAY_SIZE(ccu_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8195_ccu[] = {
+	{
+		.compatible = "mediatek,mt8195-ccusys",
+		.data = &ccu_desc,
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver clk_mt8195_ccu_drv = {
+	.probe = mtk_clk_simple_probe,
+	.driver = {
+		.name = "clk-mt8195-ccu",
+		.of_match_table = of_match_clk_mt8195_ccu,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_ccu_drv);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 09/22] clk: mediatek: Add MT8195 imgsys clock support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (7 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 08/22] clk: mediatek: Add MT8195 ccusys " Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-07-06  9:07   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 10/22] clk: mediatek: Add MT8195 ipesys " Chun-Jie Chen
                   ` (12 subsequent siblings)
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 imgsys clock providers

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig          |  6 ++
 drivers/clk/mediatek/Makefile         |  1 +
 drivers/clk/mediatek/clk-mt8195-img.c | 98 +++++++++++++++++++++++++++
 3 files changed, 105 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-img.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 6a6e496d08a4..f92d0b6b7eec 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -612,6 +612,12 @@ config COMMON_CLK_MT8195_CCUSYS
 	help
 	  This driver supports MediaTek MT8195 ccusys clocks.
 
+config COMMON_CLK_MT8195_IMGSYS
+	bool "Clock driver for MediaTek MT8195 imgsys"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 imgsys clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index bb8aac6f9185..1768eda917c2 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -85,5 +85,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS) += clk-mt8195-aud.o
 obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS_SRC) += clk-mt8195-aud_src.o
 obj-$(CONFIG_COMMON_CLK_MT8195_CAMSYS) += clk-mt8195-cam.o
 obj-$(CONFIG_COMMON_CLK_MT8195_CCUSYS) += clk-mt8195-ccu.o
+obj-$(CONFIG_COMMON_CLK_MT8195_IMGSYS) += clk-mt8195-img.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-img.c b/drivers/clk/mediatek/clk-mt8195-img.c
new file mode 100644
index 000000000000..923fa82aedae
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-img.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static const struct mtk_gate_regs img_cg_regs = {
+	.set_ofs = 0x4,
+	.clr_ofs = 0x8,
+	.sta_ofs = 0x0,
+};
+
+#define GATE_IMG(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate img_clks[] = {
+	GATE_IMG(CLK_IMG_LARB9, "img_larb9", "img_sel", 0),
+	GATE_IMG(CLK_IMG_TRAW0, "img_traw0", "img_sel", 1),
+	GATE_IMG(CLK_IMG_TRAW1, "img_traw1", "img_sel", 2),
+	GATE_IMG(CLK_IMG_TRAW2, "img_traw2", "img_sel", 3),
+	GATE_IMG(CLK_IMG_TRAW3, "img_traw3", "img_sel", 4),
+	GATE_IMG(CLK_IMG_DIP0, "img_dip0", "img_sel", 8),
+	GATE_IMG(CLK_IMG_WPE0, "img_wpe0", "img_sel", 9),
+	GATE_IMG(CLK_IMG_IPE, "img_ipe", "img_sel", 10),
+	GATE_IMG(CLK_IMG_DIP1, "img_dip1", "img_sel", 11),
+	GATE_IMG(CLK_IMG_WPE1, "img_wpe1", "img_sel", 12),
+	GATE_IMG(CLK_IMG_GALS, "img_gals", "img_sel", 31),
+};
+
+static const struct mtk_gate img1_dip_top_clks[] = {
+	GATE_IMG(CLK_IMG1_DIP_TOP_LARB10, "img1_dip_top_larb10", "img_sel", 0),
+	GATE_IMG(CLK_IMG1_DIP_TOP_DIP_TOP, "img1_dip_top_dip_top", "img_sel", 1),
+};
+
+static const struct mtk_gate img1_dip_nr_clks[] = {
+	GATE_IMG(CLK_IMG1_DIP_NR_RESERVE, "img1_dip_nr_reserve", "img_sel", 0),
+	GATE_IMG(CLK_IMG1_DIP_NR_DIP_NR, "img1_dip_nr_dip_nr", "img_sel", 1),
+};
+
+static const struct mtk_gate img1_wpe_clks[] = {
+	GATE_IMG(CLK_IMG1_WPE_LARB11, "img1_wpe_larb11", "img_sel", 0),
+	GATE_IMG(CLK_IMG1_WPE_WPE, "img1_wpe_wpe", "img_sel", 1),
+};
+
+static const struct mtk_clk_desc img_desc = {
+	.clks = img_clks,
+	.num_clks = ARRAY_SIZE(img_clks),
+};
+
+static const struct mtk_clk_desc img1_dip_top_desc = {
+	.clks = img1_dip_top_clks,
+	.num_clks = ARRAY_SIZE(img1_dip_top_clks),
+};
+
+static const struct mtk_clk_desc img1_dip_nr_desc = {
+	.clks = img1_dip_nr_clks,
+	.num_clks = ARRAY_SIZE(img1_dip_nr_clks),
+};
+
+static const struct mtk_clk_desc img1_wpe_desc = {
+	.clks = img1_wpe_clks,
+	.num_clks = ARRAY_SIZE(img1_wpe_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8195_img[] = {
+	{
+		.compatible = "mediatek,mt8195-imgsys",
+		.data = &img_desc,
+	}, {
+		.compatible = "mediatek,mt8195-imgsys1_dip_top",
+		.data = &img1_dip_top_desc,
+	}, {
+		.compatible = "mediatek,mt8195-imgsys1_dip_nr",
+		.data = &img1_dip_nr_desc,
+	}, {
+		.compatible = "mediatek,mt8195-imgsys1_wpe",
+		.data = &img1_wpe_desc,
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver clk_mt8195_img_drv = {
+	.probe = mtk_clk_simple_probe,
+	.driver = {
+		.name = "clk-mt8195-img",
+		.of_match_table = of_match_clk_mt8195_img,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_img_drv);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 10/22] clk: mediatek: Add MT8195 ipesys clock support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (8 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 09/22] clk: mediatek: Add MT8195 imgsys " Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-07-06  9:11   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 11/22] clk: mediatek: Add MT8195 mfgcfg " Chun-Jie Chen
                   ` (11 subsequent siblings)
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 ipesys clock provider

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig          |  6 +++
 drivers/clk/mediatek/Makefile         |  1 +
 drivers/clk/mediatek/clk-mt8195-ipe.c | 53 +++++++++++++++++++++++++++
 3 files changed, 60 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-ipe.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index f92d0b6b7eec..ef7d4b433eee 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -618,6 +618,12 @@ config COMMON_CLK_MT8195_IMGSYS
 	help
 	  This driver supports MediaTek MT8195 imgsys clocks.
 
+config COMMON_CLK_MT8195_IPESYS
+	bool "Clock driver for MediaTek MT8195 ipesys"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 ipesys clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 1768eda917c2..991a9be7ac46 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -86,5 +86,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS_SRC) += clk-mt8195-aud_src.o
 obj-$(CONFIG_COMMON_CLK_MT8195_CAMSYS) += clk-mt8195-cam.o
 obj-$(CONFIG_COMMON_CLK_MT8195_CCUSYS) += clk-mt8195-ccu.o
 obj-$(CONFIG_COMMON_CLK_MT8195_IMGSYS) += clk-mt8195-img.o
+obj-$(CONFIG_COMMON_CLK_MT8195_IPESYS) += clk-mt8195-ipe.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-ipe.c b/drivers/clk/mediatek/clk-mt8195-ipe.c
new file mode 100644
index 000000000000..d63d7448591a
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-ipe.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static const struct mtk_gate_regs ipe_cg_regs = {
+	.set_ofs = 0x0,
+	.clr_ofs = 0x0,
+	.sta_ofs = 0x0,
+};
+
+#define GATE_IPE(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
+
+static const struct mtk_gate ipe_clks[] = {
+	GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "ipe_sel", 0),
+	GATE_IPE(CLK_IPE_FDVT, "ipe_fdvt", "ipe_sel", 1),
+	GATE_IPE(CLK_IPE_ME, "ipe_me", "ipe_sel", 2),
+	GATE_IPE(CLK_IPE_TOP, "ipe_top", "ipe_sel", 3),
+	GATE_IPE(CLK_IPE_SMI_LARB12, "ipe_smi_larb12", "ipe_sel", 4),
+};
+
+static const struct mtk_clk_desc ipe_desc = {
+	.clks = ipe_clks,
+	.num_clks = ARRAY_SIZE(ipe_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8195_ipe[] = {
+	{
+		.compatible = "mediatek,mt8195-ipesys",
+		.data = &ipe_desc,
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver clk_mt8195_ipe_drv = {
+	.probe = mtk_clk_simple_probe,
+	.driver = {
+		.name = "clk-mt8195-ipe",
+		.of_match_table = of_match_clk_mt8195_ipe,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_ipe_drv);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 11/22] clk: mediatek: Add MT8195 mfgcfg clock support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (9 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 10/22] clk: mediatek: Add MT8195 ipesys " Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-07-09  6:29   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 12/22] clk: mediatek: Add MT8195 scp adsp " Chun-Jie Chen
                   ` (10 subsequent siblings)
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 mfgcfg clock provider

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig          |  6 ++++
 drivers/clk/mediatek/Makefile         |  1 +
 drivers/clk/mediatek/clk-mt8195-mfg.c | 49 +++++++++++++++++++++++++++
 3 files changed, 56 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-mfg.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index ef7d4b433eee..066c14a89cee 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -624,6 +624,12 @@ config COMMON_CLK_MT8195_IPESYS
 	help
 	  This driver supports MediaTek MT8195 ipesys clocks.
 
+config COMMON_CLK_MT8195_MFGCFG
+	bool "Clock driver for MediaTek MT8195 mfgcfg"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 mfgcfg clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 991a9be7ac46..9b09e7f640d1 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -87,5 +87,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_CAMSYS) += clk-mt8195-cam.o
 obj-$(CONFIG_COMMON_CLK_MT8195_CCUSYS) += clk-mt8195-ccu.o
 obj-$(CONFIG_COMMON_CLK_MT8195_IMGSYS) += clk-mt8195-img.o
 obj-$(CONFIG_COMMON_CLK_MT8195_IPESYS) += clk-mt8195-ipe.o
+obj-$(CONFIG_COMMON_CLK_MT8195_MFGCFG) += clk-mt8195-mfg.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-mfg.c b/drivers/clk/mediatek/clk-mt8195-mfg.c
new file mode 100644
index 000000000000..a9b1d337cd01
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-mfg.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static const struct mtk_gate_regs mfg_cg_regs = {
+	.set_ofs = 0x4,
+	.clr_ofs = 0x8,
+	.sta_ofs = 0x0,
+};
+
+#define GATE_MFG(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate mfg_clks[] = {
+	GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
+};
+
+static const struct mtk_clk_desc mfg_desc = {
+	.clks = mfg_clks,
+	.num_clks = ARRAY_SIZE(mfg_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8195_mfg[] = {
+	{
+		.compatible = "mediatek,mt8195-mfgcfg",
+		.data = &mfg_desc,
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver clk_mt8195_mfg_drv = {
+	.probe = mtk_clk_simple_probe,
+	.driver = {
+		.name = "clk-mt8195-mfg",
+		.of_match_table = of_match_clk_mt8195_mfg,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_mfg_drv);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 12/22] clk: mediatek: Add MT8195 scp adsp clock support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (10 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 11/22] clk: mediatek: Add MT8195 mfgcfg " Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-07-09  6:39   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 13/22] clk: mediatek: Add MT8195 nnasys " Chun-Jie Chen
                   ` (9 subsequent siblings)
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 scp adsp clock provider

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig               |  6 +++
 drivers/clk/mediatek/Makefile              |  1 +
 drivers/clk/mediatek/clk-mt8195-scp_adsp.c | 49 ++++++++++++++++++++++
 3 files changed, 56 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-scp_adsp.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 066c14a89cee..7cb745d47770 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -630,6 +630,12 @@ config COMMON_CLK_MT8195_MFGCFG
 	help
 	  This driver supports MediaTek MT8195 mfgcfg clocks.
 
+config COMMON_CLK_MT8195_SCP_ADSP
+	bool "Clock driver for MediaTek MT8195 scp_adsp"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 scp_adsp clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 9b09e7f640d1..058ff55468a2 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -88,5 +88,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_CCUSYS) += clk-mt8195-ccu.o
 obj-$(CONFIG_COMMON_CLK_MT8195_IMGSYS) += clk-mt8195-img.o
 obj-$(CONFIG_COMMON_CLK_MT8195_IPESYS) += clk-mt8195-ipe.o
 obj-$(CONFIG_COMMON_CLK_MT8195_MFGCFG) += clk-mt8195-mfg.o
+obj-$(CONFIG_COMMON_CLK_MT8195_SCP_ADSP) += clk-mt8195-scp_adsp.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-scp_adsp.c b/drivers/clk/mediatek/clk-mt8195-scp_adsp.c
new file mode 100644
index 000000000000..2ecf90cabadb
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-scp_adsp.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static const struct mtk_gate_regs scp_adsp_cg_regs = {
+	.set_ofs = 0x180,
+	.clr_ofs = 0x180,
+	.sta_ofs = 0x180,
+};
+
+#define GATE_SCP_ADSP(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &scp_adsp_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
+
+static const struct mtk_gate scp_adsp_clks[] = {
+	GATE_SCP_ADSP(CLK_SCP_ADSP_AUDIODSP, "scp_adsp_audiodsp", "adsp_sel", 0),
+};
+
+static const struct mtk_clk_desc scp_adsp_desc = {
+	.clks = scp_adsp_clks,
+	.num_clks = ARRAY_SIZE(scp_adsp_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8195_scp_adsp[] = {
+	{
+		.compatible = "mediatek,mt8195-scp_adsp",
+		.data = &scp_adsp_desc,
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver clk_mt8195_scp_adsp_drv = {
+	.probe = mtk_clk_simple_probe,
+	.driver = {
+		.name = "clk-mt8195-scp_adsp",
+		.of_match_table = of_match_clk_mt8195_scp_adsp,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_scp_adsp_drv);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 13/22] clk: mediatek: Add MT8195 nnasys clock support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (11 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 12/22] clk: mediatek: Add MT8195 scp adsp " Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-07-09  8:24   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 14/22] clk: mediatek: Add MT8195 vdecsys " Chun-Jie Chen
                   ` (8 subsequent siblings)
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 nnasys clock provider

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig          |   6 ++
 drivers/clk/mediatek/Makefile         |   1 +
 drivers/clk/mediatek/clk-mt8195-nna.c | 128 ++++++++++++++++++++++++++
 3 files changed, 135 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-nna.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 7cb745d47770..d34517728f4a 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -636,6 +636,12 @@ config COMMON_CLK_MT8195_SCP_ADSP
 	help
 	  This driver supports MediaTek MT8195 scp_adsp clocks.
 
+config COMMON_CLK_MT8195_NNASYS
+	bool "Clock driver for MediaTek MT8195 nnasys"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 nnasys clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 058ff55468a2..49e585a7ac8e 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -89,5 +89,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_IMGSYS) += clk-mt8195-img.o
 obj-$(CONFIG_COMMON_CLK_MT8195_IPESYS) += clk-mt8195-ipe.o
 obj-$(CONFIG_COMMON_CLK_MT8195_MFGCFG) += clk-mt8195-mfg.o
 obj-$(CONFIG_COMMON_CLK_MT8195_SCP_ADSP) += clk-mt8195-scp_adsp.o
+obj-$(CONFIG_COMMON_CLK_MT8195_NNASYS) += clk-mt8195-nna.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-nna.c b/drivers/clk/mediatek/clk-mt8195-nna.c
new file mode 100644
index 000000000000..4210c6cf5ef4
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-nna.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static const struct mtk_gate_regs nna0_cg_regs = {
+	.set_ofs = 0x104,
+	.clr_ofs = 0x104,
+	.sta_ofs = 0x104,
+};
+
+static const struct mtk_gate_regs nna1_cg_regs = {
+	.set_ofs = 0x110,
+	.clr_ofs = 0x110,
+	.sta_ofs = 0x110,
+};
+
+static const struct mtk_gate_regs nna2_cg_regs = {
+	.set_ofs = 0x90,
+	.clr_ofs = 0x90,
+	.sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs nna3_cg_regs = {
+	.set_ofs = 0x94,
+	.clr_ofs = 0x94,
+	.sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs nna4_cg_regs = {
+	.set_ofs = 0x98,
+	.clr_ofs = 0x98,
+	.sta_ofs = 0x98,
+};
+
+static const struct mtk_gate_regs nna5_cg_regs = {
+	.set_ofs = 0x9c,
+	.clr_ofs = 0x9c,
+	.sta_ofs = 0x9c,
+};
+
+static const struct mtk_gate_regs nna6_cg_regs = {
+	.set_ofs = 0xa0,
+	.clr_ofs = 0xa0,
+	.sta_ofs = 0xa0,
+};
+
+static const struct mtk_gate_regs nna7_cg_regs = {
+	.set_ofs = 0xa4,
+	.clr_ofs = 0xa4,
+	.sta_ofs = 0xa4,
+};
+
+#define GATE_NNA0(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &nna0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_NNA1(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &nna1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_NNA2(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &nna2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_NNA3(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &nna3_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_NNA4(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &nna4_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_NNA5(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &nna5_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_NNA6(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &nna6_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_NNA7(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &nna7_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+static const struct mtk_gate nna_clks[] = {
+	/* NNA0 */
+	GATE_NNA0(CLK_NNA_F26M, "nna_f26m", "clk26m", 0),
+	/* NNA1 */
+	GATE_NNA1(CLK_NNA_AXI, "nna_axi", "axi_sel", 0),
+	/* NNA2 */
+	GATE_NNA2(CLK_NNA_NNA0, "nna_nna0", "nna0_sel", 0),
+	/* NNA3 */
+	GATE_NNA3(CLK_NNA_NNA1, "nna_nna1", "nna0_sel", 0),
+	/* NNA4 */
+	GATE_NNA4(CLK_NNA_NNA0_EMI, "nna_nna0_emi", "mem_466m", 0),
+	GATE_NNA4(CLK_NNA_CKGEN_MEM, "nna_ckgen_mem", "mem_466m", 4),
+	/* NNA5 */
+	GATE_NNA5(CLK_NNA_NNA1_EMI, "nna_nna1_emi", "mem_466m", 0),
+	/* NNA6 */
+	GATE_NNA6(CLK_NNA_NNA0_AXI, "nna_nna0_axi", "axi_sel", 0),
+	/* NNA7 */
+	GATE_NNA7(CLK_NNA_NNA1_AXI, "nna_nna1_axi", "axi_sel", 0),
+};
+
+static const struct mtk_clk_desc nna_desc = {
+	.clks = nna_clks,
+	.num_clks = ARRAY_SIZE(nna_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8195_nna[] = {
+	{
+		.compatible = "mediatek,mt8195-nnasys",
+		.data = &nna_desc,
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver clk_mt8195_nna_drv = {
+	.probe = mtk_clk_simple_probe,
+	.driver = {
+		.name = "clk-mt8195-nna",
+		.of_match_table = of_match_clk_mt8195_nna,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_nna_drv);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 14/22] clk: mediatek: Add MT8195 vdecsys clock support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (12 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 13/22] clk: mediatek: Add MT8195 nnasys " Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-07-09  8:40   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 15/22] clk: mediatek: Add MT8195 vdosys0 " Chun-Jie Chen
                   ` (7 subsequent siblings)
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 vdecsys clock providers

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig           |   6 ++
 drivers/clk/mediatek/Makefile          |   1 +
 drivers/clk/mediatek/clk-mt8195-vdec.c | 106 +++++++++++++++++++++++++
 3 files changed, 113 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-vdec.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index d34517728f4a..b7881b8ebb23 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -642,6 +642,12 @@ config COMMON_CLK_MT8195_NNASYS
 	help
 	  This driver supports MediaTek MT8195 nnasys clocks.
 
+config COMMON_CLK_MT8195_VDECSYS
+	bool "Clock driver for MediaTek MT8195 vdecsys"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 vdecsys clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 49e585a7ac8e..9acfa705f1de 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -90,5 +90,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_IPESYS) += clk-mt8195-ipe.o
 obj-$(CONFIG_COMMON_CLK_MT8195_MFGCFG) += clk-mt8195-mfg.o
 obj-$(CONFIG_COMMON_CLK_MT8195_SCP_ADSP) += clk-mt8195-scp_adsp.o
 obj-$(CONFIG_COMMON_CLK_MT8195_NNASYS) += clk-mt8195-nna.o
+obj-$(CONFIG_COMMON_CLK_MT8195_VDECSYS) += clk-mt8195-vdec.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-vdec.c b/drivers/clk/mediatek/clk-mt8195-vdec.c
new file mode 100644
index 000000000000..9ab84e75e1a0
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-vdec.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static const struct mtk_gate_regs vdec0_cg_regs = {
+	.set_ofs = 0x0,
+	.clr_ofs = 0x4,
+	.sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs vdec1_cg_regs = {
+	.set_ofs = 0x200,
+	.clr_ofs = 0x204,
+	.sta_ofs = 0x200,
+};
+
+static const struct mtk_gate_regs vdec2_cg_regs = {
+	.set_ofs = 0x8,
+	.clr_ofs = 0xc,
+	.sta_ofs = 0x8,
+};
+
+#define GATE_VDEC0(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+#define GATE_VDEC1(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+#define GATE_VDEC2(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+static const struct mtk_gate vdec_clks[] = {
+	/* VDEC0 */
+	GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec", "vdec_sel", 0),
+	/* VDEC1 */
+	GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat", "vdec_sel", 0),
+	/* VDEC2 */
+	GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1", "vdec_sel", 0),
+};
+
+static const struct mtk_gate vdec_core1_clks[] = {
+	/* VDEC0 */
+	GATE_VDEC0(CLK_VDEC_CORE1_VDEC, "vdec_core1_vdec", "vdec_sel", 0),
+	/* VDEC1 */
+	GATE_VDEC1(CLK_VDEC_CORE1_LAT, "vdec_core1_lat", "vdec_sel", 0),
+	/* VDEC2 */
+	GATE_VDEC2(CLK_VDEC_CORE1_LARB1, "vdec_core1_larb1", "vdec_sel", 0),
+};
+
+static const struct mtk_gate vdec_soc_clks[] = {
+	/* VDEC0 */
+	GATE_VDEC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec", "vdec_sel", 0),
+	/* VDEC1 */
+	GATE_VDEC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat", "vdec_sel", 0),
+	/* VDEC2 */
+	GATE_VDEC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1", "vdec_sel", 0),
+};
+
+static const struct mtk_clk_desc vdec_desc = {
+	.clks = vdec_clks,
+	.num_clks = ARRAY_SIZE(vdec_clks),
+};
+
+static const struct mtk_clk_desc vdec_core1_desc = {
+	.clks = vdec_core1_clks,
+	.num_clks = ARRAY_SIZE(vdec_core1_clks),
+};
+
+static const struct mtk_clk_desc vdec_soc_desc = {
+	.clks = vdec_soc_clks,
+	.num_clks = ARRAY_SIZE(vdec_soc_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8195_vdec[] = {
+	{
+		.compatible = "mediatek,mt8195-vdecsys",
+		.data = &vdec_desc,
+	}, {
+		.compatible = "mediatek,mt8195-vdecsys_core1",
+		.data = &vdec_core1_desc,
+	}, {
+		.compatible = "mediatek,mt8195-vdecsys_soc",
+		.data = &vdec_soc_desc,
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver clk_mt8195_vdec_drv = {
+	.probe = mtk_clk_simple_probe,
+	.driver = {
+		.name = "clk-mt8195-vdec",
+		.of_match_table = of_match_clk_mt8195_vdec,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_vdec_drv);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 15/22] clk: mediatek: Add MT8195 vdosys0 clock support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (13 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 14/22] clk: mediatek: Add MT8195 vdecsys " Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-07-09  8:51   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 16/22] clk: mediatek: Add MT8195 vdosys1 " Chun-Jie Chen
                   ` (6 subsequent siblings)
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 vdosys0 clock provider

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig           |   6 ++
 drivers/clk/mediatek/Makefile          |   1 +
 drivers/clk/mediatek/clk-mt8195-vdo0.c | 114 +++++++++++++++++++++++++
 3 files changed, 121 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-vdo0.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index b7881b8ebb23..6602f9ba13c7 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -648,6 +648,12 @@ config COMMON_CLK_MT8195_VDECSYS
 	help
 	  This driver supports MediaTek MT8195 vdecsys clocks.
 
+config COMMON_CLK_MT8195_VDOSYS0
+	bool "Clock driver for MediaTek MT8195 vdosys0"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 vdosys0 clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 9acfa705f1de..6aa1ba00342a 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -91,5 +91,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_MFGCFG) += clk-mt8195-mfg.o
 obj-$(CONFIG_COMMON_CLK_MT8195_SCP_ADSP) += clk-mt8195-scp_adsp.o
 obj-$(CONFIG_COMMON_CLK_MT8195_NNASYS) += clk-mt8195-nna.o
 obj-$(CONFIG_COMMON_CLK_MT8195_VDECSYS) += clk-mt8195-vdec.o
+obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS0) += clk-mt8195-vdo0.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/clk-mt8195-vdo0.c
new file mode 100644
index 000000000000..4a34ccb0beed
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static const struct mtk_gate_regs vdo00_cg_regs = {
+	.set_ofs = 0x104,
+	.clr_ofs = 0x108,
+	.sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs vdo01_cg_regs = {
+	.set_ofs = 0x114,
+	.clr_ofs = 0x118,
+	.sta_ofs = 0x110,
+};
+
+static const struct mtk_gate_regs vdo02_cg_regs = {
+	.set_ofs = 0x124,
+	.clr_ofs = 0x128,
+	.sta_ofs = 0x120,
+};
+
+#define GATE_VDO00(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &vdo00_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_VDO01(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &vdo01_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_VDO02(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &vdo02_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate vdo0_clks[] = {
+	/* VDO00 */
+	GATE_VDO00(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "vpp_sel", 0),
+	GATE_VDO00(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0", "vpp_sel", 2),
+	GATE_VDO00(CLK_VDO0_DISP_COLOR1, "vdo0_disp_color1", "vpp_sel", 3),
+	GATE_VDO00(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0", "vpp_sel", 4),
+	GATE_VDO00(CLK_VDO0_DISP_CCORR1, "vdo0_disp_ccorr1", "vpp_sel", 5),
+	GATE_VDO00(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0", "vpp_sel", 6),
+	GATE_VDO00(CLK_VDO0_DISP_AAL1, "vdo0_disp_aal1", "vpp_sel", 7),
+	GATE_VDO00(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0", "vpp_sel", 8),
+	GATE_VDO00(CLK_VDO0_DISP_GAMMA1, "vdo0_disp_gamma1", "vpp_sel", 9),
+	GATE_VDO00(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0", "vpp_sel", 10),
+	GATE_VDO00(CLK_VDO0_DISP_DITHER1, "vdo0_disp_dither1", "vpp_sel", 11),
+	GATE_VDO00(CLK_VDO0_DISP_OVL1, "vdo0_disp_ovl1", "vpp_sel", 16),
+	GATE_VDO00(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0", "vpp_sel", 17),
+	GATE_VDO00(CLK_VDO0_DISP_WDMA1, "vdo0_disp_wdma1", "vpp_sel", 18),
+	GATE_VDO00(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0", "vpp_sel", 19),
+	GATE_VDO00(CLK_VDO0_DISP_RDMA1, "vdo0_disp_rdma1", "vpp_sel", 20),
+	GATE_VDO00(CLK_VDO0_DSI0, "vdo0_dsi0", "vpp_sel", 21),
+	GATE_VDO00(CLK_VDO0_DSI1, "vdo0_dsi1", "vpp_sel", 22),
+	GATE_VDO00(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0", "vpp_sel", 23),
+	GATE_VDO00(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0", "vpp_sel", 24),
+	GATE_VDO00(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "vpp_sel", 25),
+	GATE_VDO00(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0", "vpp_sel", 26),
+	GATE_VDO00(CLK_VDO0_DISP_IL_ROT0, "vdo0_disp_il_rot0", "vpp_sel", 27),
+	GATE_VDO00(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "vpp_sel", 28),
+	GATE_VDO00(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0", "vpp_sel", 29),
+	GATE_VDO00(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1", "vpp_sel", 30),
+	/* VDO01 */
+	GATE_VDO01(CLK_VDO0_DL_ASYNC0, "vdo0_dl_async0", "vpp_sel", 0),
+	GATE_VDO01(CLK_VDO0_DL_ASYNC1, "vdo0_dl_async1", "vpp_sel", 1),
+	GATE_VDO01(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2", "vpp_sel", 2),
+	GATE_VDO01(CLK_VDO0_DL_ASYNC3, "vdo0_dl_async3", "vpp_sel", 3),
+	GATE_VDO01(CLK_VDO0_DL_ASYNC4, "vdo0_dl_async4", "vpp_sel", 4),
+	GATE_VDO01(CLK_VDO0_DISP_MONITOR0, "vdo0_disp_monitor0", "vpp_sel", 5),
+	GATE_VDO01(CLK_VDO0_DISP_MONITOR1, "vdo0_disp_monitor1", "vpp_sel", 6),
+	GATE_VDO01(CLK_VDO0_DISP_MONITOR2, "vdo0_disp_monitor2", "vpp_sel", 7),
+	GATE_VDO01(CLK_VDO0_DISP_MONITOR3, "vdo0_disp_monitor3", "vpp_sel", 8),
+	GATE_VDO01(CLK_VDO0_DISP_MONITOR4, "vdo0_disp_monitor4", "vpp_sel", 9),
+	GATE_VDO01(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "vpp_sel", 10),
+	GATE_VDO01(CLK_VDO0_SMI_COMMON, "vdo0_smi_common", "vpp_sel", 11),
+	GATE_VDO01(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "vpp_sel", 12),
+	GATE_VDO01(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu", "vpp_sel", 13),
+	GATE_VDO01(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "vpp_sel", 14),
+	GATE_VDO01(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "vpp_sel", 15),
+	/* VDO02 */
+	GATE_VDO02(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "dsi_occ_sel", 0),
+	GATE_VDO02(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "dsi_occ_sel", 8),
+	GATE_VDO02(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf", "edp_sel", 16),
+};
+
+static const struct mtk_clk_desc vdo0_desc = {
+	.clks = vdo0_clks,
+	.num_clks = ARRAY_SIZE(vdo0_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8195_vdo0[] = {
+	{
+		.compatible = "mediatek,mt8195-vdosys0",
+		.data = &vdo0_desc,
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver clk_mt8195_vdo0_drv = {
+	.probe = mtk_clk_simple_probe,
+	.driver = {
+		.name = "clk-mt8195-vdo0",
+		.of_match_table = of_match_clk_mt8195_vdo0,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_vdo0_drv);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 16/22] clk: mediatek: Add MT8195 vdosys1 clock support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (14 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 15/22] clk: mediatek: Add MT8195 vdosys0 " Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-07-09  9:30   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 17/22] clk: mediatek: Add MT8195 vencsys " Chun-Jie Chen
                   ` (5 subsequent siblings)
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 vdosys1 clock provider

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig           |   6 ++
 drivers/clk/mediatek/Makefile          |   1 +
 drivers/clk/mediatek/clk-mt8195-vdo1.c | 131 +++++++++++++++++++++++++
 3 files changed, 138 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-vdo1.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 6602f9ba13c7..1e89c68f6c6c 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -654,6 +654,12 @@ config COMMON_CLK_MT8195_VDOSYS0
 	help
 	  This driver supports MediaTek MT8195 vdosys0 clocks.
 
+config COMMON_CLK_MT8195_VDOSYS1
+	bool "Clock driver for MediaTek MT8195 vdosys1"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 vdosys1 clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 6aa1ba00342a..76c0fa837cb0 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -92,5 +92,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_SCP_ADSP) += clk-mt8195-scp_adsp.o
 obj-$(CONFIG_COMMON_CLK_MT8195_NNASYS) += clk-mt8195-nna.o
 obj-$(CONFIG_COMMON_CLK_MT8195_VDECSYS) += clk-mt8195-vdec.o
 obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS0) += clk-mt8195-vdo0.o
+obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS1) += clk-mt8195-vdo1.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/clk-mt8195-vdo1.c
new file mode 100644
index 000000000000..4d16f2e9c03a
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static const struct mtk_gate_regs vdo10_cg_regs = {
+	.set_ofs = 0x104,
+	.clr_ofs = 0x108,
+	.sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs vdo11_cg_regs = {
+	.set_ofs = 0x124,
+	.clr_ofs = 0x128,
+	.sta_ofs = 0x120,
+};
+
+static const struct mtk_gate_regs vdo12_cg_regs = {
+	.set_ofs = 0x134,
+	.clr_ofs = 0x138,
+	.sta_ofs = 0x130,
+};
+
+static const struct mtk_gate_regs vdo13_cg_regs = {
+	.set_ofs = 0x144,
+	.clr_ofs = 0x148,
+	.sta_ofs = 0x140,
+};
+
+#define GATE_VDO10(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &vdo10_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_VDO11(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &vdo11_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_VDO12(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &vdo12_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_VDO13(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &vdo13_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate vdo1_clks[] = {
+	/* VDO10 */
+	GATE_VDO10(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2", "vpp_sel", 0),
+	GATE_VDO10(CLK_VDO1_SMI_LARB3, "vdo1_smi_larb3", "vpp_sel", 1),
+	GATE_VDO10(CLK_VDO1_GALS, "vdo1_gals", "vpp_sel", 2),
+	GATE_VDO10(CLK_VDO1_FAKE_ENG0, "vdo1_fake_eng0", "vpp_sel", 3),
+	GATE_VDO10(CLK_VDO1_FAKE_ENG, "vdo1_fake_eng", "vpp_sel", 4),
+	GATE_VDO10(CLK_VDO1_MDP_RDMA0, "vdo1_mdp_rdma0", "vpp_sel", 5),
+	GATE_VDO10(CLK_VDO1_MDP_RDMA1, "vdo1_mdp_rdma1", "vpp_sel", 6),
+	GATE_VDO10(CLK_VDO1_MDP_RDMA2, "vdo1_mdp_rdma2", "vpp_sel", 7),
+	GATE_VDO10(CLK_VDO1_MDP_RDMA3, "vdo1_mdp_rdma3", "vpp_sel", 8),
+	GATE_VDO10(CLK_VDO1_VPP_MERGE0, "vdo1_vpp_merge0", "vpp_sel", 9),
+	GATE_VDO10(CLK_VDO1_VPP_MERGE1, "vdo1_vpp_merge1", "vpp_sel", 10),
+	GATE_VDO10(CLK_VDO1_VPP_MERGE2, "vdo1_vpp_merge2", "vpp_sel", 11),
+	GATE_VDO10(CLK_VDO1_VPP_MERGE3, "vdo1_vpp_merge3", "vpp_sel", 12),
+	GATE_VDO10(CLK_VDO1_VPP_MERGE4, "vdo1_vpp_merge4", "vpp_sel", 13),
+	GATE_VDO10(CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC, "vdo1_vpp2_to_vdo1_dl_async", "vpp_sel", 14),
+	GATE_VDO10(CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC, "vdo1_vpp3_to_vdo1_dl_async", "vpp_sel", 15),
+	GATE_VDO10(CLK_VDO1_DISP_MUTEX, "vdo1_disp_mutex", "vpp_sel", 16),
+	GATE_VDO10(CLK_VDO1_MDP_RDMA4, "vdo1_mdp_rdma4", "vpp_sel", 17),
+	GATE_VDO10(CLK_VDO1_MDP_RDMA5, "vdo1_mdp_rdma5", "vpp_sel", 18),
+	GATE_VDO10(CLK_VDO1_MDP_RDMA6, "vdo1_mdp_rdma6", "vpp_sel", 19),
+	GATE_VDO10(CLK_VDO1_MDP_RDMA7, "vdo1_mdp_rdma7", "vpp_sel", 20),
+	GATE_VDO10(CLK_VDO1_DP_INTF0_MM, "vdo1_dp_intf0_mm", "vpp_sel", 21),
+	GATE_VDO10(CLK_VDO1_DPI0_MM, "vdo1_dpi0_mm", "vpp_sel", 22),
+	GATE_VDO10(CLK_VDO1_DPI1_MM, "vdo1_dpi1_mm", "vpp_sel", 23),
+	GATE_VDO10(CLK_VDO1_DISP_MONITOR, "vdo1_disp_monitor", "vpp_sel", 24),
+	GATE_VDO10(CLK_VDO1_MERGE0_DL_ASYNC, "vdo1_merge0_dl_async", "vpp_sel", 25),
+	GATE_VDO10(CLK_VDO1_MERGE1_DL_ASYNC, "vdo1_merge1_dl_async", "vpp_sel", 26),
+	GATE_VDO10(CLK_VDO1_MERGE2_DL_ASYNC, "vdo1_merge2_dl_async", "vpp_sel", 27),
+	GATE_VDO10(CLK_VDO1_MERGE3_DL_ASYNC, "vdo1_merge3_dl_async", "vpp_sel", 28),
+	GATE_VDO10(CLK_VDO1_MERGE4_DL_ASYNC, "vdo1_merge4_dl_async", "vpp_sel", 29),
+	GATE_VDO10(CLK_VDO1_VDO0_DSC_TO_VDO1_DL_ASYNC, "vdo1_vdo0_dsc_to_vdo1_dl_async",
+		"vpp_sel", 30),
+	GATE_VDO10(CLK_VDO1_VDO0_MERGE_TO_VDO1_DL_ASYNC, "vdo1_vdo0_merge_to_vdo1_dl_async",
+		"vpp_sel", 31),
+	/* VDO11 */
+	GATE_VDO11(CLK_VDO1_HDR_VDO_FE0, "vdo1_hdr_vdo_fe0", "vpp_sel", 0),
+	GATE_VDO11(CLK_VDO1_HDR_GFX_FE0, "vdo1_hdr_gfx_fe0", "vpp_sel", 1),
+	GATE_VDO11(CLK_VDO1_HDR_VDO_BE, "vdo1_hdr_vdo_be", "vpp_sel", 2),
+	GATE_VDO11(CLK_VDO1_HDR_VDO_FE1, "vdo1_hdr_vdo_fe1", "vpp_sel", 16),
+	GATE_VDO11(CLK_VDO1_HDR_GFX_FE1, "vdo1_hdr_gfx_fe1", "vpp_sel", 17),
+	GATE_VDO11(CLK_VDO1_DISP_MIXER, "vdo1_disp_mixer", "vpp_sel", 18),
+	GATE_VDO11(CLK_VDO1_HDR_VDO_FE0_DL_ASYNC, "vdo1_hdr_vdo_fe0_dl_async", "vpp_sel", 19),
+	GATE_VDO11(CLK_VDO1_HDR_VDO_FE1_DL_ASYNC, "vdo1_hdr_vdo_fe1_dl_async", "vpp_sel", 20),
+	GATE_VDO11(CLK_VDO1_HDR_GFX_FE0_DL_ASYNC, "vdo1_hdr_gfx_fe0_dl_async", "vpp_sel", 21),
+	GATE_VDO11(CLK_VDO1_HDR_GFX_FE1_DL_ASYNC, "vdo1_hdr_gfx_fe1_dl_async", "vpp_sel", 22),
+	GATE_VDO11(CLK_VDO1_HDR_VDO_BE_DL_ASYNC, "vdo1_hdr_vdo_be_dl_async", "vpp_sel", 23),
+	/* VDO12 */
+	GATE_VDO12(CLK_VDO1_DPI0, "vdo1_dpi0", "vpp_sel", 0),
+	GATE_VDO12(CLK_VDO1_DISP_MONITOR_DPI0, "vdo1_disp_monitor_dpi0", "vpp_sel", 1),
+	GATE_VDO12(CLK_VDO1_DPI1, "vdo1_dpi1", "vpp_sel", 8),
+	GATE_VDO12(CLK_VDO1_DISP_MONITOR_DPI1, "vdo1_disp_monitor_dpi1", "vpp_sel", 9),
+	GATE_VDO12(CLK_VDO1_DPINTF, "vdo1_dpintf", "vpp_sel", 16),
+	GATE_VDO12(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf", "vpp_sel", 17),
+	/* VDO13 */
+	GATE_VDO13(CLK_VDO1_26M_SLOW, "vdo1_26m_slow", "clk26m", 8),
+};
+
+static const struct mtk_clk_desc vdo1_desc = {
+	.clks = vdo1_clks,
+	.num_clks = ARRAY_SIZE(vdo1_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8195_vdo1[] = {
+	{
+		.compatible = "mediatek,mt8195-vdosys1",
+		.data = &vdo1_desc,
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver clk_mt8195_vdo1_drv = {
+	.probe = mtk_clk_simple_probe,
+	.driver = {
+		.name = "clk-mt8195-vdo1",
+		.of_match_table = of_match_clk_mt8195_vdo1,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_vdo1_drv);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 17/22] clk: mediatek: Add MT8195 vencsys clock support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (15 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 16/22] clk: mediatek: Add MT8195 vdosys1 " Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-07-09 10:26   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 18/22] clk: mediatek: Add MT8195 vppsys0 " Chun-Jie Chen
                   ` (4 subsequent siblings)
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 vencsys clock providers

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig           |  6 +++
 drivers/clk/mediatek/Makefile          |  1 +
 drivers/clk/mediatek/clk-mt8195-venc.c | 71 ++++++++++++++++++++++++++
 3 files changed, 78 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-venc.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 1e89c68f6c6c..3352686d98cf 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -660,6 +660,12 @@ config COMMON_CLK_MT8195_VDOSYS1
 	help
 	  This driver supports MediaTek MT8195 vdosys1 clocks.
 
+config COMMON_CLK_MT8195_VENCSYS
+	bool "Clock driver for MediaTek MT8195 vencsys"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 vencsys clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 76c0fa837cb0..76a6b404e34b 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -93,5 +93,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_NNASYS) += clk-mt8195-nna.o
 obj-$(CONFIG_COMMON_CLK_MT8195_VDECSYS) += clk-mt8195-vdec.o
 obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS0) += clk-mt8195-vdo0.o
 obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS1) += clk-mt8195-vdo1.o
+obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-venc.c b/drivers/clk/mediatek/clk-mt8195-venc.c
new file mode 100644
index 000000000000..410ca69d5759
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-venc.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static const struct mtk_gate_regs venc_cg_regs = {
+	.set_ofs = 0x4,
+	.clr_ofs = 0x8,
+	.sta_ofs = 0x0,
+};
+
+#define GATE_VENC(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+static const struct mtk_gate venc_clks[] = {
+	GATE_VENC(CLK_VENC_LARB, "venc_larb", "venc_sel", 0),
+	GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4),
+	GATE_VENC(CLK_VENC_JPGENC, "venc_jpgenc", "venc_sel", 8),
+	GATE_VENC(CLK_VENC_JPGDEC, "venc_jpgdec", "venc_sel", 12),
+	GATE_VENC(CLK_VENC_JPGDEC_C1, "venc_jpgdec_c1", "venc_sel", 16),
+	GATE_VENC(CLK_VENC_GALS, "venc_gals", "venc_sel", 28),
+};
+
+static const struct mtk_gate venc_core1_clks[] = {
+	GATE_VENC(CLK_VENC_CORE1_LARB, "venc_core1_larb", "venc_sel", 0),
+	GATE_VENC(CLK_VENC_CORE1_VENC, "venc_core1_venc", "venc_sel", 4),
+	GATE_VENC(CLK_VENC_CORE1_JPGENC, "venc_core1_jpgenc", "venc_sel", 8),
+	GATE_VENC(CLK_VENC_CORE1_JPGDEC, "venc_core1_jpgdec", "venc_sel", 12),
+	GATE_VENC(CLK_VENC_CORE1_JPGDEC_C1, "venc_core1_jpgdec_c1", "venc_sel", 16),
+	GATE_VENC(CLK_VENC_CORE1_GALS, "venc_core1_gals", "venc_sel", 28),
+};
+
+static const struct mtk_clk_desc venc_desc = {
+	.clks = venc_clks,
+	.num_clks = ARRAY_SIZE(venc_clks),
+};
+
+static const struct mtk_clk_desc venc_core1_desc = {
+	.clks = venc_core1_clks,
+	.num_clks = ARRAY_SIZE(venc_core1_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8195_venc[] = {
+	{
+		.compatible = "mediatek,mt8195-vencsys",
+		.data = &venc_desc,
+	}, {
+		.compatible = "mediatek,mt8195-vencsys_core1",
+		.data = &venc_core1_desc,
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver clk_mt8195_venc_drv = {
+	.probe = mtk_clk_simple_probe,
+	.driver = {
+		.name = "clk-mt8195-venc",
+		.of_match_table = of_match_clk_mt8195_venc,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_venc_drv);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 18/22] clk: mediatek: Add MT8195 vppsys0 clock support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (16 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 17/22] clk: mediatek: Add MT8195 vencsys " Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-07-09 10:38   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 19/22] clk: mediatek: Add MT8195 vppsys1 " Chun-Jie Chen
                   ` (3 subsequent siblings)
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 vppsys0 clock provider

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig           |   6 ++
 drivers/clk/mediatek/Makefile          |   1 +
 drivers/clk/mediatek/clk-mt8195-vpp0.c | 112 +++++++++++++++++++++++++
 3 files changed, 119 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-vpp0.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 3352686d98cf..2deef026fbb4 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -666,6 +666,12 @@ config COMMON_CLK_MT8195_VENCSYS
 	help
 	  This driver supports MediaTek MT8195 vencsys clocks.
 
+config COMMON_CLK_MT8195_VPPSYS0
+	bool "Clock driver for MediaTek MT8195 vppsys0"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 vppsys0 clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 76a6b404e34b..34cd7f2c71ac 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -94,5 +94,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VDECSYS) += clk-mt8195-vdec.o
 obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS0) += clk-mt8195-vdo0.o
 obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS1) += clk-mt8195-vdo1.o
 obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
+obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS0) += clk-mt8195-vpp0.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-vpp0.c b/drivers/clk/mediatek/clk-mt8195-vpp0.c
new file mode 100644
index 000000000000..cecd8fab7b7e
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-vpp0.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static const struct mtk_gate_regs vpp00_cg_regs = {
+	.set_ofs = 0x24,
+	.clr_ofs = 0x28,
+	.sta_ofs = 0x20,
+};
+
+static const struct mtk_gate_regs vpp01_cg_regs = {
+	.set_ofs = 0x30,
+	.clr_ofs = 0x34,
+	.sta_ofs = 0x2c,
+};
+
+static const struct mtk_gate_regs vpp02_cg_regs = {
+	.set_ofs = 0x3c,
+	.clr_ofs = 0x40,
+	.sta_ofs = 0x38,
+};
+
+#define GATE_VPP00(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &vpp00_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_VPP01(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &vpp01_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_VPP02(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &vpp02_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate vpp0_clks[] = {
+	/* VPP00 */
+	GATE_VPP00(CLK_VPP0_MDP_FG, "vpp0_mdp_fg", "vpp_sel", 1),
+	GATE_VPP00(CLK_VPP0_STITCH, "vpp0_stitch", "vpp_sel", 2),
+	GATE_VPP00(CLK_VPP0_PADDING, "vpp0_padding", "vpp_sel", 7),
+	GATE_VPP00(CLK_VPP0_MDP_TCC, "vpp0_mdp_tcc", "vpp_sel", 8),
+	GATE_VPP00(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx", "vpp_sel", 10),
+	GATE_VPP00(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx", "vpp_sel", 11),
+	GATE_VPP00(CLK_VPP0_MUTEX, "vpp0_mutex", "vpp_sel", 13),
+	GATE_VPP00(CLK_VPP0_VPP02VPP1_RELAY, "vpp0_vpp02vpp1_relay", "vpp_sel", 14),
+	GATE_VPP00(CLK_VPP0_VPP12VPP0_ASYNC, "vpp0_vpp12vpp0_async", "vpp_sel", 15),
+	GATE_VPP00(CLK_VPP0_MMSYSRAM_TOP, "vpp0_mmsysram_top", "vpp_sel", 16),
+	GATE_VPP00(CLK_VPP0_MDP_AAL, "vpp0_mdp_aal", "vpp_sel", 17),
+	GATE_VPP00(CLK_VPP0_MDP_RSZ, "vpp0_mdp_rsz", "vpp_sel", 18),
+	/* VPP01 */
+	GATE_VPP01(CLK_VPP0_SMI_COMMON, "vpp0_smi_common", "vpp_sel", 0),
+	GATE_VPP01(CLK_VPP0_GALS_VDO0_LARB0, "vpp0_gals_vdo0_larb0", "vpp_sel", 1),
+	GATE_VPP01(CLK_VPP0_GALS_VDO0_LARB1, "vpp0_gals_vdo0_larb1", "vpp_sel", 2),
+	GATE_VPP01(CLK_VPP0_GALS_VENCSYS, "vpp0_gals_vencsys", "vpp_sel", 3),
+	GATE_VPP01(CLK_VPP0_GALS_VENCSYS_CORE1, "vpp0_gals_vencsys_core1", "vpp_sel", 4),
+	GATE_VPP01(CLK_VPP0_GALS_INFRA, "vpp0_gals_infra", "vpp_sel", 5),
+	GATE_VPP01(CLK_VPP0_GALS_CAMSYS, "vpp0_gals_camsys", "vpp_sel", 6),
+	GATE_VPP01(CLK_VPP0_GALS_VPP1_LARB5, "vpp0_gals_vpp1_larb5", "vpp_sel", 7),
+	GATE_VPP01(CLK_VPP0_GALS_VPP1_LARB6, "vpp0_gals_vpp1_larb6", "vpp_sel", 8),
+	GATE_VPP01(CLK_VPP0_SMI_REORDER, "vpp0_smi_reorder", "vpp_sel", 9),
+	GATE_VPP01(CLK_VPP0_SMI_IOMMU, "vpp0_smi_iommu", "vpp_sel", 10),
+	GATE_VPP01(CLK_VPP0_GALS_IMGSYS_CAMSYS, "vpp0_gals_imgsys_camsys", "vpp_sel", 11),
+	GATE_VPP01(CLK_VPP0_MDP_RDMA, "vpp0_mdp_rdma", "vpp_sel", 12),
+	GATE_VPP01(CLK_VPP0_MDP_WROT, "vpp0_mdp_wrot", "vpp_sel", 13),
+	GATE_VPP01(CLK_VPP0_GALS_EMI0_EMI1, "vpp0_gals_emi0_emi1", "vpp_sel", 16),
+	GATE_VPP01(CLK_VPP0_SMI_SUB_COMMON_REORDER, "vpp0_smi_sub_common_reorder", "vpp_sel", 17),
+	GATE_VPP01(CLK_VPP0_SMI_RSI, "vpp0_smi_rsi", "vpp_sel", 18),
+	GATE_VPP01(CLK_VPP0_SMI_COMMON_LARB4, "vpp0_smi_common_larb4", "vpp_sel", 19),
+	GATE_VPP01(CLK_VPP0_GALS_VDEC_VDEC_CORE1, "vpp0_gals_vdec_vdec_core1", "vpp_sel", 20),
+	GATE_VPP01(CLK_VPP0_GALS_VPP1_WPE, "vpp0_gals_vpp1_wpe", "vpp_sel", 21),
+	GATE_VPP01(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1, "vpp0_gals_vdo0_vdo1_vencsys_core1",
+		"vpp_sel", 22),
+	GATE_VPP01(CLK_VPP0_FAKE_ENG, "vpp0_fake_eng", "vpp_sel", 23),
+	GATE_VPP01(CLK_VPP0_MDP_HDR, "vpp0_mdp_hdr", "vpp_sel", 24),
+	GATE_VPP01(CLK_VPP0_MDP_TDSHP, "vpp0_mdp_tdshp", "vpp_sel", 25),
+	GATE_VPP01(CLK_VPP0_MDP_COLOR, "vpp0_mdp_color", "vpp_sel", 26),
+	GATE_VPP01(CLK_VPP0_MDP_OVL, "vpp0_mdp_ovl", "vpp_sel", 27),
+	/* VPP02 */
+	GATE_VPP02(CLK_VPP0_WARP0_RELAY, "vpp0_warp0_relay", "wpe_vpp_sel", 0),
+	GATE_VPP02(CLK_VPP0_WARP0_MDP_DL_ASYNC, "vpp0_warp0_mdp_dl_async", "wpe_vpp_sel", 1),
+	GATE_VPP02(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay", "wpe_vpp_sel", 2),
+	GATE_VPP02(CLK_VPP0_WARP1_MDP_DL_ASYNC, "vpp0_warp1_mdp_dl_async", "wpe_vpp_sel", 3),
+};
+
+static const struct mtk_clk_desc vpp0_desc = {
+	.clks = vpp0_clks,
+	.num_clks = ARRAY_SIZE(vpp0_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8195_vpp0[] = {
+	{
+		.compatible = "mediatek,mt8195-vppsys0",
+		.data = &vpp0_desc,
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver clk_mt8195_vpp0_drv = {
+	.probe = mtk_clk_simple_probe,
+	.driver = {
+		.name = "clk-mt8195-vpp0",
+		.of_match_table = of_match_clk_mt8195_vpp0,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_vpp0_drv);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 19/22] clk: mediatek: Add MT8195 vppsys1 clock support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (17 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 18/22] clk: mediatek: Add MT8195 vppsys0 " Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-07-09 10:45   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 20/22] clk: mediatek: Add MT8195 wpesys " Chun-Jie Chen
                   ` (2 subsequent siblings)
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 vppsys1 clock provider

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig           |   6 ++
 drivers/clk/mediatek/Makefile          |   1 +
 drivers/clk/mediatek/clk-mt8195-vpp1.c | 110 +++++++++++++++++++++++++
 3 files changed, 117 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-vpp1.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 2deef026fbb4..91b1c19da1ab 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -672,6 +672,12 @@ config COMMON_CLK_MT8195_VPPSYS0
 	help
 	  This driver supports MediaTek MT8195 vppsys0 clocks.
 
+config COMMON_CLK_MT8195_VPPSYS1
+	bool "Clock driver for MediaTek MT8195 vppsys1"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 vppsys1 clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 34cd7f2c71ac..fbf57473bb91 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -95,5 +95,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS0) += clk-mt8195-vdo0.o
 obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS1) += clk-mt8195-vdo1.o
 obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
 obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS0) += clk-mt8195-vpp0.o
+obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS1) += clk-mt8195-vpp1.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-vpp1.c b/drivers/clk/mediatek/clk-mt8195-vpp1.c
new file mode 100644
index 000000000000..0650ba86d5b6
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-vpp1.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static const struct mtk_gate_regs vpp10_cg_regs = {
+	.set_ofs = 0x104,
+	.clr_ofs = 0x108,
+	.sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs vpp11_cg_regs = {
+	.set_ofs = 0x114,
+	.clr_ofs = 0x118,
+	.sta_ofs = 0x110,
+};
+
+#define GATE_VPP10(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &vpp10_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_VPP11(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &vpp11_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate vpp1_clks[] = {
+	/* VPP10 */
+	GATE_VPP10(CLK_VPP1_SVPP1_MDP_OVL, "vpp1_svpp1_mdp_ovl", "vpp_sel", 0),
+	GATE_VPP10(CLK_VPP1_SVPP1_MDP_TCC, "vpp1_svpp1_mdp_tcc", "vpp_sel", 1),
+	GATE_VPP10(CLK_VPP1_SVPP1_MDP_WROT, "vpp1_svpp1_mdp_wrot", "vpp_sel", 2),
+	GATE_VPP10(CLK_VPP1_SVPP1_VPP_PAD, "vpp1_svpp1_vpp_pad", "vpp_sel", 3),
+	GATE_VPP10(CLK_VPP1_SVPP2_MDP_WROT, "vpp1_svpp2_mdp_wrot", "vpp_sel", 4),
+	GATE_VPP10(CLK_VPP1_SVPP2_VPP_PAD, "vpp1_svpp2_vpp_pad", "vpp_sel", 5),
+	GATE_VPP10(CLK_VPP1_SVPP3_MDP_WROT, "vpp1_svpp3_mdp_wrot", "vpp_sel", 6),
+	GATE_VPP10(CLK_VPP1_SVPP3_VPP_PAD, "vpp1_svpp3_vpp_pad", "vpp_sel", 7),
+	GATE_VPP10(CLK_VPP1_SVPP1_MDP_RDMA, "vpp1_svpp1_mdp_rdma", "vpp_sel", 8),
+	GATE_VPP10(CLK_VPP1_SVPP1_MDP_FG, "vpp1_svpp1_mdp_fg", "vpp_sel", 9),
+	GATE_VPP10(CLK_VPP1_SVPP2_MDP_RDMA, "vpp1_svpp2_mdp_rdma", "vpp_sel", 10),
+	GATE_VPP10(CLK_VPP1_SVPP2_MDP_FG, "vpp1_svpp2_mdp_fg", "vpp_sel", 11),
+	GATE_VPP10(CLK_VPP1_SVPP3_MDP_RDMA, "vpp1_svpp3_mdp_rdma", "vpp_sel", 12),
+	GATE_VPP10(CLK_VPP1_SVPP3_MDP_FG, "vpp1_svpp3_mdp_fg", "vpp_sel", 13),
+	GATE_VPP10(CLK_VPP1_VPP_SPLIT, "vpp1_vpp_split", "vpp_sel", 14),
+	GATE_VPP10(CLK_VPP1_SVPP2_VDO0_DL_RELAY, "vpp1_svpp2_vdo0_dl_relay", "vpp_sel", 15),
+	GATE_VPP10(CLK_VPP1_SVPP1_MDP_TDSHP, "vpp1_svpp1_mdp_tdshp", "vpp_sel", 16),
+	GATE_VPP10(CLK_VPP1_SVPP1_MDP_COLOR, "vpp1_svpp1_mdp_color", "vpp_sel", 17),
+	GATE_VPP10(CLK_VPP1_SVPP3_VDO1_DL_RELAY, "vpp1_svpp3_vdo1_dl_relay", "vpp_sel", 18),
+	GATE_VPP10(CLK_VPP1_SVPP2_VPP_MERGE, "vpp1_svpp2_vpp_merge", "vpp_sel", 19),
+	GATE_VPP10(CLK_VPP1_SVPP2_MDP_COLOR, "vpp1_svpp2_mdp_color", "vpp_sel", 20),
+	GATE_VPP10(CLK_VPP1_VPPSYS1_GALS, "vpp1_vppsys1_gals", "vpp_sel", 21),
+	GATE_VPP10(CLK_VPP1_SVPP3_VPP_MERGE, "vpp1_svpp3_vpp_merge", "vpp_sel", 22),
+	GATE_VPP10(CLK_VPP1_SVPP3_MDP_COLOR, "vpp1_svpp3_mdp_color", "vpp_sel", 23),
+	GATE_VPP10(CLK_VPP1_VPPSYS1_LARB, "vpp1_vppsys1_larb", "vpp_sel", 24),
+	GATE_VPP10(CLK_VPP1_SVPP1_MDP_RSZ, "vpp1_svpp1_mdp_rsz", "vpp_sel", 25),
+	GATE_VPP10(CLK_VPP1_SVPP1_MDP_HDR, "vpp1_svpp1_mdp_hdr", "vpp_sel", 26),
+	GATE_VPP10(CLK_VPP1_SVPP1_MDP_AAL, "vpp1_svpp1_mdp_aal", "vpp_sel", 27),
+	GATE_VPP10(CLK_VPP1_SVPP2_MDP_HDR, "vpp1_svpp2_mdp_hdr", "vpp_sel", 28),
+	GATE_VPP10(CLK_VPP1_SVPP2_MDP_AAL, "vpp1_svpp2_mdp_aal", "vpp_sel", 29),
+	GATE_VPP10(CLK_VPP1_DL_ASYNC, "vpp1_dl_async", "vpp_sel", 30),
+	GATE_VPP10(CLK_VPP1_LARB5_FAKE_ENG, "vpp1_larb5_fake_eng", "vpp_sel", 31),
+	/* VPP11 */
+	GATE_VPP11(CLK_VPP1_SVPP3_MDP_HDR, "vpp1_svpp3_mdp_hdr", "vpp_sel", 0),
+	GATE_VPP11(CLK_VPP1_SVPP3_MDP_AAL, "vpp1_svpp3_mdp_aal", "vpp_sel", 1),
+	GATE_VPP11(CLK_VPP1_SVPP2_VDO1_DL_RELAY, "vpp1_svpp2_vdo1_dl_relay", "vpp_sel", 2),
+	GATE_VPP11(CLK_VPP1_LARB6_FAKE_ENG, "vpp1_larb6_fake_eng", "vpp_sel", 3),
+	GATE_VPP11(CLK_VPP1_SVPP2_MDP_RSZ, "vpp1_svpp2_mdp_rsz", "vpp_sel", 4),
+	GATE_VPP11(CLK_VPP1_SVPP3_MDP_RSZ, "vpp1_svpp3_mdp_rsz", "vpp_sel", 5),
+	GATE_VPP11(CLK_VPP1_SVPP3_VDO0_DL_RELAY, "vpp1_svpp3_vdo0_dl_relay", "vpp_sel", 6),
+	GATE_VPP11(CLK_VPP1_DISP_MUTEX, "vpp1_disp_mutex", "vpp_sel", 7),
+	GATE_VPP11(CLK_VPP1_SVPP2_MDP_TDSHP, "vpp1_svpp2_mdp_tdshp", "vpp_sel", 8),
+	GATE_VPP11(CLK_VPP1_SVPP3_MDP_TDSHP, "vpp1_svpp3_mdp_tdshp", "vpp_sel", 9),
+	GATE_VPP11(CLK_VPP1_VPP0_DL1_RELAY, "vpp1_vpp0_dl1_relay", "vpp_sel", 10),
+	GATE_VPP11(CLK_VPP1_HDMI_META, "vpp1_hdmi_meta", "hdmirx_p", 11),
+	GATE_VPP11(CLK_VPP1_VPP_SPLIT_HDMI, "vpp1_vpp_split_hdmi", "hdmirx_p", 12),
+	GATE_VPP11(CLK_VPP1_DGI_IN, "vpp1_dgi_in", "in_dgi", 13),
+	GATE_VPP11(CLK_VPP1_DGI_OUT, "vpp1_dgi_out", "dgi_out_sel", 14),
+	GATE_VPP11(CLK_VPP1_VPP_SPLIT_DGI, "vpp1_vpp_split_dgi", "dgi_out_sel", 15),
+	GATE_VPP11(CLK_VPP1_VPP0_DL_ASYNC, "vpp1_vpp0_dl_async", "vpp_sel", 16),
+	GATE_VPP11(CLK_VPP1_VPP0_DL_RELAY, "vpp1_vpp0_dl_relay", "vpp_sel", 17),
+	GATE_VPP11(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m", "clk26m", 26),
+};
+
+static const struct mtk_clk_desc vpp1_desc = {
+	.clks = vpp1_clks,
+	.num_clks = ARRAY_SIZE(vpp1_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8195_vpp1[] = {
+	{
+		.compatible = "mediatek,mt8195-vppsys1",
+		.data = &vpp1_desc,
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver clk_mt8195_vpp1_drv = {
+	.probe = mtk_clk_simple_probe,
+	.driver = {
+		.name = "clk-mt8195-vpp1",
+		.of_match_table = of_match_clk_mt8195_vpp1,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_vpp1_drv);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 20/22] clk: mediatek: Add MT8195 wpesys clock support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (18 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 19/22] clk: mediatek: Add MT8195 vppsys1 " Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-08-25 11:26   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 21/22] clk: mediatek: Add MT8195 imp i2c wrapper " Chun-Jie Chen
  2021-06-16 22:47 ` [PATCH 22/22] clk: mediatek: Add MT8195 apusys " Chun-Jie Chen
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 wpesys clock providers

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig          |   6 ++
 drivers/clk/mediatek/Makefile         |   1 +
 drivers/clk/mediatek/clk-mt8195-wpe.c | 145 ++++++++++++++++++++++++++
 3 files changed, 152 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-wpe.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 91b1c19da1ab..5089bacdf0a5 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -678,6 +678,12 @@ config COMMON_CLK_MT8195_VPPSYS1
 	help
 	  This driver supports MediaTek MT8195 vppsys1 clocks.
 
+config COMMON_CLK_MT8195_WPESYS
+	bool "Clock driver for MediaTek MT8195 wpesys"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 wpesys clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index fbf57473bb91..32cfb0030d92 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -96,5 +96,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS1) += clk-mt8195-vdo1.o
 obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
 obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS0) += clk-mt8195-vpp0.o
 obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS1) += clk-mt8195-vpp1.o
+obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-wpe.c b/drivers/clk/mediatek/clk-mt8195-wpe.c
new file mode 100644
index 000000000000..99e8b1297ef7
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-wpe.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static const struct mtk_gate_regs wpe_cg_regs = {
+	.set_ofs = 0x0,
+	.clr_ofs = 0x0,
+	.sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs wpe_vpp0_cg_regs = {
+	.set_ofs = 0x58,
+	.clr_ofs = 0x58,
+	.sta_ofs = 0x58,
+};
+
+static const struct mtk_gate_regs wpe_vpp1_cg_regs = {
+	.set_ofs = 0x5c,
+	.clr_ofs = 0x5c,
+	.sta_ofs = 0x5c,
+};
+
+#define GATE_WPE(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &wpe_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_WPE_VPP0(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &wpe_vpp0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_WPE_VPP1(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &wpe_vpp1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+static const struct mtk_gate wpe_clks[] = {
+	GATE_WPE(CLK_WPE_VPP0, "wpe_vpp0", "wpe_vpp_sel", 16),
+	GATE_WPE(CLK_WPE_VPP1, "wpe_vpp1", "wpe_vpp_sel", 17),
+	GATE_WPE(CLK_WPE_SMI_LARB7, "wpe_smi_larb7", "wpe_vpp_sel", 18),
+	GATE_WPE(CLK_WPE_SMI_LARB8, "wpe_smi_larb8", "wpe_vpp_sel", 19),
+	GATE_WPE(CLK_WPE_EVENT_TX, "wpe_event_tx", "wpe_vpp_sel", 20),
+	GATE_WPE(CLK_WPE_SMI_LARB7_P, "wpe_smi_larb7_p", "wpe_vpp_sel", 24),
+	GATE_WPE(CLK_WPE_SMI_LARB8_P, "wpe_smi_larb8_p", "wpe_vpp_sel", 25),
+};
+
+static const struct mtk_gate wpe_vpp0_clks[] = {
+	/* WPE_VPP0 */
+	GATE_WPE_VPP0(CLK_WPE_VPP0_VGEN, "wpe_vpp0_vgen", "img_sel", 0),
+	GATE_WPE_VPP0(CLK_WPE_VPP0_EXT, "wpe_vpp0_ext", "img_sel", 1),
+	GATE_WPE_VPP0(CLK_WPE_VPP0_VFC, "wpe_vpp0_vfc", "img_sel", 2),
+	GATE_WPE_VPP0(CLK_WPE_VPP0_CACH0_TOP, "wpe_vpp0_cach0_top", "img_sel", 3),
+	GATE_WPE_VPP0(CLK_WPE_VPP0_CACH0_DMA, "wpe_vpp0_cach0_dma", "img_sel", 4),
+	GATE_WPE_VPP0(CLK_WPE_VPP0_CACH1_TOP, "wpe_vpp0_cach1_top", "img_sel", 5),
+	GATE_WPE_VPP0(CLK_WPE_VPP0_CACH1_DMA, "wpe_vpp0_cach1_dma", "img_sel", 6),
+	GATE_WPE_VPP0(CLK_WPE_VPP0_CACH2_TOP, "wpe_vpp0_cach2_top", "img_sel", 7),
+	GATE_WPE_VPP0(CLK_WPE_VPP0_CACH2_DMA, "wpe_vpp0_cach2_dma", "img_sel", 8),
+	GATE_WPE_VPP0(CLK_WPE_VPP0_CACH3_TOP, "wpe_vpp0_cach3_top", "img_sel", 9),
+	GATE_WPE_VPP0(CLK_WPE_VPP0_CACH3_DMA, "wpe_vpp0_cach3_dma", "img_sel", 10),
+	GATE_WPE_VPP0(CLK_WPE_VPP0_PSP, "wpe_vpp0_psp", "img_sel", 11),
+	GATE_WPE_VPP0(CLK_WPE_VPP0_PSP2, "wpe_vpp0_psp2", "img_sel", 12),
+	GATE_WPE_VPP0(CLK_WPE_VPP0_SYNC, "wpe_vpp0_sync", "img_sel", 13),
+	GATE_WPE_VPP0(CLK_WPE_VPP0_C24, "wpe_vpp0_c24", "img_sel", 14),
+	GATE_WPE_VPP0(CLK_WPE_VPP0_MDP_CROP, "wpe_vpp0_mdp_crop", "img_sel", 15),
+	GATE_WPE_VPP0(CLK_WPE_VPP0_ISP_CROP, "wpe_vpp0_isp_crop", "img_sel", 16),
+	GATE_WPE_VPP0(CLK_WPE_VPP0_TOP, "wpe_vpp0_top", "img_sel", 17),
+	/* WPE_VPP1 */
+	GATE_WPE_VPP1(CLK_WPE_VPP0_VECI, "wpe_vpp0_veci", "img_sel", 0),
+	GATE_WPE_VPP1(CLK_WPE_VPP0_VEC2I, "wpe_vpp0_vec2i", "img_sel", 1),
+	GATE_WPE_VPP1(CLK_WPE_VPP0_VEC3I, "wpe_vpp0_vec3i", "img_sel", 2),
+	GATE_WPE_VPP1(CLK_WPE_VPP0_WPEO, "wpe_vpp0_wpeo", "img_sel", 3),
+	GATE_WPE_VPP1(CLK_WPE_VPP0_MSKO, "wpe_vpp0_msko", "img_sel", 4),
+};
+
+static const struct mtk_gate wpe_vpp1_clks[] = {
+	/* WPE_VPP0 */
+	GATE_WPE_VPP0(CLK_WPE_VPP1_VGEN, "wpe_vpp1_vgen", "img_sel", 0),
+	GATE_WPE_VPP0(CLK_WPE_VPP1_EXT, "wpe_vpp1_ext", "img_sel", 1),
+	GATE_WPE_VPP0(CLK_WPE_VPP1_VFC, "wpe_vpp1_vfc", "img_sel", 2),
+	GATE_WPE_VPP0(CLK_WPE_VPP1_CACH0_TOP, "wpe_vpp1_cach0_top", "img_sel", 3),
+	GATE_WPE_VPP0(CLK_WPE_VPP1_CACH0_DMA, "wpe_vpp1_cach0_dma", "img_sel", 4),
+	GATE_WPE_VPP0(CLK_WPE_VPP1_CACH1_TOP, "wpe_vpp1_cach1_top", "img_sel", 5),
+	GATE_WPE_VPP0(CLK_WPE_VPP1_CACH1_DMA, "wpe_vpp1_cach1_dma", "img_sel", 6),
+	GATE_WPE_VPP0(CLK_WPE_VPP1_CACH2_TOP, "wpe_vpp1_cach2_top", "img_sel", 7),
+	GATE_WPE_VPP0(CLK_WPE_VPP1_CACH2_DMA, "wpe_vpp1_cach2_dma", "img_sel", 8),
+	GATE_WPE_VPP0(CLK_WPE_VPP1_CACH3_TOP, "wpe_vpp1_cach3_top", "img_sel", 9),
+	GATE_WPE_VPP0(CLK_WPE_VPP1_CACH3_DMA, "wpe_vpp1_cach3_dma", "img_sel", 10),
+	GATE_WPE_VPP0(CLK_WPE_VPP1_PSP, "wpe_vpp1_psp", "img_sel", 11),
+	GATE_WPE_VPP0(CLK_WPE_VPP1_PSP2, "wpe_vpp1_psp2", "img_sel", 12),
+	GATE_WPE_VPP0(CLK_WPE_VPP1_SYNC, "wpe_vpp1_sync", "img_sel", 13),
+	GATE_WPE_VPP0(CLK_WPE_VPP1_C24, "wpe_vpp1_c24", "img_sel", 14),
+	GATE_WPE_VPP0(CLK_WPE_VPP1_MDP_CROP, "wpe_vpp1_mdp_crop", "img_sel", 15),
+	GATE_WPE_VPP0(CLK_WPE_VPP1_ISP_CROP, "wpe_vpp1_isp_crop", "img_sel", 16),
+	GATE_WPE_VPP0(CLK_WPE_VPP1_TOP, "wpe_vpp1_top", "img_sel", 17),
+	/* WPE_VPP1 */
+	GATE_WPE_VPP1(CLK_WPE_VPP1_VECI, "wpe_vpp1_veci", "img_sel", 0),
+	GATE_WPE_VPP1(CLK_WPE_VPP1_VEC2I, "wpe_vpp1_vec2i", "img_sel", 1),
+	GATE_WPE_VPP1(CLK_WPE_VPP1_VEC3I, "wpe_vpp1_vec3i", "img_sel", 2),
+	GATE_WPE_VPP1(CLK_WPE_VPP1_WPEO, "wpe_vpp1_wpeo", "img_sel", 3),
+	GATE_WPE_VPP1(CLK_WPE_VPP1_MSKO, "wpe_vpp1_msko", "img_sel", 4),
+};
+
+static const struct mtk_clk_desc wpe_desc = {
+	.clks = wpe_clks,
+	.num_clks = ARRAY_SIZE(wpe_clks),
+};
+
+static const struct mtk_clk_desc wpe_vpp0_desc = {
+	.clks = wpe_vpp0_clks,
+	.num_clks = ARRAY_SIZE(wpe_vpp0_clks),
+};
+
+static const struct mtk_clk_desc wpe_vpp1_desc = {
+	.clks = wpe_vpp1_clks,
+	.num_clks = ARRAY_SIZE(wpe_vpp1_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8195_wpe[] = {
+	{
+		.compatible = "mediatek,mt8195-wpesys",
+		.data = &wpe_desc,
+	}, {
+		.compatible = "mediatek,mt8195-wpesys_vpp0",
+		.data = &wpe_vpp0_desc,
+	}, {
+		.compatible = "mediatek,mt8195-wpesys_vpp1",
+		.data = &wpe_vpp1_desc,
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver clk_mt8195_wpe_drv = {
+	.probe = mtk_clk_simple_probe,
+	.driver = {
+		.name = "clk-mt8195-wpe",
+		.of_match_table = of_match_clk_mt8195_wpe,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_wpe_drv);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 21/22] clk: mediatek: Add MT8195 imp i2c wrapper clock support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (19 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 20/22] clk: mediatek: Add MT8195 wpesys " Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-07-12  8:34   ` Chen-Yu Tsai
  2021-06-16 22:47 ` [PATCH 22/22] clk: mediatek: Add MT8195 apusys " Chun-Jie Chen
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 imp i2c wrapper clock providers

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig                  |  6 ++
 drivers/clk/mediatek/Makefile                 |  1 +
 .../clk/mediatek/clk-mt8195-imp_iic_wrap.c    | 68 +++++++++++++++++++
 3 files changed, 75 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 5089bacdf0a5..ade85a52b7ed 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -684,6 +684,12 @@ config COMMON_CLK_MT8195_WPESYS
 	help
 	  This driver supports MediaTek MT8195 wpesys clocks.
 
+config COMMON_CLK_MT8195_IMP_IIC_WRAP
+	bool "Clock driver for MediaTek MT8195 imp_iic_wrap"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 imp_iic_wrap clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 32cfb0030d92..b10c6267ba98 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -97,5 +97,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
 obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS0) += clk-mt8195-vpp0.o
 obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS1) += clk-mt8195-vpp1.o
 obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
+obj-$(CONFIG_COMMON_CLK_MT8195_IMP_IIC_WRAP) += clk-mt8195-imp_iic_wrap.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c
new file mode 100644
index 000000000000..efb62f484bbe
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
+	.set_ofs = 0xe08,
+	.clr_ofs = 0xe04,
+	.sta_ofs = 0xe00,
+};
+
+#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift)				\
+	GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift,	\
+		&mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
+
+static const struct mtk_gate imp_iic_wrap_s_clks[] = {
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C5, "imp_iic_wrap_s_i2c5", "i2c_sel", 0),
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C6, "imp_iic_wrap_s_i2c6", "i2c_sel", 1),
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C7, "imp_iic_wrap_s_i2c7", "i2c_sel", 2),
+};
+
+static const struct mtk_gate imp_iic_wrap_w_clks[] = {
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C0, "imp_iic_wrap_w_i2c0", "i2c_sel", 0),
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C1, "imp_iic_wrap_w_i2c1", "i2c_sel", 1),
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C2, "imp_iic_wrap_w_i2c2", "i2c_sel", 2),
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C3, "imp_iic_wrap_w_i2c3", "i2c_sel", 3),
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C4, "imp_iic_wrap_w_i2c4", "i2c_sel", 4),
+};
+
+static const struct mtk_clk_desc imp_iic_wrap_s_desc = {
+	.clks = imp_iic_wrap_s_clks,
+	.num_clks = ARRAY_SIZE(imp_iic_wrap_s_clks),
+};
+
+static const struct mtk_clk_desc imp_iic_wrap_w_desc = {
+	.clks = imp_iic_wrap_w_clks,
+	.num_clks = ARRAY_SIZE(imp_iic_wrap_w_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8195_imp_iic_wrap[] = {
+	{
+		.compatible = "mediatek,mt8195-imp_iic_wrap_s",
+		.data = &imp_iic_wrap_s_desc,
+	}, {
+		.compatible = "mediatek,mt8195-imp_iic_wrap_w",
+		.data = &imp_iic_wrap_w_desc,
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct platform_driver clk_mt8195_imp_iic_wrap_drv = {
+	.probe = mtk_clk_simple_probe,
+	.driver = {
+		.name = "clk-mt8195-imp_iic_wrap",
+		.of_match_table = of_match_clk_mt8195_imp_iic_wrap,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_imp_iic_wrap_drv);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* [PATCH 22/22] clk: mediatek: Add MT8195 apusys clock support
  2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
                   ` (20 preceding siblings ...)
  2021-06-16 22:47 ` [PATCH 21/22] clk: mediatek: Add MT8195 imp i2c wrapper " Chun-Jie Chen
@ 2021-06-16 22:47 ` Chun-Jie Chen
  2021-07-12  8:51   ` Chen-Yu Tsai
  21 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 22:47 UTC (permalink / raw)
  To: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring
  Cc: linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group,
	Chun-Jie Chen

Add MT8195 apusys clock provider

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/Kconfig                 |  6 ++
 drivers/clk/mediatek/Makefile                |  1 +
 drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 84 ++++++++++++++++++++
 3 files changed, 91 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8195-apusys_pll.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index ade85a52b7ed..9bd1ebff61f2 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -690,6 +690,12 @@ config COMMON_CLK_MT8195_IMP_IIC_WRAP
 	help
 	  This driver supports MediaTek MT8195 imp_iic_wrap clocks.
 
+config COMMON_CLK_MT8195_APUSYS_PLL
+	bool "Clock driver for MediaTek MT8195 apusys_pll"
+	depends on COMMON_CLK_MT8195
+	help
+	  This driver supports MediaTek MT8195 apusys_pll clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index b10c6267ba98..676ed7d665b7 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -98,5 +98,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS0) += clk-mt8195-vpp0.o
 obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS1) += clk-mt8195-vpp1.o
 obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
 obj-$(CONFIG_COMMON_CLK_MT8195_IMP_IIC_WRAP) += clk-mt8195-imp_iic_wrap.o
+obj-$(CONFIG_COMMON_CLK_MT8195_APUSYS_PLL) += clk-mt8195-apusys_pll.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c
new file mode 100644
index 000000000000..d9b49cf71281
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8195-clk.h>
+
+#define MT8195_PLL_FMAX		(3800UL * MHZ)
+#define MT8195_PLL_FMIN		(1500UL * MHZ)
+#define MT8195_INTEGER_BITS	8
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags,	\
+			_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift,	\
+			_tuner_reg, _tuner_en_reg, _tuner_en_bit,	\
+			_pcw_reg, _pcw_shift, _pcw_chg_reg,				\
+			_en_reg, _pll_en_bit) {					\
+		.id = _id,						\
+		.name = _name,						\
+		.reg = _reg,						\
+		.pwr_reg = _pwr_reg,					\
+		.en_mask = _en_mask,					\
+		.flags = _flags,					\
+		.rst_bar_mask = _rst_bar_mask,				\
+		.fmax = MT8195_PLL_FMAX,				\
+		.fmin = MT8195_PLL_FMIN,				\
+		.pcwbits = _pcwbits,					\
+		.pcwibits = MT8195_INTEGER_BITS,			\
+		.pd_reg = _pd_reg,					\
+		.pd_shift = _pd_shift,					\
+		.tuner_reg = _tuner_reg,				\
+		.tuner_en_reg = _tuner_en_reg,				\
+		.tuner_en_bit = _tuner_en_bit,				\
+		.pcw_reg = _pcw_reg,					\
+		.pcw_shift = _pcw_shift,				\
+		.pcw_chg_reg = _pcw_chg_reg,				\
+		.en_reg = _en_reg,					\
+		.pll_en_bit = _pll_en_bit,				\
+	}
+
+static const struct mtk_pll_data apusys_plls[] = {
+	PLL(CLK_APUSYS_PLL_APUPLL, "apusys_pll_apupll", 0x008, 0x014, 0,
+		0, 0, 22, 0x00c, 24, 0, 0, 0, 0x00c, 0, 0, 0, 0),
+	PLL(CLK_APUSYS_PLL_NPUPLL, "apusys_pll_npupll", 0x018, 0x024, 0,
+		0, 0, 22, 0x01c, 24, 0, 0, 0, 0x01c, 0, 0, 0, 0),
+	PLL(CLK_APUSYS_PLL_APUPLL1, "apusys_pll_apupll1", 0x028, 0x034, 0,
+		0, 0, 22, 0x02c, 24, 0, 0, 0, 0x02c, 0, 0, 0, 0),
+	PLL(CLK_APUSYS_PLL_APUPLL2, "apusys_pll_apupll2", 0x038, 0x044, 0,
+		0, 0, 22, 0x03c, 24, 0, 0, 0, 0x03c, 0, 0, 0, 0),
+};
+
+static int clk_mt8195_apusys_pll_probe(struct platform_device *pdev)
+{
+	struct clk_onecell_data *clk_data;
+	struct device_node *node = pdev->dev.of_node;
+
+	clk_data = mtk_alloc_clk_data(CLK_APUSYS_PLL_NR_CLK);
+	if (!clk_data)
+		return -ENOMEM;
+
+	mtk_clk_register_plls(node, apusys_plls, ARRAY_SIZE(apusys_plls), clk_data);
+
+	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8195_apusys_pll[] = {
+	{ .compatible = "mediatek,mt8195-apusys_pll", },
+	{}
+};
+
+static struct platform_driver clk_mt8195_apusys_pll_drv = {
+	.probe = clk_mt8195_apusys_pll_probe,
+	.driver = {
+		.name = "clk-mt8195-apusys_pll",
+		.of_match_table = of_match_clk_mt8195_apusys_pll,
+	},
+};
+
+builtin_platform_driver(clk_mt8195_apusys_pll_drv);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock
  2021-06-16 22:47 ` [PATCH 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock Chun-Jie Chen
@ 2021-06-24 21:21   ` Rob Herring
  2021-07-12  9:32   ` Chen-Yu Tsai
  1 sibling, 0 replies; 59+ messages in thread
From: Rob Herring @ 2021-06-24 21:21 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat,
	linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group

On Thu, Jun 17, 2021 at 06:47:22AM +0800, Chun-Jie Chen wrote:
> This patch adds the new binding documentation for system clock
> and functional clock on Mediatek MT8195.
> 
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  .../arm/mediatek/mediatek,mt8195-clock.yaml   | 287 ++++++++++++++++++
>  .../mediatek/mediatek,mt8195-sys-clock.yaml   |  66 ++++
>  2 files changed, 353 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
>  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
> 
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> new file mode 100644
> index 000000000000..21554b3515cf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> @@ -0,0 +1,287 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: MediaTek Functional Clock Controller for MT8195
> +
> +maintainers:
> +  - Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +description:
> +  The Mediatek functional clock controller provides various clocks on MT8195.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - enum:

Drop 'oneOf' and 'items'.

> +              - mediatek,mt8195-nnasys
> +              - mediatek,mt8195-scp_adsp
> +              - mediatek,mt8195-audsys
> +              - mediatek,mt8195-audsys_src
> +              - mediatek,mt8195-imp_iic_wrap_s
> +              - mediatek,mt8195-imp_iic_wrap_w
> +              - mediatek,mt8195-mfgcfg
> +              - mediatek,mt8195-vppsys0
> +              - mediatek,mt8195-wpesys
> +              - mediatek,mt8195-wpesys_vpp0
> +              - mediatek,mt8195-wpesys_vpp1
> +              - mediatek,mt8195-vppsys1
> +              - mediatek,mt8195-imgsys
> +              - mediatek,mt8195-imgsys1_dip_top
> +              - mediatek,mt8195-imgsys1_dip_nr
> +              - mediatek,mt8195-imgsys1_wpe
> +              - mediatek,mt8195-ipesys
> +              - mediatek,mt8195-camsys
> +              - mediatek,mt8195-camsys_rawa
> +              - mediatek,mt8195-camsys_yuva
> +              - mediatek,mt8195-camsys_rawb
> +              - mediatek,mt8195-camsys_yuvb
> +              - mediatek,mt8195-camsys_mraw
> +              - mediatek,mt8195-ccusys
> +              - mediatek,mt8195-vdecsys_soc
> +              - mediatek,mt8195-vdecsys
> +              - mediatek,mt8195-vdecsys_core1
> +              - mediatek,mt8195-apusys_pll
> +              - mediatek,mt8195-vencsys
> +              - mediatek,mt8195-vencsys_core1
> +              - mediatek,mt8195-vdosys0
> +              - mediatek,mt8195-vdosys1
> +  reg:
> +    maxItems: 1
> +
> +  '#clock-cells':
> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    nnasys: clock-controller@10211000 {
> +        compatible = "mediatek,mt8195-nnasys";
> +        reg = <0x10211000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    scp_adsp: clock-controller@10720000 {
> +        compatible = "mediatek,mt8195-scp_adsp";
> +        reg = <0x10720000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    audsys: clock-controller@10890000 {
> +        compatible = "mediatek,mt8195-audsys";
> +        reg = <0x10890000 0x10000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    audsys_src: clock-controller@108a0000 {
> +        compatible = "mediatek,mt8195-audsys_src";
> +        reg = <0x108a0000 0x2000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    imp_iic_wrap_s: clock-controller@11d03000 {
> +        compatible = "mediatek,mt8195-imp_iic_wrap_s";
> +        reg = <0x11d03000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    imp_iic_wrap_w: clock-controller@11e05000 {
> +        compatible = "mediatek,mt8195-imp_iic_wrap_w";
> +        reg = <0x11e05000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    mfgcfg: clock-controller@13fbf000 {
> +        compatible = "mediatek,mt8195-mfgcfg";
> +        reg = <0x13fbf000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    vppsys0: clock-controller@14000000 {
> +        compatible = "mediatek,mt8195-vppsys0";
> +        reg = <0x14000000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    wpesys: clock-controller@14e00000 {
> +        compatible = "mediatek,mt8195-wpesys";
> +        reg = <0x14e00000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    wpesys_vpp0: clock-controller@14e02000 {
> +        compatible = "mediatek,mt8195-wpesys_vpp0";
> +        reg = <0x14e02000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    wpesys_vpp1: clock-controller@14e03000 {
> +        compatible = "mediatek,mt8195-wpesys_vpp1";
> +        reg = <0x14e03000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    vppsys1: clock-controller@14f00000 {
> +        compatible = "mediatek,mt8195-vppsys1";
> +        reg = <0x14f00000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    imgsys: clock-controller@15000000 {
> +        compatible = "mediatek,mt8195-imgsys";
> +        reg = <0x15000000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    imgsys1_dip_top: clock-controller@15110000 {
> +        compatible = "mediatek,mt8195-imgsys1_dip_top";
> +        reg = <0x15110000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    imgsys1_dip_nr: clock-controller@15130000 {
> +        compatible = "mediatek,mt8195-imgsys1_dip_nr";
> +        reg = <0x15130000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    imgsys1_wpe: clock-controller@15220000 {
> +        compatible = "mediatek,mt8195-imgsys1_wpe";
> +        reg = <0x15220000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    ipesys: clock-controller@15330000 {
> +        compatible = "mediatek,mt8195-ipesys";
> +        reg = <0x15330000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    camsys: clock-controller@16000000 {
> +        compatible = "mediatek,mt8195-camsys";
> +        reg = <0x16000000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    camsys_rawa: clock-controller@1604f000 {
> +        compatible = "mediatek,mt8195-camsys_rawa";
> +        reg = <0x1604f000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    camsys_yuva: clock-controller@1606f000 {
> +        compatible = "mediatek,mt8195-camsys_yuva";
> +        reg = <0x1606f000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    camsys_rawb: clock-controller@1608f000 {
> +        compatible = "mediatek,mt8195-camsys_rawb";
> +        reg = <0x1608f000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    camsys_yuvb: clock-controller@160af000 {
> +        compatible = "mediatek,mt8195-camsys_yuvb";
> +        reg = <0x160af000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    camsys_mraw: clock-controller@16140000 {
> +        compatible = "mediatek,mt8195-camsys_mraw";
> +        reg = <0x16140000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    ccusys: clock-controller@17200000 {
> +        compatible = "mediatek,mt8195-ccusys";
> +        reg = <0x17200000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    vdecsys_soc: clock-controller@1800f000 {
> +        compatible = "mediatek,mt8195-vdecsys_soc";
> +        reg = <0x1800f000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    vdecsys: clock-controller@1802f000 {
> +        compatible = "mediatek,mt8195-vdecsys";
> +        reg = <0x1802f000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    vdecsys_core1: clock-controller@1803f000 {
> +        compatible = "mediatek,mt8195-vdecsys_core1";
> +        reg = <0x1803f000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    apusys_pll: clock-controller@190f3000 {
> +        compatible = "mediatek,mt8195-apusys_pll";
> +        reg = <0x190f3000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    vencsys: clock-controller@1a000000 {
> +        compatible = "mediatek,mt8195-vencsys";
> +        reg = <0x1a000000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    vencsys_core1: clock-controller@1b000000 {
> +        compatible = "mediatek,mt8195-vencsys_core1";
> +        reg = <0x1b000000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    vdosys0: clock-controller@1c01a000 {
> +        compatible = "mediatek,mt8195-vdosys0";
> +        reg = <0x1c01a000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    vdosys1: clock-controller@1c100000 {
> +        compatible = "mediatek,mt8195-vdosys1";
> +        reg = <0x1c100000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
> new file mode 100644
> index 000000000000..ea379452ba91
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
> @@ -0,0 +1,66 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: MediaTek System Clock Controller for MT8195
> +
> +maintainers:
> +  - Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +description:
> +  The Mediatek system clock controller provides various clocks and system configuration
> +  like reset and bus protection on MT8195.
> +
> +properties:
> +  compatible:
> +    oneOf:

Drop oneOf.

> +      - items:
> +          - enum:
> +              - mediatek,mt8195-topckgen
> +              - mediatek,mt8195-infracfg_ao
> +              - mediatek,mt8195-apmixedsys
> +              - mediatek,mt8195-pericfg_ao
> +          - const: syscon
> +
> +  reg:
> +    maxItems: 1
> +
> +  '#clock-cells':
> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    topckgen: syscon@10000000 {
> +        compatible = "mediatek,mt8195-topckgen", "syscon";
> +        reg = <0x10000000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    infracfg_ao: syscon@10001000 {
> +        compatible = "mediatek,mt8195-infracfg_ao", "syscon";
> +        reg = <0x10001000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    apmixedsys: syscon@1000c000 {
> +        compatible = "mediatek,mt8195-apmixedsys", "syscon";
> +        reg = <0x1000c000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    pericfg_ao: syscon@11003000 {
> +        compatible = "mediatek,mt8195-pericfg_ao", "syscon";
> +        reg = <0x11003000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> -- 
> 2.18.0
> 
> 

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 02/22] clk: mediatek: Add dt-bindings of MT8195 clocks
  2021-06-16 22:47 ` [PATCH 02/22] clk: mediatek: Add dt-bindings of MT8195 clocks Chun-Jie Chen
@ 2021-06-24 21:22   ` Rob Herring
  2021-07-12  9:37   ` Chen-Yu Tsai
  1 sibling, 0 replies; 59+ messages in thread
From: Rob Herring @ 2021-06-24 21:22 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat,
	linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group

On Thu, Jun 17, 2021 at 06:47:23AM +0800, Chun-Jie Chen wrote:
> Add MT8195 clock dt-bindings, include topckgen, apmixedsys,
> infracfg_ao, pericfg_ao and subsystem clocks.
> 
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  include/dt-bindings/clock/mt8195-clk.h | 989 +++++++++++++++++++++++++
>  1 file changed, 989 insertions(+)
>  create mode 100644 include/dt-bindings/clock/mt8195-clk.h
> 
> diff --git a/include/dt-bindings/clock/mt8195-clk.h b/include/dt-bindings/clock/mt8195-clk.h
> new file mode 100644
> index 000000000000..c383a9904e76
> --- /dev/null
> +++ b/include/dt-bindings/clock/mt8195-clk.h
> @@ -0,0 +1,989 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */

Dual license please (and the dts files).

> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_MT8195_H
> +#define _DT_BINDINGS_CLK_MT8195_H
> +
> +/* TOPCKGEN */
> +
> +#define CLK_TOP_AXI_SEL			0
> +#define CLK_TOP_SPM_SEL			1
> +#define CLK_TOP_BUS_AXIMEM_SEL		2
> +#define CLK_TOP_VPP_SEL			3
> +#define CLK_TOP_ETHDR_SEL		4
> +#define CLK_TOP_IPE_SEL			5
> +#define CLK_TOP_CAM_SEL			6
> +#define CLK_TOP_CCU_SEL			7
> +#define CLK_TOP_IMG_SEL			8
> +#define CLK_TOP_CAMTM_SEL		9
> +#define CLK_TOP_DSP_SEL			10
> +#define CLK_TOP_DSP1_SEL		11
> +#define CLK_TOP_DSP2_SEL		12
> +#define CLK_TOP_DSP3_SEL		13
> +#define CLK_TOP_DSP4_SEL		14
> +#define CLK_TOP_DSP5_SEL		15
> +#define CLK_TOP_DSP6_SEL		16
> +#define CLK_TOP_DSP7_SEL		17
> +#define CLK_TOP_IPU_IF_SEL		18
> +#define CLK_TOP_MFG_SEL			19
> +#define CLK_TOP_CAMTG_SEL		20
> +#define CLK_TOP_CAMTG2_SEL		21
> +#define CLK_TOP_CAMTG3_SEL		22
> +#define CLK_TOP_CAMTG4_SEL		23
> +#define CLK_TOP_CAMTG5_SEL		24
> +#define CLK_TOP_UART_SEL		25
> +#define CLK_TOP_SPI_SEL			26
> +#define CLK_TOP_SPIS_SEL		27
> +#define CLK_TOP_MSDC50_0_H_SEL		28
> +#define CLK_TOP_MSDC50_0_SEL		29
> +#define CLK_TOP_MSDC30_1_SEL		30
> +#define CLK_TOP_MSDC30_2_SEL		31
> +#define CLK_TOP_INTDIR_SEL		32
> +#define CLK_TOP_AUD_INTBUS_SEL		33
> +#define CLK_TOP_AUDIO_H_SEL		34
> +#define CLK_TOP_PWRAP_ULPOSC_SEL	35
> +#define CLK_TOP_ATB_SEL			36
> +#define CLK_TOP_PWRMCU_SEL		37
> +#define CLK_TOP_DP_SEL			38
> +#define CLK_TOP_EDP_SEL			39
> +#define CLK_TOP_DPI_SEL			40
> +#define CLK_TOP_DISP_PWM0_SEL		41
> +#define CLK_TOP_DISP_PWM1_SEL		42
> +#define CLK_TOP_USB_SEL			43
> +#define CLK_TOP_SSUSB_XHCI_SEL		44
> +#define CLK_TOP_USB_1P_SEL		45
> +#define CLK_TOP_SSUSB_XHCI_1P_SEL	46
> +#define CLK_TOP_USB_2P_SEL		47
> +#define CLK_TOP_SSUSB_XHCI_2P_SEL	48
> +#define CLK_TOP_USB_3P_SEL		49
> +#define CLK_TOP_SSUSB_XHCI_3P_SEL	50
> +#define CLK_TOP_I2C_SEL			51
> +#define CLK_TOP_SENINF_SEL		52
> +#define CLK_TOP_SENINF1_SEL		53
> +#define CLK_TOP_SENINF2_SEL		54
> +#define CLK_TOP_SENINF3_SEL		55
> +#define CLK_TOP_GCPU_SEL		56
> +#define CLK_TOP_DXCC_SEL		57
> +#define CLK_TOP_DPMAIF_SEL		58
> +#define CLK_TOP_AES_UFSFDE_SEL		59
> +#define CLK_TOP_UFS_SEL			60
> +#define CLK_TOP_UFS_TICK1US_SEL		61
> +#define CLK_TOP_UFS_MP_SAP_SEL		62
> +#define CLK_TOP_VENC_SEL		63
> +#define CLK_TOP_VDEC_SEL		64
> +#define CLK_TOP_PWM_SEL			65
> +#define CLK_TOP_SPMI_P_MST_SEL		66
> +#define CLK_TOP_SPMI_M_MST_SEL		67
> +#define CLK_TOP_TL_SEL			68
> +#define CLK_TOP_TL_P1_SEL		69
> +#define CLK_TOP_AES_MSDCFDE_SEL		70
> +#define CLK_TOP_DSI_OCC_SEL		71
> +#define CLK_TOP_WPE_VPP_SEL		72
> +#define CLK_TOP_HDCP_SEL		73
> +#define CLK_TOP_HDCP_24M_SEL		74
> +#define CLK_TOP_HD20_DACR_REF_SEL	75
> +#define CLK_TOP_HD20_HDCP_C_SEL		76
> +#define CLK_TOP_HDMI_XTAL_SEL		77
> +#define CLK_TOP_HDMI_APB_SEL		78
> +#define CLK_TOP_SNPS_ETH_250M_SEL	79
> +#define CLK_TOP_SNPS_ETH_62P4M_PTP_SEL	80
> +#define CLK_TOP_SNPS_ETH_50M_RMII_SEL	81
> +#define CLK_TOP_DGI_OUT_SEL		82
> +#define CLK_TOP_NNA0_SEL		83
> +#define CLK_TOP_NNA1_SEL		84
> +#define CLK_TOP_ADSP_SEL		85
> +#define CLK_TOP_ASM_H_SEL		86
> +#define CLK_TOP_ASM_M_SEL		87
> +#define CLK_TOP_ASM_L_SEL		88
> +#define CLK_TOP_APLL1_SEL		89
> +#define CLK_TOP_APLL2_SEL		90
> +#define CLK_TOP_APLL3_SEL		91
> +#define CLK_TOP_APLL4_SEL		92
> +#define CLK_TOP_APLL5_SEL		93
> +#define CLK_TOP_I2SO1_M_SEL		94
> +#define CLK_TOP_I2SO2_M_SEL		95
> +#define CLK_TOP_I2SI1_M_SEL		96
> +#define CLK_TOP_I2SI2_M_SEL		97
> +#define CLK_TOP_DPTX_M_SEL		98
> +#define CLK_TOP_AUD_IEC_SEL		99
> +#define CLK_TOP_A1SYS_HP_SEL		100
> +#define CLK_TOP_A2SYS_SEL		101
> +#define CLK_TOP_A3SYS_SEL		102
> +#define CLK_TOP_A4SYS_SEL		103
> +#define CLK_TOP_SPINFI_B_SEL		104
> +#define CLK_TOP_NFI1X_SEL		105
> +#define CLK_TOP_ECC_SEL			106
> +#define CLK_TOP_AUDIO_LOCAL_BUS_SEL	107
> +#define CLK_TOP_SPINOR_SEL		108
> +#define CLK_TOP_DVIO_DGI_REF_SEL	109
> +#define CLK_TOP_SRCK_SEL		110
> +#define CLK_TOP_RSVD1_SEL		111
> +#define CLK_TOP_MFG_FAST_SEL		112
> +#define CLK_TOP_CLK26M_D2		113
> +#define CLK_TOP_CLK26M_D52		114
> +#define CLK_TOP_IN_DGI			115
> +#define CLK_TOP_IN_DGI_D2		116
> +#define CLK_TOP_IN_DGI_D4		117
> +#define CLK_TOP_IN_DGI_D6		118
> +#define CLK_TOP_IN_DGI_D8		119
> +#define CLK_TOP_MFGPLL_OPP		120
> +#define CLK_TOP_MAINPLL			121
> +#define CLK_TOP_MAINPLL_D3		122
> +#define CLK_TOP_MAINPLL_D4		123
> +#define CLK_TOP_MAINPLL_D4_D2		124
> +#define CLK_TOP_MAINPLL_D4_D4		125
> +#define CLK_TOP_MAINPLL_D4_D8		126
> +#define CLK_TOP_MAINPLL_D5		127
> +#define CLK_TOP_MAINPLL_D5_D2		128
> +#define CLK_TOP_MAINPLL_D5_D4		129
> +#define CLK_TOP_MAINPLL_D5_D8		130
> +#define CLK_TOP_MAINPLL_D6		131
> +#define CLK_TOP_MAINPLL_D6_D2		132
> +#define CLK_TOP_MAINPLL_D6_D4		133
> +#define CLK_TOP_MAINPLL_D6_D8		134
> +#define CLK_TOP_MAINPLL_D7		135
> +#define CLK_TOP_MAINPLL_D7_D2		136
> +#define CLK_TOP_MAINPLL_D7_D4		137
> +#define CLK_TOP_MAINPLL_D7_D8		138
> +#define CLK_TOP_MAINPLL_D9		139
> +#define CLK_TOP_UNIVPLL			140
> +#define CLK_TOP_UNIVPLL_D2		141
> +#define CLK_TOP_UNIVPLL_D3		142
> +#define CLK_TOP_UNIVPLL_D4		143
> +#define CLK_TOP_UNIVPLL_D4_D2		144
> +#define CLK_TOP_UNIVPLL_D4_D4		145
> +#define CLK_TOP_UNIVPLL_D4_D8		146
> +#define CLK_TOP_UNIVPLL_D5		147
> +#define CLK_TOP_UNIVPLL_D5_D2		148
> +#define CLK_TOP_UNIVPLL_D5_D4		149
> +#define CLK_TOP_UNIVPLL_D5_D8		150
> +#define CLK_TOP_UNIVPLL_D6		151
> +#define CLK_TOP_UNIVPLL_D6_D2		152
> +#define CLK_TOP_UNIVPLL_D6_D4		153
> +#define CLK_TOP_UNIVPLL_D6_D8		154
> +#define CLK_TOP_UNIVPLL_D6_D16		155
> +#define CLK_TOP_UNIVPLL_D7		156
> +#define CLK_TOP_UNIVPLL_192M		157
> +#define CLK_TOP_UNIVPLL_192M_D4		158
> +#define CLK_TOP_UNIVPLL_192M_D8		159
> +#define CLK_TOP_UNIVPLL_192M_D16	160
> +#define CLK_TOP_UNIVPLL_192M_D32	161
> +#define CLK_TOP_IMGPLL			162
> +#define CLK_TOP_APLL1			163
> +#define CLK_TOP_APLL1_D3		164
> +#define CLK_TOP_APLL1_D4		165
> +#define CLK_TOP_APLL2			166
> +#define CLK_TOP_APLL2_D3		167
> +#define CLK_TOP_APLL2_D4		168
> +#define CLK_TOP_APLL3			169
> +#define CLK_TOP_APLL3_D4		170
> +#define CLK_TOP_APLL4			171
> +#define CLK_TOP_APLL4_D4		172
> +#define CLK_TOP_APLL5			173
> +#define CLK_TOP_APLL5_D4		174
> +#define CLK_TOP_HDMIRX_APLL		175
> +#define CLK_TOP_HDMIRX_APLL_D3		176
> +#define CLK_TOP_HDMIRX_APLL_D4		177
> +#define CLK_TOP_HDMIRX_APLL_D6		178
> +#define CLK_TOP_NNAPLL			179
> +#define CLK_TOP_MMPLL			180
> +#define CLK_TOP_MMPLL_D4		181
> +#define CLK_TOP_MMPLL_D4_D2		182
> +#define CLK_TOP_MMPLL_D4_D4		183
> +#define CLK_TOP_MMPLL_D5		184
> +#define CLK_TOP_MMPLL_D5_D2		185
> +#define CLK_TOP_MMPLL_D5_D4		186
> +#define CLK_TOP_MMPLL_D6		187
> +#define CLK_TOP_MMPLL_D6_D2		188
> +#define CLK_TOP_MMPLL_D7		189
> +#define CLK_TOP_MMPLL_D9		190
> +#define CLK_TOP_TVDPLL1			191
> +#define CLK_TOP_TVDPLL1_D2		192
> +#define CLK_TOP_TVDPLL1_D4		193
> +#define CLK_TOP_TVDPLL1_D8		194
> +#define CLK_TOP_TVDPLL1_D16		195
> +#define CLK_TOP_TVDPLL2			196
> +#define CLK_TOP_TVDPLL2_D2		197
> +#define CLK_TOP_TVDPLL2_D4		198
> +#define CLK_TOP_TVDPLL2_D8		199
> +#define CLK_TOP_TVDPLL2_D16		200
> +#define CLK_TOP_MSDCPLL			201
> +#define CLK_TOP_MSDCPLL_D2		202
> +#define CLK_TOP_MSDCPLL_D4		203
> +#define CLK_TOP_MSDCPLL_D16		204
> +#define CLK_TOP_ETHPLL			205
> +#define CLK_TOP_ETHPLL_D2		206
> +#define CLK_TOP_ETHPLL_D8		207
> +#define CLK_TOP_ETHPLL_D10		208
> +#define CLK_TOP_DGIPLL			209
> +#define CLK_TOP_DGIPLL_D2		210
> +#define CLK_TOP_VDECPLL			211
> +#define CLK_TOP_ULPOSC			212
> +#define CLK_TOP_ULPOSC_D2		213
> +#define CLK_TOP_ULPOSC_D4		214
> +#define CLK_TOP_ULPOSC_D7		215
> +#define CLK_TOP_ULPOSC_D8		216
> +#define CLK_TOP_ULPOSC_D10		217
> +#define CLK_TOP_ULPOSC_D16		218
> +#define CLK_TOP_ULPOSC2			219
> +#define CLK_TOP_ADSPPLL			220
> +#define CLK_TOP_ADSPPLL_D2		221
> +#define CLK_TOP_ADSPPLL_D4		222
> +#define CLK_TOP_ADSPPLL_D8		223
> +#define CLK_TOP_MEM_466M		224
> +#define CLK_TOP_MPHONE_SLAVE_B		225
> +#define CLK_TOP_PEXTP_PIPE		226
> +#define CLK_TOP_UFS_RX_SYMBOL		227
> +#define CLK_TOP_UFS_TX_SYMBOL		228
> +#define CLK_TOP_SSUSB_U3PHY_P1_P_P0	229
> +#define CLK_TOP_UFS_RX_SYMBOL1		230
> +#define CLK_TOP_FPC			231
> +#define CLK_TOP_HDMIRX_P		232
> +#define CLK_TOP_APLL12_DIV0		233
> +#define CLK_TOP_APLL12_DIV1		234
> +#define CLK_TOP_APLL12_DIV2		235
> +#define CLK_TOP_APLL12_DIV3		236
> +#define CLK_TOP_APLL12_DIV4		237
> +#define CLK_TOP_APLL12_DIV9		238
> +#define CLK_TOP_CFG_VPP0		239
> +#define CLK_TOP_CFG_VPP1		240
> +#define CLK_TOP_CFG_VDO0		241
> +#define CLK_TOP_CFG_VDO1		242
> +#define CLK_TOP_CFG_UNIPLL_SES		243
> +#define CLK_TOP_CFG_26M_VPP0		244
> +#define CLK_TOP_CFG_26M_VPP1		245
> +#define CLK_TOP_CFG_26M_AUD		246
> +#define CLK_TOP_CFG_AXI_EAST		247
> +#define CLK_TOP_CFG_AXI_EAST_NORTH	248
> +#define CLK_TOP_CFG_AXI_NORTH		249
> +#define CLK_TOP_CFG_AXI_SOUTH		250
> +#define CLK_TOP_CFG_EXT_TEST		251
> +#define CLK_TOP_SSUSB_REF		252
> +#define CLK_TOP_SSUSB_PHY_REF		253
> +#define CLK_TOP_SSUSB_P1_REF		254
> +#define CLK_TOP_SSUSB_PHY_P1_REF	255
> +#define CLK_TOP_SSUSB_P2_REF		256
> +#define CLK_TOP_SSUSB_PHY_P2_REF	257
> +#define CLK_TOP_SSUSB_P3_REF		258
> +#define CLK_TOP_SSUSB_PHY_P3_REF	259
> +#define CLK_TOP_NR_CLK			260
> +
> +/* INFRACFG_AO */
> +
> +#define CLK_INFRA_AO_PMIC_TMR		0
> +#define CLK_INFRA_AO_PMIC_AP		1
> +#define CLK_INFRA_AO_PMIC_MD		2
> +#define CLK_INFRA_AO_PMIC_CONN		3
> +#define CLK_INFRA_AO_SEJ		4
> +#define CLK_INFRA_AO_APXGPT		5
> +#define CLK_INFRA_AO_GCE		6
> +#define CLK_INFRA_AO_GCE2		7
> +#define CLK_INFRA_AO_THERM		8
> +#define CLK_INFRA_AO_PWM_H		9
> +#define CLK_INFRA_AO_PWM1		10
> +#define CLK_INFRA_AO_PWM2		11
> +#define CLK_INFRA_AO_PWM3		12
> +#define CLK_INFRA_AO_PWM4		13
> +#define CLK_INFRA_AO_PWM		14
> +#define CLK_INFRA_AO_UART0		15
> +#define CLK_INFRA_AO_UART1		16
> +#define CLK_INFRA_AO_UART2		17
> +#define CLK_INFRA_AO_UART3		18
> +#define CLK_INFRA_AO_UART4		19
> +#define CLK_INFRA_AO_GCE_26M		20
> +#define CLK_INFRA_AO_CQ_DMA_FPC		21
> +#define CLK_INFRA_AO_UART5		22
> +#define CLK_INFRA_AO_HDMI_26M		23
> +#define CLK_INFRA_AO_SPI0		24
> +#define CLK_INFRA_AO_MSDC0		25
> +#define CLK_INFRA_AO_MSDC1		26
> +#define CLK_INFRA_AO_CG1_MSDC2		27
> +#define CLK_INFRA_AO_MSDC0_SRC		28
> +#define CLK_INFRA_AO_TRNG		29
> +#define CLK_INFRA_AO_AUXADC		30
> +#define CLK_INFRA_AO_CPUM		31
> +#define CLK_INFRA_AO_HDMI_32K		32
> +#define CLK_INFRA_AO_CEC_66M_H		33
> +#define CLK_INFRA_AO_IRRX		34
> +#define CLK_INFRA_AO_PCIE_TL_26M	35
> +#define CLK_INFRA_AO_MSDC1_SRC		36
> +#define CLK_INFRA_AO_CEC_66M_B		37
> +#define CLK_INFRA_AO_PCIE_TL_96M	38
> +#define CLK_INFRA_AO_DEVICE_APC		39
> +#define CLK_INFRA_AO_ECC_66M_H		40
> +#define CLK_INFRA_AO_DEBUGSYS		41
> +#define CLK_INFRA_AO_AUDIO		42
> +#define CLK_INFRA_AO_PCIE_TL_32K	43
> +#define CLK_INFRA_AO_DBG_TRACE		44
> +#define CLK_INFRA_AO_DRAMC_F26M		45
> +#define CLK_INFRA_AO_IRTX		46
> +#define CLK_INFRA_AO_SSUSB		47
> +#define CLK_INFRA_AO_DISP_PWM		48
> +#define CLK_INFRA_AO_CLDMA_B		49
> +#define CLK_INFRA_AO_AUDIO_26M_B	50
> +#define CLK_INFRA_AO_SPI1		51
> +#define CLK_INFRA_AO_SPI2		52
> +#define CLK_INFRA_AO_SPI3		53
> +#define CLK_INFRA_AO_UNIPRO_SYS		54
> +#define CLK_INFRA_AO_UNIPRO_TICK	55
> +#define CLK_INFRA_AO_UFS_MP_SAP_B	56
> +#define CLK_INFRA_AO_PWRMCU		57
> +#define CLK_INFRA_AO_PWRMCU_BUS_H	58
> +#define CLK_INFRA_AO_APDMA_B		59
> +#define CLK_INFRA_AO_SPI4		60
> +#define CLK_INFRA_AO_SPI5		61
> +#define CLK_INFRA_AO_CQ_DMA		62
> +#define CLK_INFRA_AO_AES_UFSFDE		63
> +#define CLK_INFRA_AO_AES		64
> +#define CLK_INFRA_AO_UFS_TICK		65
> +#define CLK_INFRA_AO_SSUSB_XHCI		66
> +#define CLK_INFRA_AO_MSDC0_SELF		67
> +#define CLK_INFRA_AO_MSDC1_SELF		68
> +#define CLK_INFRA_AO_MSDC2_SELF		69
> +#define CLK_INFRA_AO_I2S_DMA		70
> +#define CLK_INFRA_AO_AP_MSDC0		71
> +#define CLK_INFRA_AO_MD_MSDC0		72
> +#define CLK_INFRA_AO_CG3_MSDC2		73
> +#define CLK_INFRA_AO_GCPU		74
> +#define CLK_INFRA_AO_PCIE_PERI_26M	75
> +#define CLK_INFRA_AO_GCPU_66M_B		76
> +#define CLK_INFRA_AO_GCPU_133M_B	77
> +#define CLK_INFRA_AO_DISP_PWM1		78
> +#define CLK_INFRA_AO_FBIST2FPC		79
> +#define CLK_INFRA_AO_DEVICE_APC_SYNC	80
> +#define CLK_INFRA_AO_PCIE_P1_PERI_26M	81
> +#define CLK_INFRA_AO_SPIS0		82
> +#define CLK_INFRA_AO_SPIS1		83
> +#define CLK_INFRA_AO_133M_M_PERI	84
> +#define CLK_INFRA_AO_66M_M_PERI		85
> +#define CLK_INFRA_AO_PCIE_PL_P_250M_P0	86
> +#define CLK_INFRA_AO_PCIE_PL_P_250M_P1	87
> +#define CLK_INFRA_AO_PCIE_P1_TL_96M	88
> +#define CLK_INFRA_AO_AES_MSDCFDE_0P	89
> +#define CLK_INFRA_AO_UFS_TX_SYMBOL	90
> +#define CLK_INFRA_AO_UFS_RX_SYMBOL	91
> +#define CLK_INFRA_AO_UFS_RX_SYMBOL1	92
> +#define CLK_INFRA_AO_PERI_UFS_MEM_SUB	93
> +#define CLK_INFRA_AO_NR_CLK		94
> +
> +/* APMIXEDSYS */
> +
> +#define CLK_APMIXED_NNAPLL		0
> +#define CLK_APMIXED_RESPLL		1
> +#define CLK_APMIXED_ETHPLL		2
> +#define CLK_APMIXED_MSDCPLL		3
> +#define CLK_APMIXED_TVDPLL1		4
> +#define CLK_APMIXED_TVDPLL2		5
> +#define CLK_APMIXED_MMPLL		6
> +#define CLK_APMIXED_MAINPLL		7
> +#define CLK_APMIXED_VDECPLL		8
> +#define CLK_APMIXED_IMGPLL		9
> +#define CLK_APMIXED_UNIVPLL		10
> +#define CLK_APMIXED_HDMIPLL1		11
> +#define CLK_APMIXED_HDMIPLL2		12
> +#define CLK_APMIXED_HDMIRX_APLL		13
> +#define CLK_APMIXED_USB1PLL		14
> +#define CLK_APMIXED_ADSPPLL		15
> +#define CLK_APMIXED_APLL1		16
> +#define CLK_APMIXED_APLL2		17
> +#define CLK_APMIXED_APLL3		18
> +#define CLK_APMIXED_APLL4		19
> +#define CLK_APMIXED_APLL5		20
> +#define CLK_APMIXED_MFGPLL		21
> +#define CLK_APMIXED_DGIPLL		22
> +#define CLK_APMIXED_PLL_SSUSB26M	23
> +#define CLK_APMIXED_NR_CLK		24
> +
> +/* NNASYS */
> +
> +#define CLK_NNA_NNA0			0
> +#define CLK_NNA_NNA1			1
> +#define CLK_NNA_NNA0_EMI		2
> +#define CLK_NNA_CKGEN_MEM		3
> +#define CLK_NNA_NNA1_EMI		4
> +#define CLK_NNA_NNA0_AXI		5
> +#define CLK_NNA_NNA1_AXI		6
> +#define CLK_NNA_F26M			7
> +#define CLK_NNA_AXI			8
> +#define CLK_NNA_NR_CLK			9
> +
> +/* SCP_ADSP */
> +
> +#define CLK_SCP_ADSP_AUDIODSP		0
> +#define CLK_SCP_ADSP_NR_CLK		1
> +
> +/* AUDSYS */
> +
> +#define CLK_AUD_AFE			0
> +#define CLK_AUD_LRCK_CNT		1
> +#define CLK_AUD_SPDIFIN_TUNER_APLL	2
> +#define CLK_AUD_SPDIFIN_TUNER_DBG	3
> +#define CLK_AUD_UL_TML			4
> +#define CLK_AUD_APLL1_TUNER		5
> +#define CLK_AUD_APLL2_TUNER		6
> +#define CLK_AUD_TOP0_SPDF		7
> +#define CLK_AUD_APLL			8
> +#define CLK_AUD_APLL2			9
> +#define CLK_AUD_DAC			10
> +#define CLK_AUD_DAC_PREDIS		11
> +#define CLK_AUD_TML			12
> +#define CLK_AUD_ADC			13
> +#define CLK_AUD_DAC_HIRES		14
> +#define CLK_AUD_A1SYS_HP		15
> +#define CLK_AUD_AFE_DMIC1		16
> +#define CLK_AUD_AFE_DMIC2		17
> +#define CLK_AUD_AFE_DMIC3		18
> +#define CLK_AUD_AFE_DMIC4		19
> +#define CLK_AUD_AFE_26M_DMIC_TM		20
> +#define CLK_AUD_UL_TML_HIRES		21
> +#define CLK_AUD_ADC_HIRES		22
> +#define CLK_AUD_ADDA6_ADC		23
> +#define CLK_AUD_ADDA6_ADC_HIRES		24
> +#define CLK_AUD_LINEIN_TUNER		25
> +#define CLK_AUD_EARC_TUNER		26
> +#define CLK_AUD_I2SIN			27
> +#define CLK_AUD_TDM_IN			28
> +#define CLK_AUD_I2S_OUT			29
> +#define CLK_AUD_TDM_OUT			30
> +#define CLK_AUD_HDMI_OUT		31
> +#define CLK_AUD_ASRC11			32
> +#define CLK_AUD_ASRC12			33
> +#define CLK_AUD_MULTI_IN		34
> +#define CLK_AUD_INTDIR			35
> +#define CLK_AUD_A1SYS			36
> +#define CLK_AUD_A2SYS			37
> +#define CLK_AUD_PCMIF			38
> +#define CLK_AUD_A3SYS			39
> +#define CLK_AUD_A4SYS			40
> +#define CLK_AUD_MEMIF_UL1		41
> +#define CLK_AUD_MEMIF_UL2		42
> +#define CLK_AUD_MEMIF_UL3		43
> +#define CLK_AUD_MEMIF_UL4		44
> +#define CLK_AUD_MEMIF_UL5		45
> +#define CLK_AUD_MEMIF_UL6		46
> +#define CLK_AUD_MEMIF_UL8		47
> +#define CLK_AUD_MEMIF_UL9		48
> +#define CLK_AUD_MEMIF_UL10		49
> +#define CLK_AUD_MEMIF_DL2		50
> +#define CLK_AUD_MEMIF_DL3		51
> +#define CLK_AUD_MEMIF_DL6		52
> +#define CLK_AUD_MEMIF_DL7		53
> +#define CLK_AUD_MEMIF_DL8		54
> +#define CLK_AUD_MEMIF_DL10		55
> +#define CLK_AUD_MEMIF_DL11		56
> +#define CLK_AUD_GASRC0			57
> +#define CLK_AUD_GASRC1			58
> +#define CLK_AUD_GASRC2			59
> +#define CLK_AUD_GASRC3			60
> +#define CLK_AUD_GASRC4			61
> +#define CLK_AUD_GASRC5			62
> +#define CLK_AUD_GASRC6			63
> +#define CLK_AUD_GASRC7			64
> +#define CLK_AUD_GASRC8			65
> +#define CLK_AUD_GASRC9			66
> +#define CLK_AUD_GASRC10			67
> +#define CLK_AUD_GASRC11			68
> +#define CLK_AUD_GASRC12			69
> +#define CLK_AUD_GASRC13			70
> +#define CLK_AUD_GASRC14			71
> +#define CLK_AUD_GASRC15			72
> +#define CLK_AUD_GASRC16			73
> +#define CLK_AUD_GASRC17			74
> +#define CLK_AUD_GASRC18			75
> +#define CLK_AUD_GASRC19			76
> +#define CLK_AUD_NR_CLK			77
> +
> +/* AUDSYS_SRC */
> +
> +#define CLK_AUD_SRC_ASRC0		0
> +#define CLK_AUD_SRC_ASRC1		1
> +#define CLK_AUD_SRC_ASRC2		2
> +#define CLK_AUD_SRC_ASRC3		3
> +#define CLK_AUD_SRC_ASRC4		4
> +#define CLK_AUD_SRC_ASRC5		5
> +#define CLK_AUD_SRC_ASRC6		6
> +#define CLK_AUD_SRC_ASRC7		7
> +#define CLK_AUD_SRC_ASRC8		8
> +#define CLK_AUD_SRC_ASRC9		9
> +#define CLK_AUD_SRC_ASRC10		10
> +#define CLK_AUD_SRC_ASRC11		11
> +#define CLK_AUD_SRC_NR_CLK		12
> +
> +/* PERICFG_AO */
> +
> +#define CLK_PERI_AO_ETHERNET		0
> +#define CLK_PERI_AO_ETHERNET_BUS	1
> +#define CLK_PERI_AO_FLASHIF_BUS		2
> +#define CLK_PERI_AO_FLASHIF_FLASH	3
> +#define CLK_PERI_AO_SSUSB_1P_BUS	4
> +#define CLK_PERI_AO_SSUSB_1P_XHCI	5
> +#define CLK_PERI_AO_SSUSB_2P_BUS	6
> +#define CLK_PERI_AO_SSUSB_2P_XHCI	7
> +#define CLK_PERI_AO_SSUSB_3P_BUS	8
> +#define CLK_PERI_AO_SSUSB_3P_XHCI	9
> +#define CLK_PERI_AO_SPINFI		10
> +#define CLK_PERI_AO_ETHERNET_MAC	11
> +#define CLK_PERI_AO_NFI_H		12
> +#define CLK_PERI_AO_FNFI1X		13
> +#define CLK_PERI_AO_PCIE_P0_MEM		14
> +#define CLK_PERI_AO_PCIE_P1_MEM		15
> +#define CLK_PERI_AO_NR_CLK		16
> +
> +/* IMP_IIC_WRAP_S */
> +
> +#define CLK_IMP_IIC_WRAP_S_I2C5		0
> +#define CLK_IMP_IIC_WRAP_S_I2C6		1
> +#define CLK_IMP_IIC_WRAP_S_I2C7		2
> +#define CLK_IMP_IIC_WRAP_S_NR_CLK	3
> +
> +/* IMP_IIC_WRAP_W */
> +
> +#define CLK_IMP_IIC_WRAP_W_I2C0		0
> +#define CLK_IMP_IIC_WRAP_W_I2C1		1
> +#define CLK_IMP_IIC_WRAP_W_I2C2		2
> +#define CLK_IMP_IIC_WRAP_W_I2C3		3
> +#define CLK_IMP_IIC_WRAP_W_I2C4		4
> +#define CLK_IMP_IIC_WRAP_W_NR_CLK	5
> +
> +/* MFGCFG */
> +
> +#define CLK_MFG_BG3D			0
> +#define CLK_MFG_NR_CLK			1
> +
> +/* VPPSYS0 */
> +
> +#define CLK_VPP0_MDP_FG				0
> +#define CLK_VPP0_STITCH				1
> +#define CLK_VPP0_PADDING			2
> +#define CLK_VPP0_MDP_TCC			3
> +#define CLK_VPP0_WARP0_ASYNC_TX			4
> +#define CLK_VPP0_WARP1_ASYNC_TX			5
> +#define CLK_VPP0_MUTEX				6
> +#define CLK_VPP0_VPP02VPP1_RELAY		7
> +#define CLK_VPP0_VPP12VPP0_ASYNC		8
> +#define CLK_VPP0_MMSYSRAM_TOP			9
> +#define CLK_VPP0_MDP_AAL			10
> +#define CLK_VPP0_MDP_RSZ			11
> +#define CLK_VPP0_SMI_COMMON			12
> +#define CLK_VPP0_GALS_VDO0_LARB0		13
> +#define CLK_VPP0_GALS_VDO0_LARB1		14
> +#define CLK_VPP0_GALS_VENCSYS			15
> +#define CLK_VPP0_GALS_VENCSYS_CORE1		16
> +#define CLK_VPP0_GALS_INFRA			17
> +#define CLK_VPP0_GALS_CAMSYS			18
> +#define CLK_VPP0_GALS_VPP1_LARB5		19
> +#define CLK_VPP0_GALS_VPP1_LARB6		20
> +#define CLK_VPP0_SMI_REORDER			21
> +#define CLK_VPP0_SMI_IOMMU			22
> +#define CLK_VPP0_GALS_IMGSYS_CAMSYS		23
> +#define CLK_VPP0_MDP_RDMA			24
> +#define CLK_VPP0_MDP_WROT			25
> +#define CLK_VPP0_GALS_EMI0_EMI1			26
> +#define CLK_VPP0_SMI_SUB_COMMON_REORDER		27
> +#define CLK_VPP0_SMI_RSI			28
> +#define CLK_VPP0_SMI_COMMON_LARB4		29
> +#define CLK_VPP0_GALS_VDEC_VDEC_CORE1		30
> +#define CLK_VPP0_GALS_VPP1_WPE			31
> +#define CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1	32
> +#define CLK_VPP0_FAKE_ENG			33
> +#define CLK_VPP0_MDP_HDR			34
> +#define CLK_VPP0_MDP_TDSHP			35
> +#define CLK_VPP0_MDP_COLOR			36
> +#define CLK_VPP0_MDP_OVL			37
> +#define CLK_VPP0_WARP0_RELAY			38
> +#define CLK_VPP0_WARP0_MDP_DL_ASYNC		39
> +#define CLK_VPP0_WARP1_RELAY			40
> +#define CLK_VPP0_WARP1_MDP_DL_ASYNC		41
> +#define CLK_VPP0_NR_CLK				42
> +
> +/* WPESYS */
> +
> +#define CLK_WPE_VPP0			0
> +#define CLK_WPE_VPP1			1
> +#define CLK_WPE_SMI_LARB7		2
> +#define CLK_WPE_SMI_LARB8		3
> +#define CLK_WPE_EVENT_TX		4
> +#define CLK_WPE_SMI_LARB7_P		5
> +#define CLK_WPE_SMI_LARB8_P		6
> +#define CLK_WPE_NR_CLK			7
> +
> +/* WPESYS_VPP0 */
> +
> +#define CLK_WPE_VPP0_VECI		0
> +#define CLK_WPE_VPP0_VEC2I		1
> +#define CLK_WPE_VPP0_VEC3I		2
> +#define CLK_WPE_VPP0_WPEO		3
> +#define CLK_WPE_VPP0_MSKO		4
> +#define CLK_WPE_VPP0_VGEN		5
> +#define CLK_WPE_VPP0_EXT		6
> +#define CLK_WPE_VPP0_VFC		7
> +#define CLK_WPE_VPP0_CACH0_TOP		8
> +#define CLK_WPE_VPP0_CACH0_DMA		9
> +#define CLK_WPE_VPP0_CACH1_TOP		10
> +#define CLK_WPE_VPP0_CACH1_DMA		11
> +#define CLK_WPE_VPP0_CACH2_TOP		12
> +#define CLK_WPE_VPP0_CACH2_DMA		13
> +#define CLK_WPE_VPP0_CACH3_TOP		14
> +#define CLK_WPE_VPP0_CACH3_DMA		15
> +#define CLK_WPE_VPP0_PSP		16
> +#define CLK_WPE_VPP0_PSP2		17
> +#define CLK_WPE_VPP0_SYNC		18
> +#define CLK_WPE_VPP0_C24		19
> +#define CLK_WPE_VPP0_MDP_CROP		20
> +#define CLK_WPE_VPP0_ISP_CROP		21
> +#define CLK_WPE_VPP0_TOP		22
> +#define CLK_WPE_VPP0_NR_CLK		23
> +
> +/* WPESYS_VPP1 */
> +
> +#define CLK_WPE_VPP1_VECI		0
> +#define CLK_WPE_VPP1_VEC2I		1
> +#define CLK_WPE_VPP1_VEC3I		2
> +#define CLK_WPE_VPP1_WPEO		3
> +#define CLK_WPE_VPP1_MSKO		4
> +#define CLK_WPE_VPP1_VGEN		5
> +#define CLK_WPE_VPP1_EXT		6
> +#define CLK_WPE_VPP1_VFC		7
> +#define CLK_WPE_VPP1_CACH0_TOP		8
> +#define CLK_WPE_VPP1_CACH0_DMA		9
> +#define CLK_WPE_VPP1_CACH1_TOP		10
> +#define CLK_WPE_VPP1_CACH1_DMA		11
> +#define CLK_WPE_VPP1_CACH2_TOP		12
> +#define CLK_WPE_VPP1_CACH2_DMA		13
> +#define CLK_WPE_VPP1_CACH3_TOP		14
> +#define CLK_WPE_VPP1_CACH3_DMA		15
> +#define CLK_WPE_VPP1_PSP		16
> +#define CLK_WPE_VPP1_PSP2		17
> +#define CLK_WPE_VPP1_SYNC		18
> +#define CLK_WPE_VPP1_C24		19
> +#define CLK_WPE_VPP1_MDP_CROP		20
> +#define CLK_WPE_VPP1_ISP_CROP		21
> +#define CLK_WPE_VPP1_TOP		22
> +#define CLK_WPE_VPP1_NR_CLK		23
> +
> +/* VPPSYS1 */
> +
> +#define CLK_VPP1_SVPP1_MDP_OVL		0
> +#define CLK_VPP1_SVPP1_MDP_TCC		1
> +#define CLK_VPP1_SVPP1_MDP_WROT		2
> +#define CLK_VPP1_SVPP1_VPP_PAD		3
> +#define CLK_VPP1_SVPP2_MDP_WROT		4
> +#define CLK_VPP1_SVPP2_VPP_PAD		5
> +#define CLK_VPP1_SVPP3_MDP_WROT		6
> +#define CLK_VPP1_SVPP3_VPP_PAD		7
> +#define CLK_VPP1_SVPP1_MDP_RDMA		8
> +#define CLK_VPP1_SVPP1_MDP_FG		9
> +#define CLK_VPP1_SVPP2_MDP_RDMA		10
> +#define CLK_VPP1_SVPP2_MDP_FG		11
> +#define CLK_VPP1_SVPP3_MDP_RDMA		12
> +#define CLK_VPP1_SVPP3_MDP_FG		13
> +#define CLK_VPP1_VPP_SPLIT		14
> +#define CLK_VPP1_SVPP2_VDO0_DL_RELAY	15
> +#define CLK_VPP1_SVPP1_MDP_TDSHP	16
> +#define CLK_VPP1_SVPP1_MDP_COLOR	17
> +#define CLK_VPP1_SVPP3_VDO1_DL_RELAY	18
> +#define CLK_VPP1_SVPP2_VPP_MERGE	19
> +#define CLK_VPP1_SVPP2_MDP_COLOR	20
> +#define CLK_VPP1_VPPSYS1_GALS		21
> +#define CLK_VPP1_SVPP3_VPP_MERGE	22
> +#define CLK_VPP1_SVPP3_MDP_COLOR	23
> +#define CLK_VPP1_VPPSYS1_LARB		24
> +#define CLK_VPP1_SVPP1_MDP_RSZ		25
> +#define CLK_VPP1_SVPP1_MDP_HDR		26
> +#define CLK_VPP1_SVPP1_MDP_AAL		27
> +#define CLK_VPP1_SVPP2_MDP_HDR		28
> +#define CLK_VPP1_SVPP2_MDP_AAL		29
> +#define CLK_VPP1_DL_ASYNC		30
> +#define CLK_VPP1_LARB5_FAKE_ENG		31
> +#define CLK_VPP1_SVPP3_MDP_HDR		32
> +#define CLK_VPP1_SVPP3_MDP_AAL		33
> +#define CLK_VPP1_SVPP2_VDO1_DL_RELAY	34
> +#define CLK_VPP1_LARB6_FAKE_ENG		35
> +#define CLK_VPP1_SVPP2_MDP_RSZ		36
> +#define CLK_VPP1_SVPP3_MDP_RSZ		37
> +#define CLK_VPP1_SVPP3_VDO0_DL_RELAY	38
> +#define CLK_VPP1_DISP_MUTEX		39
> +#define CLK_VPP1_SVPP2_MDP_TDSHP	40
> +#define CLK_VPP1_SVPP3_MDP_TDSHP	41
> +#define CLK_VPP1_VPP0_DL1_RELAY		42
> +#define CLK_VPP1_HDMI_META		43
> +#define CLK_VPP1_VPP_SPLIT_HDMI		44
> +#define CLK_VPP1_DGI_IN			45
> +#define CLK_VPP1_DGI_OUT		46
> +#define CLK_VPP1_VPP_SPLIT_DGI		47
> +#define CLK_VPP1_VPP0_DL_ASYNC		48
> +#define CLK_VPP1_VPP0_DL_RELAY		49
> +#define CLK_VPP1_VPP_SPLIT_26M		50
> +#define CLK_VPP1_NR_CLK			51
> +
> +/* IMGSYS */
> +
> +#define CLK_IMG_LARB9			0
> +#define CLK_IMG_TRAW0			1
> +#define CLK_IMG_TRAW1			2
> +#define CLK_IMG_TRAW2			3
> +#define CLK_IMG_TRAW3			4
> +#define CLK_IMG_DIP0			5
> +#define CLK_IMG_WPE0			6
> +#define CLK_IMG_IPE			7
> +#define CLK_IMG_DIP1			8
> +#define CLK_IMG_WPE1			9
> +#define CLK_IMG_GALS			10
> +#define CLK_IMG_NR_CLK			11
> +
> +/* IMGSYS1_DIP_TOP */
> +
> +#define CLK_IMG1_DIP_TOP_LARB10		0
> +#define CLK_IMG1_DIP_TOP_DIP_TOP	1
> +#define CLK_IMG1_DIP_TOP_NR_CLK		2
> +
> +/* IMGSYS1_DIP_NR */
> +
> +#define CLK_IMG1_DIP_NR_RESERVE		0
> +#define CLK_IMG1_DIP_NR_DIP_NR		1
> +#define CLK_IMG1_DIP_NR_NR_CLK		2
> +
> +/* IMGSYS1_WPE */
> +
> +#define CLK_IMG1_WPE_LARB11		0
> +#define CLK_IMG1_WPE_WPE		1
> +#define CLK_IMG1_WPE_NR_CLK		2
> +
> +/* IPESYS */
> +
> +#define CLK_IPE_DPE			0
> +#define CLK_IPE_FDVT			1
> +#define CLK_IPE_ME			2
> +#define CLK_IPE_TOP			3
> +#define CLK_IPE_SMI_LARB12		4
> +#define CLK_IPE_NR_CLK			5
> +
> +/* CAMSYS */
> +
> +#define CLK_CAM_LARB13			0
> +#define CLK_CAM_LARB14			1
> +#define CLK_CAM_MAIN_CAM		2
> +#define CLK_CAM_MAIN_CAMTG		3
> +#define CLK_CAM_SENINF			4
> +#define CLK_CAM_GCAMSVA			5
> +#define CLK_CAM_GCAMSVB			6
> +#define CLK_CAM_GCAMSVC			7
> +#define CLK_CAM_SCAMSA			8
> +#define CLK_CAM_SCAMSB			9
> +#define CLK_CAM_CAMSV_TOP		10
> +#define CLK_CAM_CAMSV_CQ		11
> +#define CLK_CAM_ADL			12
> +#define CLK_CAM_ASG			13
> +#define CLK_CAM_PDA			14
> +#define CLK_CAM_FAKE_ENG		15
> +#define CLK_CAM_MAIN_MRAW0		16
> +#define CLK_CAM_MAIN_MRAW1		17
> +#define CLK_CAM_MAIN_MRAW2		18
> +#define CLK_CAM_MAIN_MRAW3		19
> +#define CLK_CAM_CAM2MM0_GALS		20
> +#define CLK_CAM_CAM2MM1_GALS		21
> +#define CLK_CAM_CAM2SYS_GALS		22
> +#define CLK_CAM_NR_CLK			23
> +
> +/* CAMSYS_RAWA */
> +
> +#define CLK_CAM_RAWA_LARBX		0
> +#define CLK_CAM_RAWA_CAM		1
> +#define CLK_CAM_RAWA_CAMTG		2
> +#define CLK_CAM_RAWA_NR_CLK		3
> +
> +/* CAMSYS_YUVA */
> +
> +#define CLK_CAM_YUVA_LARBX		0
> +#define CLK_CAM_YUVA_CAM		1
> +#define CLK_CAM_YUVA_CAMTG		2
> +#define CLK_CAM_YUVA_NR_CLK		3
> +
> +/* CAMSYS_RAWB */
> +
> +#define CLK_CAM_RAWB_LARBX		0
> +#define CLK_CAM_RAWB_CAM		1
> +#define CLK_CAM_RAWB_CAMTG		2
> +#define CLK_CAM_RAWB_NR_CLK		3
> +
> +/* CAMSYS_YUVB */
> +
> +#define CLK_CAM_YUVB_LARBX		0
> +#define CLK_CAM_YUVB_CAM		1
> +#define CLK_CAM_YUVB_CAMTG		2
> +#define CLK_CAM_YUVB_NR_CLK		3
> +
> +/* CAMSYS_MRAW */
> +
> +#define CLK_CAM_MRAW_LARBX		0
> +#define CLK_CAM_MRAW_CAMTG		1
> +#define CLK_CAM_MRAW_MRAW0		2
> +#define CLK_CAM_MRAW_MRAW1		3
> +#define CLK_CAM_MRAW_MRAW2		4
> +#define CLK_CAM_MRAW_MRAW3		5
> +#define CLK_CAM_MRAW_NR_CLK		6
> +
> +/* CCUSYS */
> +
> +#define CLK_CCU_LARB18			0
> +#define CLK_CCU_AHB			1
> +#define CLK_CCU_CCU0			2
> +#define CLK_CCU_CCU1			3
> +#define CLK_CCU_NR_CLK			4
> +
> +/* VDECSYS_SOC */
> +
> +#define CLK_VDEC_SOC_LARB1		0
> +#define CLK_VDEC_SOC_LAT		1
> +#define CLK_VDEC_SOC_VDEC		2
> +#define CLK_VDEC_SOC_NR_CLK		3
> +
> +/* VDECSYS */
> +
> +#define CLK_VDEC_LARB1			0
> +#define CLK_VDEC_LAT			1
> +#define CLK_VDEC_VDEC			2
> +#define CLK_VDEC_NR_CLK			3
> +
> +/* VDECSYS_CORE1 */
> +
> +#define CLK_VDEC_CORE1_LARB1		0
> +#define CLK_VDEC_CORE1_LAT		1
> +#define CLK_VDEC_CORE1_VDEC		2
> +#define CLK_VDEC_CORE1_NR_CLK		3
> +
> +/* APUSYS_PLL */
> +
> +#define CLK_APUSYS_PLL_APUPLL		0
> +#define CLK_APUSYS_PLL_NPUPLL		1
> +#define CLK_APUSYS_PLL_APUPLL1		2
> +#define CLK_APUSYS_PLL_APUPLL2		3
> +#define CLK_APUSYS_PLL_NR_CLK		4
> +
> +/* VENCSYS */
> +
> +#define CLK_VENC_LARB			0
> +#define CLK_VENC_VENC			1
> +#define CLK_VENC_JPGENC			2
> +#define CLK_VENC_JPGDEC			3
> +#define CLK_VENC_JPGDEC_C1		4
> +#define CLK_VENC_GALS			5
> +#define CLK_VENC_NR_CLK			6
> +
> +/* VENCSYS_CORE1 */
> +
> +#define CLK_VENC_CORE1_LARB		0
> +#define CLK_VENC_CORE1_VENC		1
> +#define CLK_VENC_CORE1_JPGENC		2
> +#define CLK_VENC_CORE1_JPGDEC		3
> +#define CLK_VENC_CORE1_JPGDEC_C1	4
> +#define CLK_VENC_CORE1_GALS		5
> +#define CLK_VENC_CORE1_NR_CLK		6
> +
> +/* VDOSYS0 */
> +
> +#define CLK_VDO0_DISP_OVL0		0
> +#define CLK_VDO0_DISP_COLOR0		1
> +#define CLK_VDO0_DISP_COLOR1		2
> +#define CLK_VDO0_DISP_CCORR0		3
> +#define CLK_VDO0_DISP_CCORR1		4
> +#define CLK_VDO0_DISP_AAL0		5
> +#define CLK_VDO0_DISP_AAL1		6
> +#define CLK_VDO0_DISP_GAMMA0		7
> +#define CLK_VDO0_DISP_GAMMA1		8
> +#define CLK_VDO0_DISP_DITHER0		9
> +#define CLK_VDO0_DISP_DITHER1		10
> +#define CLK_VDO0_DISP_OVL1		11
> +#define CLK_VDO0_DISP_WDMA0		12
> +#define CLK_VDO0_DISP_WDMA1		13
> +#define CLK_VDO0_DISP_RDMA0		14
> +#define CLK_VDO0_DISP_RDMA1		15
> +#define CLK_VDO0_DSI0			16
> +#define CLK_VDO0_DSI1			17
> +#define CLK_VDO0_DSC_WRAP0		18
> +#define CLK_VDO0_VPP_MERGE0		19
> +#define CLK_VDO0_DP_INTF0		20
> +#define CLK_VDO0_DISP_MUTEX0		21
> +#define CLK_VDO0_DISP_IL_ROT0		22
> +#define CLK_VDO0_APB_BUS		23
> +#define CLK_VDO0_FAKE_ENG0		24
> +#define CLK_VDO0_FAKE_ENG1		25
> +#define CLK_VDO0_DL_ASYNC0		26
> +#define CLK_VDO0_DL_ASYNC1		27
> +#define CLK_VDO0_DL_ASYNC2		28
> +#define CLK_VDO0_DL_ASYNC3		29
> +#define CLK_VDO0_DL_ASYNC4		30
> +#define CLK_VDO0_DISP_MONITOR0		31
> +#define CLK_VDO0_DISP_MONITOR1		32
> +#define CLK_VDO0_DISP_MONITOR2		33
> +#define CLK_VDO0_DISP_MONITOR3		34
> +#define CLK_VDO0_DISP_MONITOR4		35
> +#define CLK_VDO0_SMI_GALS		36
> +#define CLK_VDO0_SMI_COMMON		37
> +#define CLK_VDO0_SMI_EMI		38
> +#define CLK_VDO0_SMI_IOMMU		39
> +#define CLK_VDO0_SMI_LARB		40
> +#define CLK_VDO0_SMI_RSI		41
> +#define CLK_VDO0_DSI0_DSI		42
> +#define CLK_VDO0_DSI1_DSI		43
> +#define CLK_VDO0_DP_INTF0_DP_INTF	44
> +#define CLK_VDO0_NR_CLK			45
> +
> +/* VDOSYS1 */
> +
> +#define CLK_VDO1_SMI_LARB2			0
> +#define CLK_VDO1_SMI_LARB3			1
> +#define CLK_VDO1_GALS				2
> +#define CLK_VDO1_FAKE_ENG0			3
> +#define CLK_VDO1_FAKE_ENG			4
> +#define CLK_VDO1_MDP_RDMA0			5
> +#define CLK_VDO1_MDP_RDMA1			6
> +#define CLK_VDO1_MDP_RDMA2			7
> +#define CLK_VDO1_MDP_RDMA3			8
> +#define CLK_VDO1_VPP_MERGE0			9
> +#define CLK_VDO1_VPP_MERGE1			10
> +#define CLK_VDO1_VPP_MERGE2			11
> +#define CLK_VDO1_VPP_MERGE3			12
> +#define CLK_VDO1_VPP_MERGE4			13
> +#define CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC		14
> +#define CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC		15
> +#define CLK_VDO1_DISP_MUTEX			16
> +#define CLK_VDO1_MDP_RDMA4			17
> +#define CLK_VDO1_MDP_RDMA5			18
> +#define CLK_VDO1_MDP_RDMA6			19
> +#define CLK_VDO1_MDP_RDMA7			20
> +#define CLK_VDO1_DP_INTF0_MM			21
> +#define CLK_VDO1_DPI0_MM			22
> +#define CLK_VDO1_DPI1_MM			23
> +#define CLK_VDO1_DISP_MONITOR			24
> +#define CLK_VDO1_MERGE0_DL_ASYNC		25
> +#define CLK_VDO1_MERGE1_DL_ASYNC		26
> +#define CLK_VDO1_MERGE2_DL_ASYNC		27
> +#define CLK_VDO1_MERGE3_DL_ASYNC		28
> +#define CLK_VDO1_MERGE4_DL_ASYNC		29
> +#define CLK_VDO1_VDO0_DSC_TO_VDO1_DL_ASYNC	30
> +#define CLK_VDO1_VDO0_MERGE_TO_VDO1_DL_ASYNC	31
> +#define CLK_VDO1_HDR_VDO_FE0			32
> +#define CLK_VDO1_HDR_GFX_FE0			33
> +#define CLK_VDO1_HDR_VDO_BE			34
> +#define CLK_VDO1_HDR_VDO_FE1			35
> +#define CLK_VDO1_HDR_GFX_FE1			36
> +#define CLK_VDO1_DISP_MIXER			37
> +#define CLK_VDO1_HDR_VDO_FE0_DL_ASYNC		38
> +#define CLK_VDO1_HDR_VDO_FE1_DL_ASYNC		39
> +#define CLK_VDO1_HDR_GFX_FE0_DL_ASYNC		40
> +#define CLK_VDO1_HDR_GFX_FE1_DL_ASYNC		41
> +#define CLK_VDO1_HDR_VDO_BE_DL_ASYNC		42
> +#define CLK_VDO1_DPI0				43
> +#define CLK_VDO1_DISP_MONITOR_DPI0		44
> +#define CLK_VDO1_DPI1				45
> +#define CLK_VDO1_DISP_MONITOR_DPI1		46
> +#define CLK_VDO1_DPINTF				47
> +#define CLK_VDO1_DISP_MONITOR_DPINTF		48
> +#define CLK_VDO1_26M_SLOW			49
> +#define CLK_VDO1_NR_CLK				50
> +
> +#endif /* _DT_BINDINGS_CLK_MT8195_H */
> -- 
> 2.18.0
> 
> 

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg
  2021-06-16 22:47 ` [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg Chun-Jie Chen
@ 2021-06-30  7:31   ` Chen-Yu Tsai
  2021-06-30 10:53     ` Matthias Brugger
  0 siblings, 1 reply; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-06-30  7:31 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group

On Thu, Jun 17, 2021 at 7:01 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> On MT8195, tuner_en_reg is moved to register offest 0x0.
> If we only judge by tuner_en_reg, it may lead to wrong address.
> Add tuner_en_bit to the check condition. And it has been confirmed,
> on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by
> clock square control.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

Though you might want to consider converting these types of checks into feature
flags.

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg
  2021-06-30  7:31   ` Chen-Yu Tsai
@ 2021-06-30 10:53     ` Matthias Brugger
  2021-06-30 11:09       ` Chen-Yu Tsai
  0 siblings, 1 reply; 59+ messages in thread
From: Matthias Brugger @ 2021-06-30 10:53 UTC (permalink / raw)
  To: Chen-Yu Tsai, Chun-Jie Chen
  Cc: Stephen Boyd, Nicolas Boichat, Rob Herring, linux-arm-kernel,
	linux-kernel, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group



On 30/06/2021 09:31, Chen-Yu Tsai wrote:
> On Thu, Jun 17, 2021 at 7:01 AM Chun-Jie Chen
> <chun-jie.chen@mediatek.com> wrote:
>>
>> On MT8195, tuner_en_reg is moved to register offest 0x0.
>> If we only judge by tuner_en_reg, it may lead to wrong address.
>> Add tuner_en_bit to the check condition. And it has been confirmed,
>> on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by
>> clock square control.
>>
>> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> 
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
> 
> Though you might want to consider converting these types of checks into feature
> flags.
> 

Yes I think adding a feature flag is the way to go. Luckily there are only a few
SoCs that will need updates at the same time.

Regards,
Matthias

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg
  2021-06-30 10:53     ` Matthias Brugger
@ 2021-06-30 11:09       ` Chen-Yu Tsai
  2021-06-30 11:43         ` Matthias Brugger
  0 siblings, 1 reply; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-06-30 11:09 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: Chun-Jie Chen, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group

On Wed, Jun 30, 2021 at 6:53 PM Matthias Brugger <matthias.bgg@gmail.com> wrote:
>
>
>
> On 30/06/2021 09:31, Chen-Yu Tsai wrote:
> > On Thu, Jun 17, 2021 at 7:01 AM Chun-Jie Chen
> > <chun-jie.chen@mediatek.com> wrote:
> >>
> >> On MT8195, tuner_en_reg is moved to register offest 0x0.
> >> If we only judge by tuner_en_reg, it may lead to wrong address.
> >> Add tuner_en_bit to the check condition. And it has been confirmed,
> >> on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by
> >> clock square control.
> >>
> >> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> >
> > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
> >
> > Though you might want to consider converting these types of checks into feature
> > flags.
> >
>
> Yes I think adding a feature flag is the way to go. Luckily there are only a few
> SoCs that will need updates at the same time.

I also see that the different clock modules are tied together using only clock
names written in the drivers, instead of clock references in the device tree.

Unfortunately reworking this would likely require a lot more work. I previously
did a bit of internal reworking for the sunxi drivers. While not the same, I
think the plumbing required is comparable.

ChenYu

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg
  2021-06-30 11:09       ` Chen-Yu Tsai
@ 2021-06-30 11:43         ` Matthias Brugger
  2021-07-01  4:02           ` Chen-Yu Tsai
  0 siblings, 1 reply; 59+ messages in thread
From: Matthias Brugger @ 2021-06-30 11:43 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Chun-Jie Chen, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group



On 30/06/2021 13:09, Chen-Yu Tsai wrote:
> On Wed, Jun 30, 2021 at 6:53 PM Matthias Brugger <matthias.bgg@gmail.com> wrote:
>>
>>
>>
>> On 30/06/2021 09:31, Chen-Yu Tsai wrote:
>>> On Thu, Jun 17, 2021 at 7:01 AM Chun-Jie Chen
>>> <chun-jie.chen@mediatek.com> wrote:
>>>>
>>>> On MT8195, tuner_en_reg is moved to register offest 0x0.
>>>> If we only judge by tuner_en_reg, it may lead to wrong address.
>>>> Add tuner_en_bit to the check condition. And it has been confirmed,
>>>> on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by
>>>> clock square control.
>>>>
>>>> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
>>>
>>> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
>>>
>>> Though you might want to consider converting these types of checks into feature
>>> flags.
>>>
>>
>> Yes I think adding a feature flag is the way to go. Luckily there are only a few
>> SoCs that will need updates at the same time.
> 
> I also see that the different clock modules are tied together using only clock
> names written in the drivers, instead of clock references in the device tree.
> 

Not sure I understand what you mean. Do you refer to something like [1]? That's
because the clock is probed by the DRM driver, as they share the same compatible
and IP block.

Regards,
Matthias

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/mediatek/clk-mt8173-mm.c?h=v5.13#n139

> Unfortunately reworking this would likely require a lot more work. I previously
> did a bit of internal reworking for the sunxi drivers. While not the same, I
> think the plumbing required is comparable.
> 
> ChenYu
> 

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg
  2021-06-30 11:43         ` Matthias Brugger
@ 2021-07-01  4:02           ` Chen-Yu Tsai
  0 siblings, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-01  4:02 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: Chun-Jie Chen, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group

"On Wed, Jun 30, 2021 at 7:43 PM Matthias Brugger
<matthias.bgg@gmail.com> wrote:
> On 30/06/2021 13:09, Chen-Yu Tsai wrote:
> > On Wed, Jun 30, 2021 at 6:53 PM Matthias Brugger <matthias.bgg@gmail.com> wrote:
> >> On 30/06/2021 09:31, Chen-Yu Tsai wrote:
> >>> On Thu, Jun 17, 2021 at 7:01 AM Chun-Jie Chen
> >>> <chun-jie.chen@mediatek.com> wrote:
> >>>>
> >>>> On MT8195, tuner_en_reg is moved to register offest 0x0.
> >>>> If we only judge by tuner_en_reg, it may lead to wrong address.
> >>>> Add tuner_en_bit to the check condition. And it has been confirmed,
> >>>> on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by
> >>>> clock square control.
> >>>>
> >>>> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> >>>
> >>> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
> >>>
> >>> Though you might want to consider converting these types of checks into feature
> >>> flags.
> >>>
> >>
> >> Yes I think adding a feature flag is the way to go. Luckily there are only a few
> >> SoCs that will need updates at the same time.
> >
> > I also see that the different clock modules are tied together using only clock
> > names written in the drivers, instead of clock references in the device tree.
> >
>
> Not sure I understand what you mean. Do you refer to something like [1]? That's
> because the clock is probed by the DRM driver, as they share the same compatible
> and IP block.

In the example driver you mentioned, most of the registered clocks have the same
parent clock, "mm_sel". This clock is from another hardware block,
"topckgen" [1].

The two are linked together by looking up the clock name. The link should be
explicitly described in the device tree, instead of implicitly by some name
found in two drivers. The consuming driver can fetch the clock name via
of_clk_get_parent_name(), or be migrated to use `struct clk_parent_data`,
which allows specifying local (to the DT node) clock names or clk indices
as parent clk references.

What's more confusing is that the mmsys node actually has "assigned-clocks"
properties [2] referencing the "mm_sel" clock, but not "clock" properties
referencing the same clock. On the surface this looks like the hardware
is trying to configure clocks that it doesn't use.

Also, Maxime Ripard made the argument before that "assigned-clock-rates"
doesn't give any real guarantees that the clock rate won't change. A
better method is to request and "lock" the clock rate in the consuming
driver.

So overall I think there are many improvements that can be made to the
Mediatek clk drivers. They aren't real blockers to new drivers though,
and I think each would take some effort and coordination across all
the SoCs.


Regards
ChenYu

[1] https://elixir.bootlin.com/linux/latest/source/drivers/clk/mediatek/clk-mt8173.c#L545
[2] https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/mediatek/mt8173.dtsi#L996


> Regards,
> Matthias
>
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/mediatek/clk-mt8173-mm.c?h=v5.13#n139
>
> > Unfortunately reworking this would likely require a lot more work. I previously
> > did a bit of internal reworking for the sunxi drivers. While not the same, I
> > think the plumbing required is comparable.
> >
> > ChenYu
> >

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 04/22] clk: mediatek: Add MT8195 basic clocks support
  2021-06-16 22:47 ` [PATCH 04/22] clk: mediatek: Add MT8195 basic clocks support Chun-Jie Chen
@ 2021-07-02 11:44   ` Chen-Yu Tsai
       [not found]     ` <1626913060.1546.4.camel@mtksdaap41>
  0 siblings, 1 reply; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-02 11:44 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group

Hi,


On Thu, Jun 17, 2021 at 7:05 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 basic clock providers, include topckgen, apmixedsys,
> infracfg_ao and pericfg_ao.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  drivers/clk/mediatek/Kconfig      |    8 +
>  drivers/clk/mediatek/Makefile     |    1 +
>  drivers/clk/mediatek/clk-mt8195.c | 1958 +++++++++++++++++++++++++++++
>  3 files changed, 1967 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt8195.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 576babd86f98..6707aba3d500 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -580,6 +580,14 @@ config COMMON_CLK_MT8192_VENCSYS
>         help
>           This driver supports MediaTek MT8192 vencsys clocks.
>
> +config COMMON_CLK_MT8195
> +       bool "Clock driver for MediaTek MT8195"
> +       depends on ARM64 || COMPILE_TEST
> +       select COMMON_CLK_MEDIATEK
> +       default ARM64
> +       help
> +         This driver supports MediaTek MT8195 basic clocks.
> +
>  config COMMON_CLK_MT8516
>         bool "Clock driver for MediaTek MT8516"
>         depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 15bc045f0b71..f8002d8966e1 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -80,5 +80,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk-mt8192-msdc.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
> +obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195.o
>  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
>  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c
> new file mode 100644
> index 000000000000..aea9ebe4c051
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195.c
> @@ -0,0 +1,1958 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-mux.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +
> +static DEFINE_SPINLOCK(mt8195_clk_lock);
> +
> +static const struct mtk_fixed_clk top_fixed_clks[] = {
> +       FIXED_CLK(CLK_TOP_IN_DGI, "in_dgi", NULL, 165000000),
> +       FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 248000000),
> +       FIXED_CLK(CLK_TOP_ULPOSC2, "ulposc2", NULL, 326000000),
> +       FIXED_CLK(CLK_TOP_MEM_466M, "mem_466m", NULL, 533000000),
> +       FIXED_CLK(CLK_TOP_MPHONE_SLAVE_B, "mphone_slave_b", NULL, 49152000),
> +       FIXED_CLK(CLK_TOP_PEXTP_PIPE, "pextp_pipe", NULL, 250000000),
> +       FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL, "ufs_rx_symbol", NULL, 166000000),
> +       FIXED_CLK(CLK_TOP_UFS_TX_SYMBOL, "ufs_tx_symbol", NULL, 166000000),
> +       FIXED_CLK(CLK_TOP_SSUSB_U3PHY_P1_P_P0, "ssusb_u3phy_p1_p_p0", NULL, 131000000),
> +       FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL1, "ufs_rx_symbol1", NULL, 166000000),
> +       FIXED_CLK(CLK_TOP_FPC, "fpc", NULL, 50000000),
> +       FIXED_CLK(CLK_TOP_HDMIRX_P, "hdmirx_p", NULL, 594000000),

I assume these are fixed PLLs? They should have inputs (parents).

Moreover, at least ULPOSC and ULPOSC2 look like they are in APMIXEDSYS

> +};
> +
> +static const struct mtk_fixed_factor top_early_divs[] = {
> +       FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
> +};
> +
> +static const struct mtk_fixed_factor top_divs[] = {
> +       FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m", 1, 52),
> +       FACTOR(CLK_TOP_IN_DGI_D2, "in_dgi_d2", "in_dgi", 1, 2),
> +       FACTOR(CLK_TOP_IN_DGI_D4, "in_dgi_d4", "in_dgi", 1, 4),
> +       FACTOR(CLK_TOP_IN_DGI_D6, "in_dgi_d6", "in_dgi", 1, 6),
> +       FACTOR(CLK_TOP_IN_DGI_D8, "in_dgi_d8", "in_dgi", 1, 8),
> +       FACTOR(CLK_TOP_MFGPLL_OPP, "mfgpll_opp", "mfgpll", 1, 1),
> +       FACTOR(CLK_TOP_MAINPLL, "mainpll_ck", "mainpll", 1, 1),

Why are this and other 1:1 factor clks needed? They look like placeholders.
Please remove them.

> +       FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll_ck", 1, 3),
> +       FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll_ck", 1, 4),
> +       FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2),
> +       FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4),
> +       FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8),
> +       FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll_ck", 1, 5),
> +       FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
> +       FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
> +       FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8),
> +       FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll_ck", 1, 6),
> +       FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2),
> +       FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4),
> +       FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8),
> +       FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll_ck", 1, 7),
> +       FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
> +       FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
> +       FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8),
> +       FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll_ck", 1, 9),
> +       FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1),
> +       FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 2),
> +       FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1, 3),
> +       FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll_ck", 1, 4),
> +       FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2),
> +       FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4),
> +       FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8),
> +       FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1, 5),
> +       FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
> +       FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
> +       FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
> +       FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll_ck", 1, 6),
> +       FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2),
> +       FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4),
> +       FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8),
> +       FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16),
> +       FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1, 7),
> +       FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13),
> +       FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
> +       FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
> +       FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
> +       FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
> +       FACTOR(CLK_TOP_IMGPLL, "imgpll_ck", "imgpll", 1, 1),
> +       FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
> +       FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1, 3),
> +       FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4),
> +       FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
> +       FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1, 3),
> +       FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4),
> +       FACTOR(CLK_TOP_APLL3, "apll3_ck", "apll3", 1, 1),
> +       FACTOR(CLK_TOP_APLL3_D4, "apll3_d4", "apll3_ck", 1, 4),
> +       FACTOR(CLK_TOP_APLL4, "apll4_ck", "apll4", 1, 1),
> +       FACTOR(CLK_TOP_APLL4_D4, "apll4_d4", "apll4_ck", 1, 4),
> +       FACTOR(CLK_TOP_APLL5, "apll5_ck", "apll5", 1, 1),
> +       FACTOR(CLK_TOP_APLL5_D4, "apll5_d4", "apll5_ck", 1, 4),
> +       FACTOR(CLK_TOP_HDMIRX_APLL, "hdmirx_apll_ck", "hdmirx_apll", 1, 1),
> +       FACTOR(CLK_TOP_HDMIRX_APLL_D3, "hdmirx_apll_d3", "hdmirx_apll_ck", 1, 3),
> +       FACTOR(CLK_TOP_HDMIRX_APLL_D4, "hdmirx_apll_d4", "hdmirx_apll_ck", 1, 4),
> +       FACTOR(CLK_TOP_HDMIRX_APLL_D6, "hdmirx_apll_d6", "hdmirx_apll_ck", 1, 6),
> +       FACTOR(CLK_TOP_NNAPLL, "nnapll_ck", "nnapll", 1, 1),
> +       FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
> +       FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_ck", 1, 4),
> +       FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
> +       FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
> +       FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll_ck", 1, 5),
> +       FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
> +       FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
> +       FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_ck", 1, 6),
> +       FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2),
> +       FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll_ck", 1, 7),
> +       FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll_ck", 1, 9),
> +       FACTOR(CLK_TOP_TVDPLL1, "tvdpll1_ck", "tvdpll1", 1, 1),
> +       FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1_ck", 1, 2),
> +       FACTOR(CLK_TOP_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1_ck", 1, 4),
> +       FACTOR(CLK_TOP_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1_ck", 1, 8),
> +       FACTOR(CLK_TOP_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1_ck", 1, 16),
> +       FACTOR(CLK_TOP_TVDPLL2, "tvdpll2_ck", "tvdpll2", 1, 1),
> +       FACTOR(CLK_TOP_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2_ck", 1, 2),
> +       FACTOR(CLK_TOP_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2_ck", 1, 4),
> +       FACTOR(CLK_TOP_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2_ck", 1, 8),
> +       FACTOR(CLK_TOP_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2_ck", 1, 16),
> +       FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
> +       FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
> +       FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4),
> +       FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll_ck", 1, 16),
> +       FACTOR(CLK_TOP_ETHPLL, "ethpll_ck", "ethpll", 1, 1),
> +       FACTOR(CLK_TOP_ETHPLL_D2, "ethpll_d2", "ethpll_ck", 1, 2),
> +       FACTOR(CLK_TOP_ETHPLL_D8, "ethpll_d8", "ethpll_ck", 1, 8),
> +       FACTOR(CLK_TOP_ETHPLL_D10, "ethpll_d10", "ethpll_ck", 1, 10),
> +       FACTOR(CLK_TOP_DGIPLL, "dgipll_ck", "dgipll", 1, 1),
> +       FACTOR(CLK_TOP_DGIPLL_D2, "dgipll_d2", "dgipll_ck", 1, 2),
> +       FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1),
> +       FACTOR(CLK_TOP_ULPOSC_D2, "ulposc_d2", "ulposc", 1, 2),
> +       FACTOR(CLK_TOP_ULPOSC_D4, "ulposc_d4", "ulposc", 1, 4),
> +       FACTOR(CLK_TOP_ULPOSC_D7, "ulposc_d7", "ulposc", 1, 7),
> +       FACTOR(CLK_TOP_ULPOSC_D8, "ulposc_d8", "ulposc", 1, 8),
> +       FACTOR(CLK_TOP_ULPOSC_D10, "ulposc_d10", "ulposc", 1, 10),
> +       FACTOR(CLK_TOP_ULPOSC_D16, "ulposc_d16", "ulposc", 1, 16),
> +       FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1),
> +       FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll_ck", 1, 2),
> +       FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll_ck", 1, 4),
> +       FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll_ck", 1, 8),
> +};
> +
> +static const char * const axi_parents[] = {
> +       "clk26m",
> +       "mainpll_d4_d4",
> +       "mainpll_d7_d2",
> +       "mainpll_d4_d2",
> +       "mainpll_d5_d2",
> +       "mainpll_d6_d2",
> +       "ulposc_d4"
> +};
> +
> +static const char * const spm_parents[] = {
> +       "clk26m",
> +       "ulposc_d10",
> +       "mainpll_d7_d4",
> +       "clk32k"
> +};
> +
> +static const char * const bus_aximem_parents[] = {
> +       "clk26m",
> +       "mainpll_d7_d2",
> +       "mainpll_d4_d2",
> +       "mainpll_d5_d2",
> +       "mainpll_d6"
> +};
> +
> +static const char * const vpp_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d2",
> +       "mainpll_d5_d2",
> +       "mmpll_d6_d2",
> +       "univpll_d5_d2",
> +       "univpll_d4_d2",
> +       "mmpll_d4_d2",
> +       "mmpll_d7",
> +       "univpll_d6",
> +       "mainpll_d4",
> +       "mmpll_d5",
> +       "tvdpll1_ck",
> +       "tvdpll2_ck",
> +       "univpll_d4",
> +       "mmpll_d4"
> +};
> +
> +static const char * const ethdr_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d2",
> +       "mainpll_d5_d2",
> +       "mmpll_d6_d2",
> +       "univpll_d5_d2",
> +       "univpll_d4_d2",
> +       "mmpll_d4_d2",
> +       "mmpll_d7",
> +       "univpll_d6",
> +       "mainpll_d4",
> +       "mmpll_d5_d4",
> +       "tvdpll1_ck",
> +       "tvdpll2_ck",
> +       "univpll_d4",
> +       "mmpll_d4"
> +};
> +
> +static const char * const ipe_parents[] = {
> +       "clk26m",
> +       "imgpll_ck",
> +       "mainpll_d4",
> +       "mmpll_d6",
> +       "univpll_d6",
> +       "mainpll_d6",
> +       "mmpll_d4_d2",
> +       "univpll_d4_d2",
> +       "mainpll_d4_d2",
> +       "mmpll_d6_d2",
> +       "univpll_d5_d2"
> +};
> +
> +static const char * const cam_parents[] = {
> +       "clk26m",
> +       "mainpll_d4",
> +       "mmpll_d4",
> +       "univpll_d4",
> +       "univpll_d5",
> +       "univpll_d6",
> +       "mmpll_d7",
> +       "univpll_d4_d2",
> +       "mainpll_d4_d2",
> +       "imgpll_ck"
> +};
> +
> +static const char * const ccu_parents[] = {
> +       "clk26m",
> +       "univpll_d6",
> +       "mainpll_d4_d2",
> +       "mainpll_d4",
> +       "univpll_d5",
> +       "mainpll_d6",
> +       "mmpll_d6",
> +       "mmpll_d7",
> +       "univpll_d4_d2",
> +       "univpll_d7"
> +};
> +
> +static const char * const img_parents[] = {
> +       "clk26m",
> +       "imgpll_ck",
> +       "univpll_d4",
> +       "mainpll_d4",
> +       "univpll_d5",
> +       "mmpll_d6",
> +       "univpll_d6",
> +       "mainpll_d6",
> +       "mmpll_d4_d2",
> +       "univpll_d4_d2",
> +       "mainpll_d4_d2",
> +       "univpll_d5_d2"
> +};
> +
> +static const char * const camtm_parents[] = {
> +       "clk26m",
> +       "univpll_d4_d4",
> +       "univpll_d6_d2",
> +       "univpll_d6_d4"
> +};
> +
> +static const char * const dsp_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d2",
> +       "univpll_d4_d2",
> +       "univpll_d5",
> +       "univpll_d4",
> +       "mmpll_d4",
> +       "mainpll_d3",
> +       "univpll_d3"
> +};
> +
> +static const char * const dsp1_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d2",
> +       "mainpll_d4_d2",
> +       "univpll_d5",
> +       "mmpll_d5",
> +       "univpll_d4",
> +       "mainpll_d3",
> +       "univpll_d3"
> +};
> +
> +static const char * const dsp2_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d2",
> +       "mainpll_d4_d2",
> +       "univpll_d5",
> +       "mmpll_d5",
> +       "univpll_d4",
> +       "mainpll_d3",
> +       "univpll_d3"
> +};
> +
> +static const char * const dsp3_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d2",
> +       "mainpll_d4_d2",
> +       "univpll_d5",
> +       "mmpll_d5",
> +       "univpll_d4",
> +       "mainpll_d3",
> +       "univpll_d3"
> +};
> +
> +static const char * const dsp4_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d2",
> +       "univpll_d4_d2",
> +       "mainpll_d4",
> +       "univpll_d4",
> +       "mmpll_d4",
> +       "mainpll_d3",
> +       "univpll_d3"
> +};
> +
> +static const char * const dsp5_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d2",
> +       "univpll_d4_d2",
> +       "mainpll_d4",
> +       "univpll_d4",
> +       "mmpll_d4",
> +       "mainpll_d3",
> +       "univpll_d3"
> +};
> +
> +static const char * const dsp6_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d2",
> +       "univpll_d4_d2",
> +       "mainpll_d4",
> +       "univpll_d4",
> +       "mmpll_d4",
> +       "mainpll_d3",
> +       "univpll_d3"
> +};
> +
> +static const char * const dsp7_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d2",
> +       "univpll_d4_d2",
> +       "univpll_d5",
> +       "univpll_d4",
> +       "mmpll_d4",
> +       "mainpll_d3",
> +       "univpll_d3"
> +};

If dsp~dsp7_parents are all the same, please merge them and share one
instance. And since they are located a bit far from the clock definitions
in this file, please add comments describing which clocks share the same
set of parents.

> +
> +static const char * const ipu_if_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d2",
> +       "univpll_d5_d2",
> +       "mainpll_d4_d2",
> +       "mainpll_d6",
> +       "univpll_d5",
> +       "univpll_d4",
> +       "mmpll_d4"
> +};
> +
> +static const char * const mfg_parents[] = {
> +       "clk26m",
> +       "mainpll_d5_d2",
> +       "univpll_d6",
> +       "univpll_d7"
> +};
> +
> +static const char * const camtg_parents[] = {
> +       "clk26m",
> +       "univpll_192m_d8",
> +       "univpll_d6_d8",
> +       "univpll_192m_d4",
> +       "univpll_d6_d16",
> +       "clk26m_d2",
> +       "univpll_192m_d16",
> +       "univpll_192m_d32"
> +};
> +
> +static const char * const camtg2_parents[] = {
> +       "clk26m",
> +       "univpll_192m_d8",
> +       "univpll_d6_d8",
> +       "univpll_192m_d4",
> +       "univpll_d6_d16",
> +       "clk26m_d2",
> +       "univpll_192m_d16",
> +       "univpll_192m_d32"
> +};
> +
> +static const char * const camtg3_parents[] = {
> +       "clk26m",
> +       "univpll_192m_d8",
> +       "univpll_d6_d8",
> +       "univpll_192m_d4",
> +       "univpll_d6_d16",
> +       "clk26m_d2",
> +       "univpll_192m_d16",
> +       "univpll_192m_d32"
> +};
> +
> +static const char * const camtg4_parents[] = {
> +       "clk26m",
> +       "univpll_192m_d8",
> +       "univpll_d6_d8",
> +       "univpll_192m_d4",
> +       "univpll_d6_d16",
> +       "clk26m_d2",
> +       "univpll_192m_d16",
> +       "univpll_192m_d32"
> +};
> +
> +static const char * const camtg5_parents[] = {
> +       "clk26m",
> +       "univpll_192m_d8",
> +       "univpll_d6_d8",
> +       "univpll_192m_d4",
> +       "univpll_d6_d16",
> +       "clk26m_d2",
> +       "univpll_192m_d16",
> +       "univpll_192m_d32"
> +};

Same goes for camtg* ...

> +
> +static const char * const uart_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d8"
> +};
> +
> +static const char * const spi_parents[] = {
> +       "clk26m",
> +       "mainpll_d5_d4",
> +       "mainpll_d6_d4",
> +       "msdcpll_d4",
> +       "univpll_d6_d2",
> +       "mainpll_d6_d2",
> +       "mainpll_d4_d4",
> +       "univpll_d5_d4"
> +};
> +
> +static const char * const spis_parents[] = {
> +       "clk26m",
> +       "univpll_d6",
> +       "mainpll_d6",
> +       "univpll_d4_d2",
> +       "univpll_d6_d2",
> +       "univpll_d4_d4",
> +       "univpll_d6_d4",
> +       "mainpll_d7_d4"
> +};
> +
> +static const char * const msdc50_0_h_parents[] = {
> +       "clk26m",
> +       "mainpll_d4_d2",
> +       "mainpll_d6_d2"
> +};
> +
> +static const char * const msdc50_0_parents[] = {
> +       "clk26m",
> +       "msdcpll_ck",
> +       "msdcpll_d2",
> +       "univpll_d4_d4",
> +       "mainpll_d6_d2",
> +       "univpll_d4_d2"
> +};
> +
> +static const char * const msdc30_1_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d2",
> +       "mainpll_d6_d2",
> +       "mainpll_d7_d2",
> +       "msdcpll_d2"
> +};
> +
> +static const char * const msdc30_2_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d2",
> +       "mainpll_d6_d2",
> +       "mainpll_d7_d2",
> +       "msdcpll_d2"
> +};

And msdc30_* ...

> +
> +static const char * const intdir_parents[] = {
> +       "clk26m",
> +       "univpll_d6",
> +       "mainpll_d4",
> +       "univpll_d4"
> +};
> +
> +static const char * const aud_intbus_parents[] = {
> +       "clk26m",
> +       "mainpll_d4_d4",
> +       "mainpll_d7_d4"
> +};
> +
> +static const char * const audio_h_parents[] = {
> +       "clk26m",
> +       "univpll_d7",
> +       "apll1_ck",
> +       "apll2_ck"
> +};
> +
> +static const char * const pwrap_ulposc_parents[] = {
> +       "ulposc_d10",
> +       "clk26m",
> +       "ulposc_d4",
> +       "ulposc_d7",
> +       "ulposc_d8",
> +       "ulposc_d16",
> +       "mainpll_d4_d8",
> +       "univpll_d5_d8"
> +};
> +
> +static const char * const atb_parents[] = {
> +       "clk26m",
> +       "mainpll_d4_d2",
> +       "mainpll_d5_d2"
> +};
> +
> +static const char * const pwrmcu_parents[] = {
> +       "clk26m",
> +       "mainpll_d7_d2",
> +       "mainpll_d6_d2",
> +       "mainpll_d5_d2",
> +       "mainpll_d9",
> +       "mainpll_d4_d2"
> +};
> +
> +static const char * const dp_parents[] = {
> +       "clk26m",
> +       "tvdpll1_d2",
> +       "tvdpll2_d2",
> +       "tvdpll1_d4",
> +       "tvdpll2_d4",
> +       "tvdpll1_d8",
> +       "tvdpll2_d8",
> +       "tvdpll1_d16",
> +       "tvdpll2_d16"
> +};
> +
> +static const char * const edp_parents[] = {
> +       "clk26m",
> +       "tvdpll1_d2",
> +       "tvdpll2_d2",
> +       "tvdpll1_d4",
> +       "tvdpll2_d4",
> +       "tvdpll1_d8",
> +       "tvdpll2_d8",
> +       "tvdpll1_d16",
> +       "tvdpll2_d16"
> +};
> +
> +static const char * const dpi_parents[] = {
> +       "clk26m",
> +       "tvdpll1_d2",
> +       "tvdpll2_d2",
> +       "tvdpll1_d4",
> +       "tvdpll2_d4",
> +       "tvdpll1_d8",
> +       "tvdpll2_d8",
> +       "tvdpll1_d16",
> +       "tvdpll2_d16"
> +};

And the display output encoder clocks ...

> +
> +static const char * const disp_pwm0_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d4",
> +       "ulposc_d2",
> +       "ulposc_d4",
> +       "ulposc_d16"
> +};
> +
> +static const char * const disp_pwm1_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d4",
> +       "ulposc_d2",
> +       "ulposc_d4",
> +       "ulposc_d16"
> +};

And disp_pwm* ...

> +
> +static const char * const usb_parents[] = {
> +       "clk26m",
> +       "univpll_d5_d4",
> +       "univpll_d6_d4",
> +       "univpll_d5_d2"
> +};
> +
> +static const char * const ssusb_xhci_parents[] = {
> +       "clk26m",
> +       "univpll_d5_d4",
> +       "univpll_d6_d4",
> +       "univpll_d5_d2"
> +};
> +
> +static const char * const usb_1p_parents[] = {
> +       "clk26m",
> +       "univpll_d5_d4",
> +       "univpll_d6_d4",
> +       "univpll_d5_d2"
> +};
> +
> +static const char * const ssusb_xhci_1p_parents[] = {
> +       "clk26m",
> +       "univpll_d5_d4",
> +       "univpll_d6_d4",
> +       "univpll_d5_d2"
> +};
> +
> +static const char * const usb_2p_parents[] = {
> +       "clk26m",
> +       "univpll_d5_d4",
> +       "univpll_d6_d4",
> +       "univpll_d5_d2"
> +};
> +
> +static const char * const ssusb_xhci_2p_parents[] = {
> +       "clk26m",
> +       "univpll_d5_d4",
> +       "univpll_d6_d4",
> +       "univpll_d5_d2"
> +};
> +
> +static const char * const usb_3p_parents[] = {
> +       "clk26m",
> +       "univpll_d5_d4",
> +       "univpll_d6_d4",
> +       "univpll_d5_d2"
> +};
> +
> +static const char * const ssusb_xhci_3p_parents[] = {
> +       "clk26m",
> +       "univpll_d5_d4",
> +       "univpll_d6_d4",
> +       "univpll_d5_d2"
> +};

And all the USB clocks ...

> +
> +static const char * const i2c_parents[] = {
> +       "clk26m",
> +       "mainpll_d4_d8",
> +       "univpll_d5_d4"
> +};
> +
> +static const char * const seninf_parents[] = {
> +       "clk26m",
> +       "univpll_d4_d4",
> +       "univpll_d6_d2",
> +       "univpll_d4_d2",
> +       "univpll_d7",
> +       "univpll_d6",
> +       "mmpll_d6",
> +       "univpll_d5"
> +};
> +
> +static const char * const seninf1_parents[] = {
> +       "clk26m",
> +       "univpll_d4_d4",
> +       "univpll_d6_d2",
> +       "univpll_d4_d2",
> +       "univpll_d7",
> +       "univpll_d6",
> +       "mmpll_d6",
> +       "univpll_d5"
> +};
> +
> +static const char * const seninf2_parents[] = {
> +       "clk26m",
> +       "univpll_d4_d4",
> +       "univpll_d6_d2",
> +       "univpll_d4_d2",
> +       "univpll_d7",
> +       "univpll_d6",
> +       "mmpll_d6",
> +       "univpll_d5"
> +};
> +
> +static const char * const seninf3_parents[] = {
> +       "clk26m",
> +       "univpll_d4_d4",
> +       "univpll_d6_d2",
> +       "univpll_d4_d2",
> +       "univpll_d7",
> +       "univpll_d6",
> +       "mmpll_d6",
> +       "univpll_d5"
> +};

And seninf* ...

> +
> +static const char * const gcpu_parents[] = {
> +       "clk26m",
> +       "mainpll_d6",
> +       "univpll_d4_d2",
> +       "mmpll_d5_d2",
> +       "univpll_d5_d2"
> +};
> +
> +static const char * const dxcc_parents[] = {
> +       "clk26m",
> +       "mainpll_d4_d2",
> +       "mainpll_d4_d4",
> +       "mainpll_d4_d8"
> +};
> +
> +static const char * const dpmaif_parents[] = {
> +       "clk26m",
> +       "univpll_d4_d4",
> +       "mainpll_d6",
> +       "mainpll_d4_d2",
> +       "univpll_d4_d2"
> +};
> +
> +static const char * const aes_ufsfde_parents[] = {
> +       "clk26m",
> +       "mainpll_d4_d2",
> +       "mainpll_d6",
> +       "mainpll_d4_d4",
> +       "univpll_d4_d2",
> +       "univpll_d6"
> +};
> +
> +static const char * const ufs_parents[] = {
> +       "clk26m",
> +       "mainpll_d4_d4",
> +       "mainpll_d4_d8",
> +       "univpll_d4_d4",
> +       "mainpll_d6_d2",
> +       "univpll_d6_d2",
> +       "msdcpll_d2"
> +};
> +
> +static const char * const ufs_tick1us_parents[] = {
> +       "clk26m_d52",
> +       "clk26m"
> +};
> +
> +static const char * const ufs_mp_sap_parents[] = {
> +       "clk26m",
> +       "msdcpll_d16"
> +};
> +
> +static const char * const venc_parents[] = {
> +       "clk26m",
> +       "mmpll_d4_d2",
> +       "mainpll_d6",
> +       "univpll_d4_d2",
> +       "mainpll_d4_d2",
> +       "univpll_d6",
> +       "mmpll_d6",
> +       "mainpll_d5_d2",
> +       "mainpll_d6_d2",
> +       "mmpll_d9",
> +       "univpll_d4_d4",
> +       "mainpll_d4",
> +       "univpll_d4",
> +       "univpll_d5",
> +       "univpll_d5_d2",
> +       "mainpll_d5"
> +};
> +
> +static const char * const vdec_parents[] = {
> +       "clk26m",
> +       "mainpll_d5_d2",
> +       "mmpll_d6_d2",
> +       "univpll_d4_d2",
> +       "mmpll_d4_d2",
> +       "mainpll_d5",
> +       "mmpll_d6",
> +       "mmpll_d5",
> +       "vdecpll_ck",
> +       "univpll_d4",
> +       "mmpll_d4",
> +       "univpll_d6_d2",
> +       "mmpll_d9",
> +       "univpll_d6",
> +       "univpll_d5",
> +       "mainpll_d4"
> +};
> +
> +static const char * const pwm_parents[] = {
> +       "clk26m",
> +       "univpll_d4_d8"
> +};
> +
> +static const char * const spmi_p_mst_parents[] = {
> +       "clk26m",
> +       "clk26m_d2",
> +       "ulposc_d8",
> +       "ulposc_d10",
> +       "ulposc_d16",
> +       "ulposc_d7",
> +       "clk32k",
> +       "mainpll_d7_d8",
> +       "mainpll_d6_d8",
> +       "mainpll_d5_d8"
> +};
> +
> +static const char * const spmi_m_mst_parents[] = {
> +       "clk26m",
> +       "clk26m_d2",
> +       "ulposc_d8",
> +       "ulposc_d10",
> +       "ulposc_d16",
> +       "ulposc_d7",
> +       "clk32k",
> +       "mainpll_d7_d8",
> +       "mainpll_d6_d8",
> +       "mainpll_d5_d8"
> +};

And spmi_* ...

> +
> +static const char * const tl_parents[] = {
> +       "clk26m",
> +       "univpll_d5_d4",
> +       "mainpll_d4_d4"
> +};
> +
> +static const char * const tl_p1_parents[] = {
> +       "clk26m",
> +       "univpll_d5_d4",
> +       "mainpll_d4_d4"
> +};

And these two ...

> +
> +static const char * const aes_msdcfde_parents[] = {
> +       "clk26m",
> +       "mainpll_d4_d2",
> +       "mainpll_d6",
> +       "mainpll_d4_d4",
> +       "univpll_d4_d2",
> +       "univpll_d6"
> +};

This could be merged with aes_ufsfde, and be called aes_fde_parents.

> +
> +static const char * const dsi_occ_parents[] = {
> +       "clk26m",
> +       "mainpll_d6_d2",
> +       "univpll_d5_d2",
> +       "univpll_d4_d2"
> +};
> +
> +static const char * const wpe_vpp_parents[] = {
> +       "clk26m",
> +       "mainpll_d5_d2",
> +       "mmpll_d6_d2",
> +       "univpll_d5_d2",
> +       "mainpll_d4_d2",
> +       "univpll_d4_d2",
> +       "mmpll_d4_d2",
> +       "mainpll_d6",
> +       "mmpll_d7",
> +       "univpll_d6",
> +       "mainpll_d5",
> +       "univpll_d5",
> +       "mainpll_d4",
> +       "tvdpll1_ck",
> +       "univpll_d4"
> +};
> +
> +static const char * const hdcp_parents[] = {
> +       "clk26m",
> +       "univpll_d4_d8",
> +       "mainpll_d5_d8",
> +       "univpll_d6_d4"
> +};
> +
> +static const char * const hdcp_24m_parents[] = {
> +       "clk26m",
> +       "univpll_192m_d4",
> +       "univpll_192m_d8",
> +       "univpll_d6_d8"
> +};
> +
> +static const char * const hd20_dacr_ref_parents[] = {
> +       "clk26m",
> +       "univpll_d4_d2",
> +       "univpll_d4_d4",
> +       "univpll_d4_d8"
> +};
> +
> +static const char * const hd20_hdcp_c_parents[] = {
> +       "clk26m",
> +       "msdcpll_d4",
> +       "univpll_d4_d8",
> +       "univpll_d6_d8"
> +};
> +
> +static const char * const hdmi_xtal_parents[] = {
> +       "clk26m",
> +       "clk26m_d2"
> +};
> +
> +static const char * const hdmi_apb_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d4",
> +       "msdcpll_d2"
> +};
> +
> +static const char * const snps_eth_250m_parents[] = {
> +       "clk26m",
> +       "ethpll_d2"
> +};
> +
> +static const char * const snps_eth_62p4m_ptp_parents[] = {
> +       "apll2_d3",
> +       "apll1_d3",
> +       "clk26m",
> +       "ethpll_d8"
> +};
> +
> +static const char * const snps_eth_50m_rmii_parents[] = {
> +       "clk26m",
> +       "ethpll_d10"
> +};
> +
> +static const char * const dgi_out_parents[] = {
> +       "clk26m",
> +       "dgipll_ck",
> +       "dgipll_d2",
> +       "in_dgi",
> +       "in_dgi_d2",
> +       "mmpll_d4_d4"
> +};
> +
> +static const char * const nna0_parents[] = {
> +       "clk26m",
> +       "nnapll_ck",
> +       "univpll_d4",
> +       "mainpll_d4",
> +       "univpll_d5",
> +       "mmpll_d6",
> +       "univpll_d6",
> +       "mainpll_d6",
> +       "mmpll_d4_d2",
> +       "univpll_d4_d2",
> +       "mainpll_d4_d2",
> +       "mmpll_d6_d2"
> +};
> +
> +static const char * const nna1_parents[] = {
> +       "clk26m",
> +       "nnapll_ck",
> +       "univpll_d4",
> +       "mainpll_d4",
> +       "univpll_d5",
> +       "mmpll_d6",
> +       "univpll_d6",
> +       "mainpll_d6",
> +       "mmpll_d4_d2",
> +       "univpll_d4_d2",
> +       "mainpll_d4_d2",
> +       "mmpll_d6_d2"
> +};

You could merge nna0 and nna1. Datasheet mentions nnapll_s0 and nnapll_1.
I'm not sure what they refer to.

> +
> +static const char * const adsp_parents[] = {
> +       "clk26m",
> +       "clk26m_d2",
> +       "mainpll_d6",
> +       "mainpll_d5_d2",
> +       "univpll_d4_d4",
> +       "univpll_d4",
> +       "univpll_d6",
> +       "ulposc",
> +       "adsppll_ck",
> +       "adsppll_d2",
> +       "adsppll_d4",
> +       "adsppll_d8"
> +};
> +
> +static const char * const asm_h_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d4",
> +       "univpll_d6_d2",
> +       "mainpll_d5_d2"
> +};
> +
> +static const char * const asm_m_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d4",
> +       "univpll_d6_d2",
> +       "mainpll_d5_d2"
> +};
> +
> +static const char * const asm_l_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d4",
> +       "univpll_d6_d2",
> +       "mainpll_d5_d2"
> +};

Merge asm_*.

> +
> +static const char * const apll1_parents[] = {
> +       "clk26m",
> +       "apll1_d4"
> +};
> +
> +static const char * const apll2_parents[] = {
> +       "clk26m",
> +       "apll2_d4"
> +};
> +
> +static const char * const apll3_parents[] = {
> +       "clk26m",
> +       "apll3_d4"
> +};
> +
> +static const char * const apll4_parents[] = {
> +       "clk26m",
> +       "apll4_d4"
> +};
> +
> +static const char * const apll5_parents[] = {
> +       "clk26m",
> +       "apll5_d4"
> +};
> +
> +static const char * const i2so1_m_parents[] = {
> +       "clk26m",
> +       "apll1_ck",
> +       "apll2_ck",
> +       "apll3_ck",
> +       "apll4_ck",
> +       "apll5_ck",
> +       "hdmirx_apll_ck"
> +};
> +
> +static const char * const i2so2_m_parents[] = {
> +       "clk26m",
> +       "apll1_ck",
> +       "apll2_ck",
> +       "apll3_ck",
> +       "apll4_ck",
> +       "apll5_ck",
> +       "hdmirx_apll_ck"
> +};
> +
> +static const char * const i2si1_m_parents[] = {
> +       "clk26m",
> +       "apll1_ck",
> +       "apll2_ck",
> +       "apll3_ck",
> +       "apll4_ck",
> +       "apll5_ck",
> +       "hdmirx_apll_ck"
> +};
> +
> +static const char * const i2si2_m_parents[] = {
> +       "clk26m",
> +       "apll1_ck",
> +       "apll2_ck",
> +       "apll3_ck",
> +       "apll4_ck",
> +       "apll5_ck",
> +       "hdmirx_apll_ck"
> +};
> +
> +static const char * const dptx_m_parents[] = {
> +       "clk26m",
> +       "apll1_ck",
> +       "apll2_ck",
> +       "apll3_ck",
> +       "apll4_ck",
> +       "apll5_ck",
> +       "hdmirx_apll_ck"
> +};
> +
> +static const char * const aud_iec_parents[] = {
> +       "clk26m",
> +       "apll1_ck",
> +       "apll2_ck",
> +       "apll3_ck",
> +       "apll4_ck",
> +       "apll5_ck",
> +       "hdmirx_apll_ck"
> +};

Merge all the digital audio ones, starting from i2so1_m.

> +
> +static const char * const a1sys_hp_parents[] = {
> +       "clk26m",
> +       "apll1_d4"
> +};
> +
> +static const char * const a2sys_parents[] = {
> +       "clk26m",
> +       "apll2_d4"
> +};
> +
> +static const char * const a3sys_parents[] = {
> +       "clk26m",
> +       "apll3_d4",
> +       "apll4_d4",
> +       "apll5_d4",
> +       "hdmirx_apll_d3",
> +       "hdmirx_apll_d4",
> +       "hdmirx_apll_d6"
> +};
> +
> +static const char * const a4sys_parents[] = {
> +       "clk26m",
> +       "apll3_d4",
> +       "apll4_d4",
> +       "apll5_d4",
> +       "hdmirx_apll_d3",
> +       "hdmirx_apll_d4",
> +       "hdmirx_apll_d6"
> +};

Merge a3sys and a4sys.

> +
> +static const char * const spinfi_b_parents[] = {
> +       "clk26m",
> +       "univpll_d6_d8",
> +       "univpll_d5_d8",
> +       "mainpll_d4_d8",
> +       "mainpll_d7_d4",
> +       "mainpll_d6_d4",
> +       "univpll_d6_d4",
> +       "univpll_d5_d4"
> +};
> +
> +static const char * const nfi1x_parents[] = {
> +       "clk26m",
> +       "univpll_d5_d4",
> +       "mainpll_d7_d4",
> +       "mainpll_d6_d4",
> +       "univpll_d6_d4",
> +       "mainpll_d4_d4",
> +       "mainpll_d7_d2",
> +       "mainpll_d6_d2"
> +};
> +
> +static const char * const ecc_parents[] = {
> +       "clk26m",
> +       "mainpll_d4_d4",
> +       "mainpll_d5_d2",
> +       "mainpll_d4_d2",
> +       "mainpll_d6",
> +       "univpll_d6"
> +};
> +
> +static const char * const audio_local_bus_parents[] = {
> +       "clk26m",
> +       "clk26m_d2",
> +       "mainpll_d4_d4",
> +       "mainpll_d7_d2",
> +       "mainpll_d4_d2",
> +       "mainpll_d5_d2",
> +       "mainpll_d6_d2",
> +       "mainpll_d7",
> +       "univpll_d6",
> +       "ulposc",
> +       "ulposc_d4",
> +       "ulposc_d2"
> +};
> +
> +static const char * const spinor_parents[] = {
> +       "clk26m",

Datasheet says first parent is "univpll_d5_d8". Please check with hardware
engineers. If the datasheet is wrong please add a comment saying so.

> +       "clk26m_d2",
> +       "mainpll_d7_d8",
> +       "univpll_d6_d8"
> +};
> +
> +static const char * const dvio_dgi_ref_parents[] = {
> +       "clk26m",
> +       "in_dgi",
> +       "in_dgi_d2",
> +       "in_dgi_d4",
> +       "in_dgi_d6",
> +       "in_dgi_d8",
> +       "mmpll_d4_d4"
> +};
> +
> +static const char * const srck_parents[] = {
> +       "ulposc_d10",
> +       "clk26m"
> +};
> +
> +static const char * const rsvd1_parents[] = {
> +       "clk26m",
> +       "mainpll_d4_d4",
> +       "mainpll_d5_d4",
> +       "mainpll_d6_d4",
> +       "mainpll_d7_d4",
> +       "univpll_d6_d4",

These are completely different from the datasheet. Please check.

> +       "ulposc",
> +       "ulposc2"
> +};
> +
> +static const char * const mfg_fast_parents[] = {
> +       "mfg_sel",
> +       "mfgpll_opp"
> +};
> +
> +static const struct mtk_mux top_mtk_muxes[] = {
> +       /* CLK_CFG_0 */
> +       MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel",

Please drop the "_sel" suffix from the clock names. It would have made
sense if this were purely a mux, and there was another clock gate. But
since the driver combines the two components into one representation,
please just drop the suffix that implies just a mux. This goes for all
clocks in the series and also the macro bindings.

> +               axi_parents, 0x020, 0x024, 0x028, 0, 3, 7, 0x04, 0, CLK_IS_CRITICAL),
> +       MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel",
> +               spm_parents, 0x020, 0x024, 0x028, 8, 2, 15, 0x04, 1, CLK_IS_CRITICAL),

Where is the SCP clock?

> +       MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM_SEL, "bus_aximem_sel",
> +               bus_aximem_parents, 0x020, 0x024, 0x028, 24, 3, 31, 0x04, 3, CLK_IS_CRITICAL),
> +       /* CLK_CFG_1 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP_SEL, "vpp_sel",
> +               vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR_SEL, "ethdr_sel",
> +               ethdr_parents, 0x02C, 0x030, 0x034, 8, 4, 15, 0x04, 5),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel",
> +               ipe_parents, 0x02C, 0x030, 0x034, 16, 4, 23, 0x04, 6),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel",
> +               cam_parents, 0x02C, 0x030, 0x034, 24, 4, 31, 0x04, 7),
> +       /* CLK_CFG_2 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel",
> +               ccu_parents, 0x038, 0x03C, 0x040, 0, 4, 7, 0x04, 8),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG_SEL, "img_sel",
> +               img_parents, 0x038, 0x03C, 0x040, 8, 4, 15, 0x04, 9),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel",
> +               camtm_parents, 0x038, 0x03C, 0x040, 16, 2, 23, 0x04, 10),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel",
> +               dsp_parents, 0x038, 0x03C, 0x040, 24, 3, 31, 0x04, 11),
> +       /* CLK_CFG_3 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1_SEL, "dsp1_sel",
> +               dsp1_parents, 0x044, 0x048, 0x04C, 0, 3, 7, 0x04, 12),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2_SEL, "dsp2_sel",
> +               dsp2_parents, 0x044, 0x048, 0x04C, 8, 3, 15, 0x04, 13),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3_SEL, "dsp3_sel",
> +               dsp3_parents, 0x044, 0x048, 0x04C, 16, 3, 23, 0x04, 14),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP4_SEL, "dsp4_sel",
> +               dsp4_parents, 0x044, 0x048, 0x04C, 24, 3, 31, 0x04, 15),
> +       /* CLK_CFG_4 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5_SEL, "dsp5_sel",
> +               dsp5_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x04, 16),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP6_SEL, "dsp6_sel",
> +               dsp6_parents, 0x050, 0x054, 0x058, 8, 3, 15, 0x04, 17),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel",
> +               dsp7_parents, 0x050, 0x054, 0x058, 16, 3, 23, 0x04, 18),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF_SEL, "ipu_if_sel",
> +               ipu_if_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x04, 19),
> +       /* CLK_CFG_5 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel",
> +               mfg_parents, 0x05C, 0x060, 0x064, 0, 2, 7, 0x04, 20),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
> +               camtg_parents, 0x05C, 0x060, 0x064, 8, 3, 15, 0x04, 21),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
> +               camtg2_parents, 0x05C, 0x060, 0x064, 16, 3, 23, 0x04, 22),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel",
> +               camtg3_parents, 0x05C, 0x060, 0x064, 24, 3, 31, 0x04, 23),
> +       /* CLK_CFG_6 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4_SEL, "camtg4_sel",
> +               camtg4_parents, 0x068, 0x06C, 0x070, 0, 3, 7, 0x04, 24),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5_SEL, "camtg5_sel",
> +               camtg5_parents, 0x068, 0x06C, 0x070, 8, 3, 15, 0x04, 25),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel",
> +               uart_parents, 0x068, 0x06C, 0x070, 16, 1, 23, 0x04, 26),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel",
> +               spi_parents, 0x068, 0x06C, 0x070, 24, 3, 31, 0x04, 27),
> +       /* CLK_CFG_7 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIS_SEL, "spis_sel",
> +               spis_parents, 0x074, 0x078, 0x07C, 0, 3, 7, 0x04, 28),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel",
> +               msdc50_0_h_parents, 0x074, 0x078, 0x07C, 8, 2, 15, 0x04, 29),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
> +               msdc50_0_parents, 0x074, 0x078, 0x07C, 16, 3, 23, 0x04, 30),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
> +               msdc30_1_parents, 0x074, 0x078, 0x07C, 24, 3, 31, 0x04, 31),
> +       /* CLK_CFG_8 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
> +               msdc30_2_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x08, 0),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR_SEL, "intdir_sel",
> +               intdir_parents, 0x080, 0x084, 0x088, 8, 2, 15, 0x08, 1),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
> +               aud_intbus_parents, 0x080, 0x084, 0x088, 16, 2, 23, 0x08, 2),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, "audio_h_sel",
> +               audio_h_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x08, 3),
> +       /* CLK_CFG_9 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL, "pwrap_ulposc_sel",
> +               pwrap_ulposc_parents, 0x08C, 0x090, 0x094, 0, 3, 7, 0x08, 4),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel",
> +               atb_parents, 0x08C, 0x090, 0x094, 8, 2, 15, 0x08, 5),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRMCU_SEL, "pwrmcu_sel",
> +               pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DP_SEL, "dp_sel",
> +               dp_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7),
> +       /* CLK_CFG_10 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP_SEL, "edp_sel",
> +               edp_parents, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI_SEL, "dpi_sel",
> +               dpi_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0_SEL, "disp_pwm0_sel",
> +               disp_pwm0_parents, 0x098, 0x09C, 0x0A0, 16, 3, 23, 0x08, 10),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM1_SEL, "disp_pwm1_sel",
> +               disp_pwm1_parents, 0x098, 0x09C, 0x0A0, 24, 3, 31, 0x08, 11),
> +       /* CLK_CFG_11 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SEL, "usb_sel",

The datasheet lists these as "usb_top" and "usb_top_Xp". Please keep the name
the same as the datasheet so it is easy to search for. Also note the discrepency
between the macro name and the clock name. Same goes for the three other USB
clocks.

> +               usb_parents, 0x0A4, 0x0A8, 0x0AC, 0, 2, 7, 0x08, 12),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel",
> +               ssusb_xhci_parents, 0x0A4, 0x0A8, 0x0AC, 8, 2, 15, 0x08, 13),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_1P_SEL, "usb_1p_sel",
> +               usb_1p_parents, 0x0A4, 0x0A8, 0x0AC, 16, 2, 23, 0x08, 14),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_1P_SEL, "ssusb_xhci_1p_sel",
> +               ssusb_xhci_1p_parents, 0x0A4, 0x0A8, 0x0AC, 24, 2, 31, 0x08, 15),
> +       /* CLK_CFG_12 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_2P_SEL, "usb_2p_sel",
> +               usb_2p_parents, 0x0B0, 0x0B4, 0x0B8, 0, 2, 7, 0x08, 16),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P_SEL, "ssusb_xhci_2p_sel",
> +               ssusb_xhci_2p_parents, 0x0B0, 0x0B4, 0x0B8, 8, 2, 15, 0x08, 17),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_3P_SEL, "usb_3p_sel",
> +               usb_3p_parents, 0x0B0, 0x0B4, 0x0B8, 16, 2, 23, 0x08, 18),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P_SEL, "ssusb_xhci_3p_sel",
> +               ssusb_xhci_3p_parents, 0x0B0, 0x0B4, 0x0B8, 24, 2, 31, 0x08, 19),
> +       /* CLK_CFG_13 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel",
> +               i2c_parents, 0x0BC, 0x0C0, 0x0C4, 0, 2, 7, 0x08, 20),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel",
> +               seninf_parents, 0x0BC, 0x0C0, 0x0C4, 8, 3, 15, 0x08, 21),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, "seninf1_sel",
> +               seninf1_parents, 0x0BC, 0x0C0, 0x0C4, 16, 3, 23, 0x08, 22),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2_SEL, "seninf2_sel",
> +               seninf2_parents, 0x0BC, 0x0C0, 0x0C4, 24, 3, 31, 0x08, 23),
> +       /* CLK_CFG_14 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3_SEL, "seninf3_sel",
> +               seninf3_parents, 0x0C8, 0x0CC, 0x0D0, 0, 3, 7, 0x08, 24),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, "gcpu_sel",
> +               gcpu_parents, 0x0C8, 0x0CC, 0x0D0, 8, 3, 15, 0x08, 25),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel",
> +               dxcc_parents, 0x0C8, 0x0CC, 0x0D0, 16, 2, 23, 0x08, 26),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_SEL, "dpmaif_sel",
> +               dpmaif_parents, 0x0C8, 0x0CC, 0x0D0, 24, 3, 31, 0x08, 27),
> +       /* CLK_CFG_15 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, "aes_ufsfde_sel",
> +               aes_ufsfde_parents, 0x0D4, 0x0D8, 0x0DC, 0, 3, 7, 0x08, 28),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_SEL, "ufs_sel",
> +               ufs_parents, 0x0D4, 0x0D8, 0x0DC, 8, 3, 15, 0x08, 29),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_TICK1US_SEL, "ufs_tick1us_sel",
> +               ufs_tick1us_parents, 0x0D4, 0x0D8, 0x0DC, 16, 1, 23, 0x08, 30),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_MP_SAP_SEL, "ufs_mp_sap_sel",
> +               ufs_mp_sap_parents, 0x0D4, 0x0D8, 0x0DC, 24, 1, 31, 0x08, 31),
> +       /* CLK_CFG_16 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel",
> +               venc_parents, 0x0E0, 0x0E4, 0x0E8, 0, 4, 7, 0x0C, 0),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel",
> +               vdec_parents, 0x0E0, 0x0E4, 0x0E8, 8, 4, 15, 0x0C, 1),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel",
> +               pwm_parents, 0x0E0, 0x0E4, 0x0E8, 16, 1, 23, 0x0C, 2),

MCU clock? Not sure what it's supposed to be called since the naming has a
slightly different format.

If you are skipping clocks, please leave a comment in the list explaining
why.

> +       /* CLK_CFG_17 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST_SEL, "spmi_p_mst_sel",
> +               spmi_p_mst_parents, 0x0EC, 0x0F0, 0x0F4, 0, 4, 7, 0x0C, 4),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST_SEL, "spmi_m_mst_sel",
> +               spmi_m_mst_parents, 0x0EC, 0x0F0, 0x0F4, 8, 4, 15, 0x0C, 5),

DVFSRC clock?

> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_SEL, "tl_sel",
> +               tl_parents, 0x0EC, 0x0F0, 0x0F4, 24, 2, 31, 0x0C, 7),
> +       /* CLK_CFG_18 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_P1_SEL, "tl_p1_sel",
> +               tl_p1_parents, 0x0F8, 0x0FC, 0x0100, 0, 2, 7, 0x0C, 8),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel",
> +               aes_msdcfde_parents, 0x0F8, 0x0FC, 0x0100, 8, 3, 15, 0x0C, 9),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC_SEL, "dsi_occ_sel",
> +               dsi_occ_parents, 0x0F8, 0x0FC, 0x0100, 16, 2, 23, 0x0C, 10),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE_VPP_SEL, "wpe_vpp_sel",
> +               wpe_vpp_parents, 0x0F8, 0x0FC, 0x0100, 24, 4, 31, 0x0C, 11),
> +       /* CLK_CFG_19 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_SEL, "hdcp_sel",
> +               hdcp_parents, 0x0104, 0x0108, 0x010C, 0, 2, 7, 0x0C, 12),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel",
> +               hdcp_24m_parents, 0x0104, 0x0108, 0x010C, 8, 2, 15, 0x0C, 13),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_HD20_DACR_REF_SEL, "hd20_dacr_ref_sel",
> +               hd20_dacr_ref_parents, 0x0104, 0x0108, 0x010C, 16, 2, 23, 0x0C, 14),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_HD20_HDCP_C_SEL, "hd20_hdcp_c_sel",
> +               hd20_hdcp_c_parents, 0x0104, 0x0108, 0x010C, 24, 2, 31, 0x0C, 15),
> +       /* CLK_CFG_20 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_XTAL_SEL, "hdmi_xtal_sel",
> +               hdmi_xtal_parents, 0x0110, 0x0114, 0x0118, 0, 1, 7, 0x0C, 16),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_APB_SEL, "hdmi_apb_sel",
> +               hdmi_apb_parents, 0x0110, 0x0114, 0x0118, 8, 2, 15, 0x0C, 17),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M_SEL, "snps_eth_250m_sel",
> +               snps_eth_250m_parents, 0x0110, 0x0114, 0x0118, 16, 1, 23, 0x0C, 18),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP_SEL, "snps_eth_62p4m_ptp_sel",
> +               snps_eth_62p4m_ptp_parents, 0x0110, 0x0114, 0x0118, 24, 2, 31, 0x0C, 19),
> +       /* CLK_CFG_21 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII_SEL, "snps_eth_50m_rmii_sel",
> +               snps_eth_50m_rmii_parents, 0x011C, 0x0120, 0x0124, 0, 1, 7, 0x0C, 20),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DGI_OUT_SEL, "dgi_out_sel",
> +               dgi_out_parents, 0x011C, 0x0120, 0x0124, 8, 3, 15, 0x0C, 21),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA0_SEL, "nna0_sel",
> +               nna0_parents, 0x011C, 0x0120, 0x0124, 16, 4, 23, 0x0C, 22),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA1_SEL, "nna1_sel",
> +               nna1_parents, 0x011C, 0x0120, 0x0124, 24, 4, 31, 0x0C, 23),
> +       /* CLK_CFG_22 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_SEL, "adsp_sel",
> +               adsp_parents, 0x0128, 0x012C, 0x0130, 0, 4, 7, 0x0C, 24),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_H_SEL, "asm_h_sel",
> +               asm_h_parents, 0x0128, 0x012C, 0x0130, 8, 2, 15, 0x0C, 25),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_M_SEL, "asm_m_sel",
> +               asm_m_parents, 0x0128, 0x012C, 0x0130, 16, 2, 23, 0x0C, 26),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_L_SEL, "asm_l_sel",
> +               asm_l_parents, 0x0128, 0x012C, 0x0130, 24, 2, 31, 0x0C, 27),
> +       /* CLK_CFG_23 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1_SEL, "apll1_sel",
> +               apll1_parents, 0x0134, 0x0138, 0x013C, 0, 1, 7, 0x0C, 28),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2_SEL, "apll2_sel",
> +               apll2_parents, 0x0134, 0x0138, 0x013C, 8, 1, 15, 0x0C, 29),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL3_SEL, "apll3_sel",
> +               apll3_parents, 0x0134, 0x0138, 0x013C, 16, 1, 23, 0x0C, 30),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL4_SEL, "apll4_sel",
> +               apll4_parents, 0x0134, 0x0138, 0x013C, 24, 1, 31, 0x0C, 31),
> +       /* CLK_CFG_24 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5_SEL, "apll5_sel",
> +               apll5_parents, 0x0140, 0x0144, 0x0148, 0, 1, 7, 0x010, 0),

For the APLLs, you will need to differentiate them from the actual PLLs in
the APMIXEDSYS block.

> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1_M_SEL, "i2so1_m_sel",
> +               i2so1_m_parents, 0x0140, 0x0144, 0x0148, 8, 3, 15, 0x010, 1),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2_M_SEL, "i2so2_m_sel",
> +               i2so2_m_parents, 0x0140, 0x0144, 0x0148, 16, 3, 23, 0x010, 2),

I2SO4_M?

> +       /* CLK_CFG_25 */

I2SO5_M?

> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1_M_SEL, "i2si1_m_sel",
> +               i2si1_m_parents, 0x014C, 0x0150, 0x0154, 8, 3, 15, 0x010, 5),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2_M_SEL, "i2si2_m_sel",
> +               i2si2_m_parents, 0x014C, 0x0150, 0x0154, 16, 3, 23, 0x010, 6),

I2SI4_M?

> +       /* CLK_CFG_26 */

I2SI5_M?

> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX_M_SEL, "dptx_m_sel",
> +               dptx_m_parents, 0x0158, 0x015C, 0x0160, 8, 3, 15, 0x010, 9),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC_SEL, "aud_iec_sel",
> +               aud_iec_parents, 0x0158, 0x015C, 0x0160, 16, 3, 23, 0x010, 10),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel",
> +               a1sys_hp_parents, 0x0158, 0x015C, 0x0160, 24, 1, 31, 0x010, 11),
> +       /* CLK_CFG_27 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS_SEL, "a2sys_sel",
> +               a2sys_parents, 0x0164, 0x0168, 0x016C, 0, 1, 7, 0x010, 12),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS_SEL, "a3sys_sel",
> +               a3sys_parents, 0x0164, 0x0168, 0x016C, 8, 3, 15, 0x010, 13),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS_SEL, "a4sys_sel",
> +               a4sys_parents, 0x0164, 0x0168, 0x016C, 16, 3, 23, 0x010, 14),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_B_SEL, "spinfi_b_sel",
> +               spinfi_b_parents, 0x0164, 0x0168, 0x016C, 24, 3, 31, 0x010, 15),
> +       /* CLK_CFG_28 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel",
> +               nfi1x_parents, 0x0170, 0x0174, 0x0178, 0, 3, 7, 0x010, 16),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, "ecc_sel",
> +               ecc_parents, 0x0170, 0x0174, 0x0178, 8, 3, 15, 0x010, 17),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS_SEL, "audio_local_bus_sel",
> +               audio_local_bus_parents, 0x0170, 0x0174, 0x0178, 16, 4, 23, 0x010, 18),
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR_SEL, "spinor_sel",
> +               spinor_parents, 0x0170, 0x0174, 0x0178, 24, 2, 31, 0x010, 19),
> +       /* CLK_CFG_29 */
> +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DVIO_DGI_REF_SEL, "dvio_dgi_ref_sel",
> +               dvio_dgi_ref_parents, 0x017C, 0x0180, 0x0184, 0, 3, 7, 0x010, 20),

ULPOSC and ULPOSC_CORE?

> +       MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK_SEL, "srck_sel",
> +               srck_parents, 0x017C, 0x0180, 0x0184, 24, 1, 31, 0x010, 23, CLK_IS_CRITICAL),

What happened to CLK_CFG_30~36?

> +       /* CLK_CFG_37 */
> +       MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_RSVD1_SEL, "rsvd1_sel",
> +               rsvd1_parents, 0x01DC, 0x01E0, 0x01E4, 0, 3, 7, 0x014, 20, CLK_IS_CRITICAL),

What about the other three?

> +};
> +
> +static struct mtk_composite top_muxes[] = {
> +       /* CLK_MISC_CFG_3 */
> +       MUX(CLK_TOP_MFG_FAST_SEL, "mfg_fast_sel", mfg_fast_parents, 0x0250, 8, 1),
> +};
> +
> +static const struct mtk_composite top_adj_divs[] = {
> +       DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2si1_m_sel", 0x0320, 0, 0x0328, 8, 0),
> +       DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2si2_m_sel", 0x0320, 1, 0x0328, 8, 8),
> +       DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "i2so1_m_sel", 0x0320, 2, 0x0328, 8, 16),
> +       DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "i2so2_m_sel", 0x0320, 3, 0x0328, 8, 24),
> +       DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "aud_iec_sel", 0x0320, 4, 0x0334, 8, 0),

What about 5~8?

> +       DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "dptx_m_sel", 0x0320, 9, 0x0338, 8, 8),
> +};
> +
> +static const struct mtk_gate_regs infra_ao0_cg_regs = {
> +       .set_ofs = 0x80,
> +       .clr_ofs = 0x84,
> +       .sta_ofs = 0x90,
> +};
> +
> +static const struct mtk_gate_regs infra_ao1_cg_regs = {
> +       .set_ofs = 0x88,
> +       .clr_ofs = 0x8c,
> +       .sta_ofs = 0x94,
> +};
> +
> +static const struct mtk_gate_regs infra_ao2_cg_regs = {
> +       .set_ofs = 0xa4,
> +       .clr_ofs = 0xa8,
> +       .sta_ofs = 0xac,
> +};
> +
> +static const struct mtk_gate_regs infra_ao3_cg_regs = {
> +       .set_ofs = 0xc0,
> +       .clr_ofs = 0xc4,
> +       .sta_ofs = 0xc8,
> +};
> +
> +static const struct mtk_gate_regs infra_ao4_cg_regs = {
> +       .set_ofs = 0xe0,
> +       .clr_ofs = 0xe4,
> +       .sta_ofs = 0xe8,
> +};
> +
> +#define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag)                \
> +       GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
> +               &mtk_clk_gate_ops_setclr, _flag)
> +
> +#define GATE_INFRA_AO0(_id, _name, _parent, _shift)    \
> +       GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
> +
> +#define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag)               \
> +       GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
> +               &mtk_clk_gate_ops_setclr, _flag)
> +
> +#define GATE_INFRA_AO1(_id, _name, _parent, _shift)    \
> +       GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
> +
> +#define GATE_INFRA_AO2(_id, _name, _parent, _shift)                    \
> +       GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag)               \
> +       GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \
> +               &mtk_clk_gate_ops_setclr, _flag)
> +
> +#define GATE_INFRA_AO3(_id, _name, _parent, _shift)    \
> +       GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
> +
> +#define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag)               \
> +       GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao4_cg_regs, _shift, \
> +               &mtk_clk_gate_ops_setclr, _flag)
> +
> +#define GATE_INFRA_AO4(_id, _name, _parent, _shift)    \
> +       GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, 0)
> +
> +static const struct mtk_gate infra_ao_clks[] = {
> +       /* INFRA_AO0 */
> +       GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, "infra_ao_pmic_tmr", "pwrap_ulposc_sel", 0),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, "infra_ao_pmic_ap", "pwrap_ulposc_sel", 1),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, "infra_ao_pmic_md", "pwrap_ulposc_sel", 2),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, "infra_ao_pmic_conn", "pwrap_ulposc_sel", 3),
> +       GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ, "infra_ao_sej", "axi_sel", 5, CLK_IS_CRITICAL),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, "infra_ao_apxgpt", "axi_sel", 6),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_GCE, "infra_ao_gce", "axi_sel", 8),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_GCE2, "infra_ao_gce2", "axi_sel", 9),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_THERM, "infra_ao_therm", "axi_sel", 10),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_PWM_H, "infra_ao_pwm_h", "axi_sel", 15),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, "infra_ao_pwm1", "pwm_sel", 16),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, "infra_ao_pwm2", "pwm_sel", 17),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, "infra_ao_pwm3", "pwm_sel", 18),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, "infra_ao_pwm4", "pwm_sel", 19),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_PWM, "infra_ao_pwm", "pwm_sel", 21),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_UART0, "infra_ao_uart0", "uart_sel", 22),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_UART1, "infra_ao_uart1", "uart_sel", 23),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_UART2, "infra_ao_uart2", "uart_sel", 24),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_UART3, "infra_ao_uart3", "uart_sel", 25),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_UART4, "infra_ao_uart4", "uart_sel", 26),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, "infra_ao_gce_26m", "clk26m", 27),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_cq_dma_fpc", "fpc", 28),
> +       GATE_INFRA_AO0(CLK_INFRA_AO_UART5, "infra_ao_uart5", "uart_sel", 29),
> +       /* INFRA_AO1 */
> +       GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "clk26m", 0),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 1),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "msdc50_0_h_sel", 2),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "axi_sel", 4),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_CG1_MSDC2, "infra_ao_cg1_msdc2", "axi_sel", 5),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, "infra_ao_msdc0_src", "msdc50_0_sel", 6),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, "infra_ao_trng", "axi_sel", 9),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, "infra_ao_auxadc", "clk26m", 10),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, "infra_ao_cpum", "axi_sel", 11),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_32K, "infra_ao_hdmi_32k", "clk32k", 12),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_H, "infra_ao_cec_66m_h", "axi_sel", 13),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_IRRX, "infra_ao_irrx", "axi_sel", 14),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_26M, "infra_ao_pcie_tl_26m", "clk26m", 15),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, "infra_ao_msdc1_src", "msdc30_1_sel", 16),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_B, "infra_ao_cec_66m_b", "axi_sel", 17),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, "infra_ao_pcie_tl_96m", "tl_sel", 18),
> +       GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DEVICE_APC, "infra_ao_device_apc", "axi_sel", 20,
> +               CLK_IS_CRITICAL),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_H, "infra_ao_ecc_66m_h", "axi_sel", 23),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, "infra_ao_debugsys", "axi_sel", 24),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, "infra_ao_audio", "axi_sel", 25),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_32K, "infra_ao_pcie_tl_32k", "clk32k", 26),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, "infra_ao_dbg_trace", "axi_sel", 29),
> +       GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, "infra_ao_dramc_f26m", "clk26m", 31),
> +       /* INFRA_AO2 */
> +       GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, "infra_ao_irtx", "axi_sel", 0),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB, "infra_ao_ssusb", "usb_sel", 1),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, "infra_ao_disp_pwm", "disp_pwm0_sel", 2),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_B, "infra_ao_cldma_b", "axi_sel", 3),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_B, "infra_ao_audio_26m_b", "clk26m", 4),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spi_sel", 6),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, "infra_ao_spi2", "spi_sel", 9),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, "infra_ao_spi3", "spi_sel", 10),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_SYS, "infra_ao_unipro_sys", "ufs_sel", 11),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_TICK, "infra_ao_unipro_tick", "ufs_tick1us_sel", 12),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_UFS_MP_SAP_B, "infra_ao_ufs_mp_sap_b", "ufs_mp_sap_sel", 13),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_PWRMCU, "infra_ao_pwrmcu", "pwrmcu_sel", 15),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_PWRMCU_BUS_H, "infra_ao_pwrmcu_bus_h", "axi_sel", 17),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_APDMA_B, "infra_ao_apdma_b", "axi_sel", 18),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "spi_sel", 25),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "spi_sel", 26),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, "infra_ao_cq_dma", "axi_sel", 27),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_AES_UFSFDE, "infra_ao_aes_ufsfde", "ufs_sel", 28),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_AES, "infra_ao_aes", "aes_ufsfde_sel", 29),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_UFS_TICK, "infra_ao_ufs_tick", "ufs_tick1us_sel", 30),
> +       GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_XHCI, "infra_ao_ssusb_xhci", "ssusb_xhci_sel", 31),
> +       /* INFRA_AO3 */
> +       GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, "infra_ao_msdc0_self", "msdc50_0_sel", 0),
> +       GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SELF, "infra_ao_msdc1_self", "msdc50_0_sel", 1),
> +       GATE_INFRA_AO3(CLK_INFRA_AO_MSDC2_SELF, "infra_ao_msdc2_self", "msdc50_0_sel", 2),
> +       GATE_INFRA_AO3(CLK_INFRA_AO_I2S_DMA, "infra_ao_i2s_dma", "axi_sel", 5),
> +       GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, "infra_ao_ap_msdc0", "msdc50_0_sel", 7),
> +       GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, "infra_ao_md_msdc0", "msdc50_0_sel", 8),
> +       GATE_INFRA_AO3(CLK_INFRA_AO_CG3_MSDC2, "infra_ao_cg3_msdc2", "msdc30_2_sel", 9),
> +       GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, "infra_ao_gcpu", "gcpu_sel", 10),
> +       GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_PERI_26M, "infra_ao_pcie_peri_26m", "clk26m", 15),
> +       GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_B, "infra_ao_gcpu_66m_b", "axi_sel", 16),
> +       GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_B, "infra_ao_gcpu_133m_b", "axi_sel", 17),
> +       GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, "infra_ao_disp_pwm1", "disp_pwm1_sel", 20),
> +       GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, "infra_ao_fbist2fpc", "msdc50_0_sel", 24),
> +       GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_DEVICE_APC_SYNC, "infra_ao_device_apc_sync", "axi_sel",
> +               25, CLK_IS_CRITICAL),
> +       GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_P1_PERI_26M, "infra_ao_pcie_p1_peri_26m", "clk26m", 26),
> +       GATE_INFRA_AO3(CLK_INFRA_AO_SPIS0, "infra_ao_spis0", "spis_sel", 28),
> +       GATE_INFRA_AO3(CLK_INFRA_AO_SPIS1, "infra_ao_spis1", "spis_sel", 29),
> +       /* INFRA_AO4 */
> +       GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_133M_M_PERI, "infra_ao_133m_m_peri", "axi_sel", 0,
> +               CLK_IS_CRITICAL),
> +       GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_66M_M_PERI, "infra_ao_66m_m_peri", "spi_sel", 1,
> +               CLK_IS_CRITICAL),
> +       GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P0, "infra_ao_pcie_pl_p_250m_p0", "pextp_pipe",
> +               7),
> +       GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P1, "infra_ao_pcie_pl_p_250m_p1",
> +               "ssusb_u3phy_p1_p_p0", 8),
> +       GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_P1_TL_96M, "infra_ao_pcie_p1_tl_96m", "tl_p1_sel", 17),
> +       GATE_INFRA_AO4(CLK_INFRA_AO_AES_MSDCFDE_0P, "infra_ao_aes_msdcfde_0p", "aes_msdcfde_sel",
> +               18),
> +       GATE_INFRA_AO4(CLK_INFRA_AO_UFS_TX_SYMBOL, "infra_ao_ufs_tx_symbol", "ufs_tx_symbol", 22),
> +       GATE_INFRA_AO4(CLK_INFRA_AO_UFS_RX_SYMBOL, "infra_ao_ufs_rx_symbol", "ufs_rx_symbol", 23),
> +       GATE_INFRA_AO4(CLK_INFRA_AO_UFS_RX_SYMBOL1, "infra_ao_ufs_rx_symbol1", "ufs_rx_symbol1",
> +               24),
> +       GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31),
> +};
> +
> +static const struct mtk_gate_regs peri_ao_cg_regs = {
> +       .set_ofs = 0x10,
> +       .clr_ofs = 0x14,
> +       .sta_ofs = 0x18,
> +};
> +
> +#define GATE_PERI_AO(_id, _name, _parent, _shift)                      \
> +       GATE_MTK(_id, _name, _parent, &peri_ao_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate peri_ao_clks[] = {
> +       GATE_PERI_AO(CLK_PERI_AO_ETHERNET, "peri_ao_ethernet", "axi_sel", 0),
> +       GATE_PERI_AO(CLK_PERI_AO_ETHERNET_BUS, "peri_ao_ethernet_bus", "axi_sel", 1),
> +       GATE_PERI_AO(CLK_PERI_AO_FLASHIF_BUS, "peri_ao_flashif_bus", "axi_sel", 3),
> +       GATE_PERI_AO(CLK_PERI_AO_FLASHIF_FLASH, "peri_ao_flashif_flash", "spinor_sel", 5),
> +       GATE_PERI_AO(CLK_PERI_AO_SSUSB_1P_BUS, "peri_ao_ssusb_1p_bus", "usb_1p_sel", 7),
> +       GATE_PERI_AO(CLK_PERI_AO_SSUSB_1P_XHCI, "peri_ao_ssusb_1p_xhci", "ssusb_xhci_1p_sel", 8),
> +       GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_BUS, "peri_ao_ssusb_2p_bus", "usb_2p_sel", 9),
> +       GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_XHCI, "peri_ao_ssusb_2p_xhci", "ssusb_xhci_2p_sel", 10),
> +       GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_BUS, "peri_ao_ssusb_3p_bus", "usb_3p_sel", 11),
> +       GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_XHCI, "peri_ao_ssusb_3p_xhci", "ssusb_xhci_3p_sel", 12),
> +       GATE_PERI_AO(CLK_PERI_AO_SPINFI, "peri_ao_spinfi", "spinfi_b_sel", 15),
> +       GATE_PERI_AO(CLK_PERI_AO_ETHERNET_MAC, "peri_ao_ethernet_mac", "snps_eth_250m_sel", 16),
> +       GATE_PERI_AO(CLK_PERI_AO_NFI_H, "peri_ao_nfi_h", "axi_sel", 19),
> +       GATE_PERI_AO(CLK_PERI_AO_FNFI1X, "peri_ao_fnfi1x", "nfi1x_sel", 20),
> +       GATE_PERI_AO(CLK_PERI_AO_PCIE_P0_MEM, "peri_ao_pcie_p0_mem", "mem_466m", 24),
> +       GATE_PERI_AO(CLK_PERI_AO_PCIE_P1_MEM, "peri_ao_pcie_p1_mem", "mem_466m", 25),
> +};
> +
> +static const struct mtk_gate_regs top0_cg_regs = {
> +       .set_ofs = 0x238,
> +       .clr_ofs = 0x238,
> +       .sta_ofs = 0x238,
> +};
> +
> +static const struct mtk_gate_regs top1_cg_regs = {
> +       .set_ofs = 0x250,
> +       .clr_ofs = 0x250,
> +       .sta_ofs = 0x250,
> +};
> +
> +#define GATE_TOP0_FLAGS(_id, _name, _parent, _shift, _flag)            \
> +       GATE_MTK_FLAGS(_id, _name, _parent, &top0_cg_regs, _shift,      \
> +               &mtk_clk_gate_ops_no_setclr_inv, _flag)
> +
> +#define GATE_TOP0(_id, _name, _parent, _shift)                 \
> +       GATE_TOP0_FLAGS(_id, _name, _parent, _shift, 0)
> +
> +#define GATE_TOP1(_id, _name, _parent, _shift)                 \
> +       GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
> +
> +static const struct mtk_gate top_clks[] = {
> +       /* TOP0 */
> +       GATE_TOP0(CLK_TOP_CFG_VPP0, "cfg_vpp0", "vpp_sel", 0),
> +       GATE_TOP0(CLK_TOP_CFG_VPP1, "cfg_vpp1", "vpp_sel", 1),
> +       GATE_TOP0(CLK_TOP_CFG_VDO0, "cfg_vdo0", "vpp_sel", 2),
> +       GATE_TOP0(CLK_TOP_CFG_VDO1, "cfg_vdo1", "vpp_sel", 3),
> +       GATE_TOP0(CLK_TOP_CFG_UNIPLL_SES, "cfg_unipll_ses", "univpll_d2", 4),
> +       GATE_TOP0(CLK_TOP_CFG_26M_VPP0, "cfg_26m_vpp0", "clk26m", 5),
> +       GATE_TOP0(CLK_TOP_CFG_26M_VPP1, "cfg_26m_vpp1", "clk26m", 6),
> +       GATE_TOP0(CLK_TOP_CFG_26M_AUD, "cfg_26m_aud", "clk26m", 9),
> +       GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST, "cfg_axi_east", "axi_sel", 10, CLK_IS_CRITICAL),
> +       GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST_NORTH, "cfg_axi_east_north", "axi_sel", 11,
> +               CLK_IS_CRITICAL),
> +       GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_NORTH, "cfg_axi_north", "axi_sel", 12, CLK_IS_CRITICAL),
> +       GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_SOUTH, "cfg_axi_south", "axi_sel", 13, CLK_IS_CRITICAL),
> +       GATE_TOP0(CLK_TOP_CFG_EXT_TEST, "cfg_ext_test", "msdcpll_d2", 15),
> +       /* TOP1 */
> +       GATE_TOP1(CLK_TOP_SSUSB_REF, "ssusb_ref", "clk26m", 0),
> +       GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 1),
> +       GATE_TOP1(CLK_TOP_SSUSB_P1_REF, "ssusb_p1_ref", "clk26m", 2),
> +       GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, "ssusb_phy_p1_ref", "clk26m", 3),
> +       GATE_TOP1(CLK_TOP_SSUSB_P2_REF, "ssusb_p2_ref", "clk26m", 4),
> +       GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, "ssusb_phy_p2_ref", "clk26m", 5),
> +       GATE_TOP1(CLK_TOP_SSUSB_P3_REF, "ssusb_p3_ref", "clk26m", 6),
> +       GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, "ssusb_phy_p3_ref", "clk26m", 7),
> +};

These should be grouped with the other TOPCKGEN clocks. Another reason to
split this driver into multiple ones.

> +
> +static const struct mtk_gate_regs apmixed_cg_regs = {
> +       .set_ofs = 0x8,
> +       .clr_ofs = 0x8,
> +       .sta_ofs = 0x8,
> +};
> +
> +#define GATE_APMIXED(_id, _name, _parent, _shift)                      \
> +       GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
> +
> +static const struct mtk_gate apmixed_clks[] = {
> +       GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M, "pll_ssusb26m", "clk26m", 1),
> +};
> +
> +#define MT8195_PLL_FMAX                (3800UL * MHZ)
> +#define MT8195_PLL_FMIN                (1500UL * MHZ)
> +#define MT8195_INTEGER_BITS    8
> +
> +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags,      \
> +                       _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift,    \
> +                       _tuner_reg, _tuner_en_reg, _tuner_en_bit,       \
> +                       _pcw_reg, _pcw_shift, _pcw_chg_reg,                             \
> +                       _en_reg, _pll_en_bit) {                                 \
> +               .id = _id,                                              \
> +               .name = _name,                                          \
> +               .reg = _reg,                                            \
> +               .pwr_reg = _pwr_reg,                                    \
> +               .en_mask = _en_mask,                                    \
> +               .flags = _flags,                                        \
> +               .rst_bar_mask = _rst_bar_mask,                          \
> +               .fmax = MT8195_PLL_FMAX,                                \
> +               .fmin = MT8195_PLL_FMIN,                                \
> +               .pcwbits = _pcwbits,                                    \
> +               .pcwibits = MT8195_INTEGER_BITS,                        \
> +               .pd_reg = _pd_reg,                                      \
> +               .pd_shift = _pd_shift,                                  \
> +               .tuner_reg = _tuner_reg,                                \
> +               .tuner_en_reg = _tuner_en_reg,                          \
> +               .tuner_en_bit = _tuner_en_bit,                          \
> +               .pcw_reg = _pcw_reg,                                    \
> +               .pcw_shift = _pcw_shift,                                \
> +               .pcw_chg_reg = _pcw_chg_reg,                            \
> +               .en_reg = _en_reg,                                      \
> +               .pll_en_bit = _pll_en_bit,                              \
> +       }
> +
> +static const struct mtk_pll_data plls[] = {
> +       PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0, 0,
> +               0, 0, 22, 0x0398, 24, 0, 0, 0, 0x0398, 0, 0x0398, 0, 9),
> +       PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320, 0,
> +               0, 0, 22, 0x0198, 24, 0, 0, 0, 0x0198, 0, 0x0198, 0, 9),
> +       PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370, 0,
> +               0, 0, 22, 0x0368, 24, 0, 0, 0, 0x0368, 0, 0x0368, 0, 9),
> +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
> +               0, 0, 22, 0x0718, 24, 0, 0, 0, 0x0718, 0, 0x0718, 0, 9),
> +       PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x00a0, 0x00b0, 0,
> +               0, 0, 22, 0x00a8, 24, 0, 0, 0, 0x00a8, 0, 0x00a8, 0, 9),
> +       PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x00c0, 0x00d0, 0,
> +               0, 0, 22, 0x00c8, 24, 0, 0, 0, 0x00c8, 0, 0x00c8, 0, 9),
> +       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x00e0, 0x00f0, 0xff000000,
> +               HAVE_RST_BAR, BIT(23), 22, 0x00e8, 24, 0, 0, 0, 0x00e8, 0, 0x00e8, 0, 9),
> +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x01d0, 0x01e0, 0xff000000,
> +               HAVE_RST_BAR, BIT(23), 22, 0x01d8, 24, 0, 0, 0, 0x01d8, 0, 0x01d8, 0, 9),
> +       PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x0890, 0x08a0, 0,
> +               0, 0, 22, 0x0898, 24, 0, 0, 0, 0x0898, 0, 0x0898, 0, 9),
> +       PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0100, 0x0110, 0,
> +               0, 0, 22, 0x0108, 24, 0, 0, 0, 0x0108, 0, 0x0108, 0, 9),
> +       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x01f0, 0x0700, 0xff000000,
> +               HAVE_RST_BAR, BIT(23), 22, 0x01f8, 24, 0, 0, 0, 0x01f8, 0, 0x01f8, 0, 9),
> +       PLL(CLK_APMIXED_HDMIPLL1, "hdmipll1", 0x08c0, 0x08d0, 0,
> +               0, 0, 22, 0x08c8, 24, 0, 0, 0, 0x08c8, 0, 0x08c8, 0, 9),
> +       PLL(CLK_APMIXED_HDMIPLL2, "hdmipll2", 0x0870, 0x0880, 0,
> +               0, 0, 22, 0x0878, 24, 0, 0, 0, 0x0878, 0, 0x0878, 0, 9),
> +       PLL(CLK_APMIXED_HDMIRX_APLL, "hdmirx_apll", 0x08e0, 0x0dd4, 0,
> +               0, 0, 32, 0x08e8, 24, 0, 0, 0, 0x08ec, 0, 0x08e8, 0, 9),
> +       PLL(CLK_APMIXED_USB1PLL, "usb1pll", 0x01a0, 0x01b0, 0,
> +               0, 0, 22, 0x01a8, 24, 0, 0, 0, 0x01a8, 0, 0x01a8, 0, 9),
> +       PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x07e0, 0x07f0, 0,
> +               0, 0, 22, 0x07e8, 24, 0, 0, 0, 0x07e8, 0, 0x07e8, 0, 9),
> +       PLL(CLK_APMIXED_APLL1, "apll1", 0x07c0, 0x0dc0, 0,
> +               0, 0, 32, 0x07c8, 24, 0x0470, 0x0000, 12, 0x07cc, 0, 0x07c8, 0, 9),
> +       PLL(CLK_APMIXED_APLL2, "apll2", 0x0780, 0x0dc4, 0,
> +               0, 0, 32, 0x0788, 24, 0x0474, 0x0000, 13, 0x078c, 0, 0x0788, 0, 9),
> +       PLL(CLK_APMIXED_APLL3, "apll3", 0x0760, 0x0dc8, 0,
> +               0, 0, 32, 0x0768, 24, 0x0478, 0x0000, 14, 0x076c, 0, 0x0768, 0, 9),
> +       PLL(CLK_APMIXED_APLL4, "apll4", 0x0740, 0x0dcc, 0,
> +               0, 0, 32, 0x0748, 24, 0x047C, 0x0000, 15, 0x074c, 0, 0x0748, 0, 9),
> +       PLL(CLK_APMIXED_APLL5, "apll5", 0x07a0, 0x0dd0, 0x100000,
> +               0, 0, 32, 0x07a8, 24, 0x0480, 0x0000, 16, 0x07ac, 0, 0x07a8, 0, 9),
> +       PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x0350, 0,
> +               0, 0, 22, 0x0348, 24, 0, 0, 0, 0x0348, 0, 0x0348, 0, 9),
> +       PLL(CLK_APMIXED_DGIPLL, "dgipll", 0x0150, 0x0160, 0,
> +               0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0, 0x0158, 0, 9),
> +};
> +
> +static struct clk_onecell_data *top_clk_data;
> +
> +static void clk_mt8195_top_init_early(struct device_node *node)
> +{
> +       int i;
> +
> +       top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
> +       if (!top_clk_data)
> +               return;
> +
> +       for (i = 0; i < CLK_TOP_NR_CLK; i++)
> +               top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
> +
> +       mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data);
> +
> +       of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
> +}
> +
> +CLK_OF_DECLARE_DRIVER(mt8195_topckgen, "mediatek,mt8195-topckgen",
> +                       clk_mt8195_top_init_early);
> +
> +static int clk_mt8195_top_probe(struct platform_device *pdev)
> +{
> +       struct device_node *node = pdev->dev.of_node;
> +       int r;
> +       void __iomem *base;
> +
> +       base = devm_platform_ioremap_resource(pdev, 0);
> +       if (IS_ERR(base))
> +               return PTR_ERR(base);
> +
> +       mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
> +                       top_clk_data);
> +       mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data);
> +       mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
> +       mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node,
> +                       &mt8195_clk_lock, top_clk_data);
> +       mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
> +                       &mt8195_clk_lock, top_clk_data);
> +       mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
> +                       &mt8195_clk_lock, top_clk_data);

Future work: these functions probably should be made to return errors.

> +       r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data);
> +       if (r)
> +               return r;
> +
> +       return of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
> +}
> +
> +static int clk_mt8195_infra_ao_probe(struct platform_device *pdev)
> +{
> +       struct clk_onecell_data *clk_data;
> +       struct device_node *node = pdev->dev.of_node;
> +       int r;
> +
> +       clk_data = mtk_alloc_clk_data(CLK_INFRA_AO_NR_CLK);
> +       if (!clk_data)
> +               return -ENOMEM;
> +
> +       r = mtk_clk_register_gates(node, infra_ao_clks, ARRAY_SIZE(infra_ao_clks), clk_data);
> +       if (r)
> +               return r;
> +
> +       return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

You are leaking clk_data if mtk_clk_register_gates() or of_clk_add_provider()
fail.

> +}
> +
> +static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
> +{
> +       struct clk_onecell_data *clk_data;
> +       struct device_node *node = pdev->dev.of_node;
> +       int r;
> +
> +       clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
> +       if (!clk_data)
> +               return -ENOMEM;
> +
> +       mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
> +       r = mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
> +       if (r)
> +               return r;
> +
> +       return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

Same here.

> +}
> +
> +static int clk_mt8195_peri_ao_probe(struct platform_device *pdev)
> +{
> +       struct clk_onecell_data *clk_data;
> +       struct device_node *node = pdev->dev.of_node;
> +       int r;
> +
> +       clk_data = mtk_alloc_clk_data(CLK_PERI_AO_NR_CLK);
> +       if (!clk_data)
> +               return -ENOMEM;
> +
> +       r = mtk_clk_register_gates(node, peri_ao_clks, ARRAY_SIZE(peri_ao_clks), clk_data);
> +       if (r)
> +               return r;
> +
> +       return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

And here.

> +}
> +
> +static const struct of_device_id of_match_clk_mt8195[] = {
> +       {
> +               .compatible = "mediatek,mt8195-apmixedsys",
> +               .data = clk_mt8195_apmixed_probe,
> +       }, {
> +               .compatible = "mediatek,mt8195-topckgen",
> +               .data = clk_mt8195_top_probe,
> +       }, {
> +               .compatible = "mediatek,mt8195-infracfg_ao",
> +               .data = clk_mt8195_infra_ao_probe,
> +       }, {
> +               .compatible = "mediatek,mt8195-pericfg_ao",
> +               .data = clk_mt8195_peri_ao_probe,

This file contains four drivers. They do not have depend on each other,
and do not need to be in the same file. Please split them into different
files and preferably different patches so people reading them don't have
to look through unrelated data. Then you don't need the pointer to the
probe function.

You can keep them under the same Kconfig symbol.

> +       }, {
> +               /* sentinel */
> +       }
> +};
> +
> +static int clk_mt8195_probe(struct platform_device *pdev)
> +{
> +       int (*clk_probe)(struct platform_device *pdev);
> +       int r;
> +
> +       clk_probe = of_device_get_match_data(&pdev->dev);
> +       if (!clk_probe)
> +               return -EINVAL;
> +
> +       r = clk_probe(pdev);
> +       if (r)
> +               dev_err(&pdev->dev,
> +                       "could not register clock provider: %s: %d\n",
> +                       pdev->name, r);
> +
> +       return r;
> +}
> +
> +static struct platform_driver clk_mt8195_drv = {
> +       .probe = clk_mt8195_probe,
> +       .driver = {
> +               .name = "clk-mt8195",
> +               .of_match_table = of_match_clk_mt8195,
> +       },
> +};
> +
> +static int __init clk_mt8195_init(void)
> +{
> +       return platform_driver_register(&clk_mt8195_drv);
> +}
> +
> +arch_initcall(clk_mt8195_init);

Is there any particular reason for arch_initcall?


Regards
ChenYu

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 05/22] clk: mediatek: Add MT8195 audio clock support
  2021-06-16 22:47 ` [PATCH 05/22] clk: mediatek: Add MT8195 audio clock support Chun-Jie Chen
@ 2021-07-05  9:03   ` Chen-Yu Tsai
  2021-07-12  1:26     ` Chun-Jie Chen
  0 siblings, 1 reply; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-05  9:03 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group

Hi,

On Thu, Jun 17, 2021 at 06:47:26AM +0800, Chun-Jie Chen wrote:
> Add MT8195 audio clock provider
> 
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  drivers/clk/mediatek/Kconfig          |   6 +
>  drivers/clk/mediatek/Makefile         |   1 +
>  drivers/clk/mediatek/clk-mt8195-aud.c | 198 ++++++++++++++++++++++++++
>  3 files changed, 205 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt8195-aud.c
> 
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 6707aba3d500..e2bae9d490a4 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -588,6 +588,12 @@ config COMMON_CLK_MT8195
>  	help
>  	  This driver supports MediaTek MT8195 basic clocks.
>  
> +config COMMON_CLK_MT8195_AUDSYS
> +	bool "Clock driver for MediaTek MT8195 audsys"
> +	depends on COMMON_CLK_MT8195
> +	help
> +	  This driver supports MediaTek MT8195 audsys clocks.
> +

The clock modules aren't shared between different chips, so either we
enable support for all clock hardware in one chip or we don't. It
doesn't make sense to support just some of them. So having just one
Kconfig option and having all drivers under it is better.

>  config COMMON_CLK_MT8516
>  	bool "Clock driver for MediaTek MT8516"
>  	depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index f8002d8966e1..f27c04314186 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -81,5 +81,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
>  obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195.o
> +obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS) += clk-mt8195-aud.o
>  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
>  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-aud.c b/drivers/clk/mediatek/clk-mt8195-aud.c
> new file mode 100644
> index 000000000000..db5f80d41de0
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-aud.c
> @@ -0,0 +1,198 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +
> +static const struct mtk_gate_regs aud0_cg_regs = {
> +	.set_ofs = 0x0,
> +	.clr_ofs = 0x0,
> +	.sta_ofs = 0x0,
> +};
> +
> +static const struct mtk_gate_regs aud1_cg_regs = {
> +	.set_ofs = 0x10,
> +	.clr_ofs = 0x10,
> +	.sta_ofs = 0x10,
> +};
> +
> +static const struct mtk_gate_regs aud2_cg_regs = {
> +	.set_ofs = 0x14,
> +	.clr_ofs = 0x14,
> +	.sta_ofs = 0x14,
> +};
> +
> +static const struct mtk_gate_regs aud3_cg_regs = {
> +	.set_ofs = 0x18,
> +	.clr_ofs = 0x18,
> +	.sta_ofs = 0x18,
> +};
> +
> +static const struct mtk_gate_regs aud4_cg_regs = {
> +	.set_ofs = 0x4,
> +	.clr_ofs = 0x4,
> +	.sta_ofs = 0x4,
> +};
> +
> +static const struct mtk_gate_regs aud5_cg_regs = {
> +	.set_ofs = 0xc,
> +	.clr_ofs = 0xc,
> +	.sta_ofs = 0xc,
> +};
> +
> +#define GATE_AUD0(_id, _name, _parent, _shift)			\
> +	GATE_MTK(_id, _name, _parent, &aud0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
> +
> +#define GATE_AUD1(_id, _name, _parent, _shift)			\
> +	GATE_MTK(_id, _name, _parent, &aud1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
> +
> +#define GATE_AUD2(_id, _name, _parent, _shift)			\
> +	GATE_MTK(_id, _name, _parent, &aud2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
> +
> +#define GATE_AUD3(_id, _name, _parent, _shift)			\
> +	GATE_MTK(_id, _name, _parent, &aud3_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
> +
> +#define GATE_AUD4(_id, _name, _parent, _shift)			\
> +	GATE_MTK(_id, _name, _parent, &aud4_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
> +
> +#define GATE_AUD5(_id, _name, _parent, _shift)			\
> +	GATE_MTK(_id, _name, _parent, &aud5_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
> +
> +static const struct mtk_gate aud_clks[] = {
> +	/* AUD0 */
> +	GATE_AUD0(CLK_AUD_AFE, "aud_afe", "a1sys_hp_sel", 2),
> +	GATE_AUD0(CLK_AUD_LRCK_CNT, "aud_lrck_cnt", "a1sys_hp_sel", 4),
> +	GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_APLL, "aud_spdifin_tuner_apll", "apll4_sel", 10),
> +	GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_DBG, "aud_spdifin_tuner_dbg", "apll4_sel", 11),
> +	GATE_AUD0(CLK_AUD_UL_TML, "aud_ul_tml", "a1sys_hp_sel", 18),
> +	GATE_AUD0(CLK_AUD_APLL1_TUNER, "aud_apll1_tuner", "apll1_sel", 19),
> +	GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "apll2_sel", 20),
> +	GATE_AUD0(CLK_AUD_TOP0_SPDF, "aud_top0_spdf", "aud_iec_sel", 21),
> +	GATE_AUD0(CLK_AUD_APLL, "aud_apll", "apll1_sel", 23),
> +	GATE_AUD0(CLK_AUD_APLL2, "aud_apll2", "apll2_sel", 24),
> +	GATE_AUD0(CLK_AUD_DAC, "aud_dac", "a1sys_hp_sel", 25),
> +	GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "a1sys_hp_sel", 26),
> +	GATE_AUD0(CLK_AUD_TML, "aud_tml", "a1sys_hp_sel", 27),
> +	GATE_AUD0(CLK_AUD_ADC, "aud_adc", "a1sys_hp_sel", 28),
> +	GATE_AUD0(CLK_AUD_DAC_HIRES, "aud_dac_hires", "audio_h_sel", 31),
> +	/* AUD1 */
> +	GATE_AUD1(CLK_AUD_I2SIN, "aud_i2sin", "a1sys_hp_sel", 0),
> +	GATE_AUD1(CLK_AUD_TDM_IN, "aud_tdm_in", "a1sys_hp_sel", 1),
> +	GATE_AUD1(CLK_AUD_I2S_OUT, "aud_i2s_out", "a1sys_hp_sel", 6),
> +	GATE_AUD1(CLK_AUD_TDM_OUT, "aud_tdm_out", "a1sys_hp_sel", 7),
> +	GATE_AUD1(CLK_AUD_HDMI_OUT, "aud_hdmi_out", "a1sys_hp_sel", 8),
> +	GATE_AUD1(CLK_AUD_ASRC11, "aud_asrc11", "a1sys_hp_sel", 16),
> +	GATE_AUD1(CLK_AUD_ASRC12, "aud_asrc12", "a1sys_hp_sel", 17),
> +	GATE_AUD1(CLK_AUD_MULTI_IN, "aud_multi_in", "mphone_slave_b", 19),
> +	GATE_AUD1(CLK_AUD_INTDIR, "aud_intdir", "intdir_sel", 20),
> +	GATE_AUD1(CLK_AUD_A1SYS, "aud_a1sys", "a1sys_hp_sel", 21),
> +	GATE_AUD1(CLK_AUD_A2SYS, "aud_a2sys", "a2sys_sel", 22),
> +	GATE_AUD1(CLK_AUD_PCMIF, "aud_pcmif", "a1sys_hp_sel", 24),
> +	GATE_AUD1(CLK_AUD_A3SYS, "aud_a3sys", "a3sys_sel", 30),
> +	GATE_AUD1(CLK_AUD_A4SYS, "aud_a4sys", "a4sys_sel", 31),
> +	/* AUD2 */
> +	GATE_AUD2(CLK_AUD_MEMIF_UL1, "aud_memif_ul1", "a1sys_hp_sel", 0),
> +	GATE_AUD2(CLK_AUD_MEMIF_UL2, "aud_memif_ul2", "a1sys_hp_sel", 1),
> +	GATE_AUD2(CLK_AUD_MEMIF_UL3, "aud_memif_ul3", "a1sys_hp_sel", 2),
> +	GATE_AUD2(CLK_AUD_MEMIF_UL4, "aud_memif_ul4", "a1sys_hp_sel", 3),
> +	GATE_AUD2(CLK_AUD_MEMIF_UL5, "aud_memif_ul5", "a1sys_hp_sel", 4),
> +	GATE_AUD2(CLK_AUD_MEMIF_UL6, "aud_memif_ul6", "a1sys_hp_sel", 5),
> +	GATE_AUD2(CLK_AUD_MEMIF_UL8, "aud_memif_ul8", "a1sys_hp_sel", 7),
> +	GATE_AUD2(CLK_AUD_MEMIF_UL9, "aud_memif_ul9", "a1sys_hp_sel", 8),
> +	GATE_AUD2(CLK_AUD_MEMIF_UL10, "aud_memif_ul10", "a1sys_hp_sel", 9),
> +	GATE_AUD2(CLK_AUD_MEMIF_DL2, "aud_memif_dl2", "a1sys_hp_sel", 18),
> +	GATE_AUD2(CLK_AUD_MEMIF_DL3, "aud_memif_dl3", "a1sys_hp_sel", 19),
> +	GATE_AUD2(CLK_AUD_MEMIF_DL6, "aud_memif_dl6", "a1sys_hp_sel", 22),
> +	GATE_AUD2(CLK_AUD_MEMIF_DL7, "aud_memif_dl7", "a1sys_hp_sel", 23),
> +	GATE_AUD2(CLK_AUD_MEMIF_DL8, "aud_memif_dl8", "a1sys_hp_sel", 24),
> +	GATE_AUD2(CLK_AUD_MEMIF_DL10, "aud_memif_dl10", "a1sys_hp_sel", 26),
> +	GATE_AUD2(CLK_AUD_MEMIF_DL11, "aud_memif_dl11", "a1sys_hp_sel", 27),
> +	/* AUD3 */
> +	GATE_AUD3(CLK_AUD_GASRC0, "aud_gasrc0", "asm_h_sel", 0),
> +	GATE_AUD3(CLK_AUD_GASRC1, "aud_gasrc1", "asm_h_sel", 1),
> +	GATE_AUD3(CLK_AUD_GASRC2, "aud_gasrc2", "asm_h_sel", 2),
> +	GATE_AUD3(CLK_AUD_GASRC3, "aud_gasrc3", "asm_h_sel", 3),
> +	GATE_AUD3(CLK_AUD_GASRC4, "aud_gasrc4", "asm_h_sel", 4),
> +	GATE_AUD3(CLK_AUD_GASRC5, "aud_gasrc5", "asm_h_sel", 5),
> +	GATE_AUD3(CLK_AUD_GASRC6, "aud_gasrc6", "asm_h_sel", 6),
> +	GATE_AUD3(CLK_AUD_GASRC7, "aud_gasrc7", "asm_h_sel", 7),
> +	GATE_AUD3(CLK_AUD_GASRC8, "aud_gasrc8", "asm_h_sel", 8),
> +	GATE_AUD3(CLK_AUD_GASRC9, "aud_gasrc9", "asm_h_sel", 9),
> +	GATE_AUD3(CLK_AUD_GASRC10, "aud_gasrc10", "asm_h_sel", 10),
> +	GATE_AUD3(CLK_AUD_GASRC11, "aud_gasrc11", "asm_h_sel", 11),
> +	GATE_AUD3(CLK_AUD_GASRC12, "aud_gasrc12", "asm_h_sel", 12),
> +	GATE_AUD3(CLK_AUD_GASRC13, "aud_gasrc13", "asm_h_sel", 13),
> +	GATE_AUD3(CLK_AUD_GASRC14, "aud_gasrc14", "asm_h_sel", 14),
> +	GATE_AUD3(CLK_AUD_GASRC15, "aud_gasrc15", "asm_h_sel", 15),
> +	GATE_AUD3(CLK_AUD_GASRC16, "aud_gasrc16", "asm_h_sel", 16),
> +	GATE_AUD3(CLK_AUD_GASRC17, "aud_gasrc17", "asm_h_sel", 17),
> +	GATE_AUD3(CLK_AUD_GASRC18, "aud_gasrc18", "asm_h_sel", 18),
> +	GATE_AUD3(CLK_AUD_GASRC19, "aud_gasrc19", "asm_h_sel", 19),
> +	/* AUD4 */
> +	GATE_AUD4(CLK_AUD_A1SYS_HP, "aud_a1sys_hp", "a1sys_hp_sel", 2),
> +	GATE_AUD4(CLK_AUD_AFE_DMIC1, "aud_afe_dmic1", "a1sys_hp_sel", 10),
> +	GATE_AUD4(CLK_AUD_AFE_DMIC2, "aud_afe_dmic2", "a1sys_hp_sel", 11),
> +	GATE_AUD4(CLK_AUD_AFE_DMIC3, "aud_afe_dmic3", "a1sys_hp_sel", 12),
> +	GATE_AUD4(CLK_AUD_AFE_DMIC4, "aud_afe_dmic4", "a1sys_hp_sel", 13),
> +	GATE_AUD4(CLK_AUD_AFE_26M_DMIC_TM, "aud_afe_26m_dmic_tm", "a1sys_hp_sel", 14),
> +	GATE_AUD4(CLK_AUD_UL_TML_HIRES, "aud_ul_tml_hires", "audio_h_sel", 16),
> +	GATE_AUD4(CLK_AUD_ADC_HIRES, "aud_adc_hires", "audio_h_sel", 17),
> +	GATE_AUD4(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "a1sys_hp_sel", 18),
> +	GATE_AUD4(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "audio_h_sel", 19),
> +	/* AUD5 */
> +	GATE_AUD5(CLK_AUD_LINEIN_TUNER, "aud_linein_tuner", "apll5_sel", 5),
> +	GATE_AUD5(CLK_AUD_EARC_TUNER, "aud_earc_tuner", "apll3_sel", 7),
> +};

These are all clock gates, and are all internal to the audio hardware,
i.e. not used by other drivers or modules.

So these don't actually need to be in a separate clk driver. They can be
modelled within ASoC as supplies that are automatically managed by ASoC
core. Otherwise just have them as bits that are toggled by the audio
driver's start/stop sequencing code, like they are now, but through
vastly more complicated plumbing.

Please work with the audio driver owner to see if this can be moved into
the audio driver.

Regards
ChenYu

> +
> +static int clk_mt8195_aud_probe(struct platform_device *pdev)
> +{
> +	struct clk_onecell_data *clk_data;
> +	struct device_node *node = pdev->dev.of_node;
> +	int r;
> +
> +	clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
> +	if (!clk_data)
> +		return -ENOMEM;
> +
> +	r = mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);
> +	if (r)
> +		return r;
> +
> +	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +	if (r)
> +		goto err_clk_provider;
> +
> +	r = devm_of_platform_populate(&pdev->dev);
> +	if (r)
> +		goto err_plat_populate;
> +
> +	return 0;
> +
> +err_plat_populate:
> +	of_clk_del_provider(node);
> +err_clk_provider:
> +	return r;
> +}
> +
> +static const struct of_device_id of_match_clk_mt8195_aud[] = {
> +	{ .compatible = "mediatek,mt8195-audsys", },
> +	{}
> +};
> +
> +static struct platform_driver clk_mt8195_aud_drv = {
> +	.probe = clk_mt8195_aud_probe,
> +	.driver = {
> +		.name = "clk-mt8195-aud",
> +		.of_match_table = of_match_clk_mt8195_aud,
> +	},
> +};
> +
> +builtin_platform_driver(clk_mt8195_aud_drv);
> -- 
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 06/22] clk: mediatek: Add MT8195 audio src clock support
  2021-06-16 22:47 ` [PATCH 06/22] clk: mediatek: Add MT8195 audio src " Chun-Jie Chen
@ 2021-07-05 10:07   ` Chen-Yu Tsai
  0 siblings, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-05 10:07 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group

Hi,

On Thu, Jun 17, 2021 at 06:47:27AM +0800, Chun-Jie Chen wrote:
> Add MT8195 audio src source clock provider
> 
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  drivers/clk/mediatek/Kconfig              |  6 +++
>  drivers/clk/mediatek/Makefile             |  1 +
>  drivers/clk/mediatek/clk-mt8195-aud_src.c | 60 +++++++++++++++++++++++
>  3 files changed, 67 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt8195-aud_src.c
> 
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index e2bae9d490a4..62dd02bc2755 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -594,6 +594,12 @@ config COMMON_CLK_MT8195_AUDSYS
>  	help
>  	  This driver supports MediaTek MT8195 audsys clocks.
>  
> +config COMMON_CLK_MT8195_AUDSYS_SRC
> +	bool "Clock driver for MediaTek MT8195 audsys_src"
> +	depends on COMMON_CLK_MT8195
> +	help
> +	  This driver supports MediaTek MT8195 audsys_src clocks.
> +

Same comments regarding the Kconfig symbol as the previous patch.

>  config COMMON_CLK_MT8516
>  	bool "Clock driver for MediaTek MT8516"
>  	depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index f27c04314186..52a5d3f49ff0 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -82,5 +82,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
>  obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
>  obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS) += clk-mt8195-aud.o
> +obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS_SRC) += clk-mt8195-aud_src.o
>  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
>  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-aud_src.c b/drivers/clk/mediatek/clk-mt8195-aud_src.c
> new file mode 100644
> index 000000000000..7cabe0d68825
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-aud_src.c
> @@ -0,0 +1,60 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +
> +static const struct mtk_gate_regs aud_src_cg_regs = {
> +	.set_ofs = 0x1004,
> +	.clr_ofs = 0x1004,
> +	.sta_ofs = 0x1004,
> +};
> +
> +#define GATE_AUD_SRC(_id, _name, _parent, _shift)			\
> +	GATE_MTK(_id, _name, _parent, &aud_src_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
> +
> +static const struct mtk_gate aud_src_clks[] = {
> +	GATE_AUD_SRC(CLK_AUD_SRC_ASRC0, "aud_src_asrc0", "asm_h_sel", 0),
> +	GATE_AUD_SRC(CLK_AUD_SRC_ASRC1, "aud_src_asrc1", "asm_h_sel", 1),
> +	GATE_AUD_SRC(CLK_AUD_SRC_ASRC2, "aud_src_asrc2", "asm_h_sel", 2),
> +	GATE_AUD_SRC(CLK_AUD_SRC_ASRC3, "aud_src_asrc3", "asm_h_sel", 3),
> +	GATE_AUD_SRC(CLK_AUD_SRC_ASRC4, "aud_src_asrc4", "asm_h_sel", 4),
> +	GATE_AUD_SRC(CLK_AUD_SRC_ASRC5, "aud_src_asrc5", "asm_h_sel", 5),
> +	GATE_AUD_SRC(CLK_AUD_SRC_ASRC6, "aud_src_asrc6", "asm_h_sel", 6),
> +	GATE_AUD_SRC(CLK_AUD_SRC_ASRC7, "aud_src_asrc7", "asm_h_sel", 7),
> +	GATE_AUD_SRC(CLK_AUD_SRC_ASRC8, "aud_src_asrc8", "asm_h_sel", 8),
> +	GATE_AUD_SRC(CLK_AUD_SRC_ASRC9, "aud_src_asrc9", "asm_h_sel", 9),
> +	GATE_AUD_SRC(CLK_AUD_SRC_ASRC10, "aud_src_asrc10", "asm_h_sel", 10),
> +	GATE_AUD_SRC(CLK_AUD_SRC_ASRC11, "aud_src_asrc11", "asm_h_sel", 11),

And same thing about moving this into the audio driver. AFAICT there is
no audio driver supporting this hardware block, so this will never get
used.


Regards
ChenYu

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 07/22] clk: mediatek: Add MT8195 camsys clock support
  2021-06-16 22:47 ` [PATCH 07/22] clk: mediatek: Add MT8195 camsys " Chun-Jie Chen
@ 2021-07-06  8:53   ` Chen-Yu Tsai
  0 siblings, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-06  8:53 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

On Thu, Jun 17, 2021 at 7:04 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 camsys clock providers
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 08/22] clk: mediatek: Add MT8195 ccusys clock support
  2021-06-16 22:47 ` [PATCH 08/22] clk: mediatek: Add MT8195 ccusys " Chun-Jie Chen
@ 2021-07-06  9:00   ` Chen-Yu Tsai
  2021-08-17  0:56     ` Chun-Jie Chen
  0 siblings, 1 reply; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-06  9:00 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

On Thu, Jun 17, 2021 at 6:59 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 ccusys clock provider
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

Also, I noticed that Mediatek drivers don't support the reset controls found
in these clock controllers. Are there plans to add support for them?

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 09/22] clk: mediatek: Add MT8195 imgsys clock support
  2021-06-16 22:47 ` [PATCH 09/22] clk: mediatek: Add MT8195 imgsys " Chun-Jie Chen
@ 2021-07-06  9:07   ` Chen-Yu Tsai
  0 siblings, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-06  9:07 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

Hi,

On Thu, Jun 17, 2021 at 7:01 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 imgsys clock providers
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  drivers/clk/mediatek/Kconfig          |  6 ++
>  drivers/clk/mediatek/Makefile         |  1 +
>  drivers/clk/mediatek/clk-mt8195-img.c | 98 +++++++++++++++++++++++++++
>  3 files changed, 105 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt8195-img.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 6a6e496d08a4..f92d0b6b7eec 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -612,6 +612,12 @@ config COMMON_CLK_MT8195_CCUSYS
>         help
>           This driver supports MediaTek MT8195 ccusys clocks.
>
> +config COMMON_CLK_MT8195_IMGSYS
> +       bool "Clock driver for MediaTek MT8195 imgsys"
> +       depends on COMMON_CLK_MT8195
> +       help
> +         This driver supports MediaTek MT8195 imgsys clocks.
> +
>  config COMMON_CLK_MT8516
>         bool "Clock driver for MediaTek MT8516"
>         depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index bb8aac6f9185..1768eda917c2 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -85,5 +85,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS) += clk-mt8195-aud.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS_SRC) += clk-mt8195-aud_src.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_CAMSYS) += clk-mt8195-cam.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_CCUSYS) += clk-mt8195-ccu.o
> +obj-$(CONFIG_COMMON_CLK_MT8195_IMGSYS) += clk-mt8195-img.o
>  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
>  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-img.c b/drivers/clk/mediatek/clk-mt8195-img.c
> new file mode 100644
> index 000000000000..923fa82aedae
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-img.c
> @@ -0,0 +1,98 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +
> +static const struct mtk_gate_regs img_cg_regs = {
> +       .set_ofs = 0x4,
> +       .clr_ofs = 0x8,
> +       .sta_ofs = 0x0,
> +};
> +
> +#define GATE_IMG(_id, _name, _parent, _shift)                  \
> +       GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate img_clks[] = {
> +       GATE_IMG(CLK_IMG_LARB9, "img_larb9", "img_sel", 0),
> +       GATE_IMG(CLK_IMG_TRAW0, "img_traw0", "img_sel", 1),
> +       GATE_IMG(CLK_IMG_TRAW1, "img_traw1", "img_sel", 2),
> +       GATE_IMG(CLK_IMG_TRAW2, "img_traw2", "img_sel", 3),
> +       GATE_IMG(CLK_IMG_TRAW3, "img_traw3", "img_sel", 4),
> +       GATE_IMG(CLK_IMG_DIP0, "img_dip0", "img_sel", 8),
> +       GATE_IMG(CLK_IMG_WPE0, "img_wpe0", "img_sel", 9),
> +       GATE_IMG(CLK_IMG_IPE, "img_ipe", "img_sel", 10),
> +       GATE_IMG(CLK_IMG_DIP1, "img_dip1", "img_sel", 11),
> +       GATE_IMG(CLK_IMG_WPE1, "img_wpe1", "img_sel", 12),
> +       GATE_IMG(CLK_IMG_GALS, "img_gals", "img_sel", 31),
> +};
> +
> +static const struct mtk_gate img1_dip_top_clks[] = {
> +       GATE_IMG(CLK_IMG1_DIP_TOP_LARB10, "img1_dip_top_larb10", "img_sel", 0),
> +       GATE_IMG(CLK_IMG1_DIP_TOP_DIP_TOP, "img1_dip_top_dip_top", "img_sel", 1),
> +};
> +
> +static const struct mtk_gate img1_dip_nr_clks[] = {
> +       GATE_IMG(CLK_IMG1_DIP_NR_RESERVE, "img1_dip_nr_reserve", "img_sel", 0),

Adding a clock for a bit that is named "reserved" is sort of weird.
Does it actually exist and function?

Otherwise,

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 10/22] clk: mediatek: Add MT8195 ipesys clock support
  2021-06-16 22:47 ` [PATCH 10/22] clk: mediatek: Add MT8195 ipesys " Chun-Jie Chen
@ 2021-07-06  9:11   ` Chen-Yu Tsai
  0 siblings, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-06  9:11 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

On Thu, Jun 17, 2021 at 7:08 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 ipesys clock provider

It would be better if you could provide some more context for the patch,
such as what hardware subsystem / group does this belong to, what do
these clocks feed into? And in the case of supporting multiple clock
controllers in one driver, what led you to group them in the same
driver?

This applies to all your patches. The single statement "Add xxx clock
provider" is simply repeating what the subject already says.

The code looks OK.

Thanks
ChenYu

> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 11/22] clk: mediatek: Add MT8195 mfgcfg clock support
  2021-06-16 22:47 ` [PATCH 11/22] clk: mediatek: Add MT8195 mfgcfg " Chun-Jie Chen
@ 2021-07-09  6:29   ` Chen-Yu Tsai
  0 siblings, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-09  6:29 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

On Thu, Jun 17, 2021 at 7:08 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 mfgcfg clock provider

Same thing about the commit log. More context please.

> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  drivers/clk/mediatek/Kconfig          |  6 ++++
>  drivers/clk/mediatek/Makefile         |  1 +
>  drivers/clk/mediatek/clk-mt8195-mfg.c | 49 +++++++++++++++++++++++++++
>  3 files changed, 56 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt8195-mfg.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index ef7d4b433eee..066c14a89cee 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -624,6 +624,12 @@ config COMMON_CLK_MT8195_IPESYS
>         help
>           This driver supports MediaTek MT8195 ipesys clocks.
>
> +config COMMON_CLK_MT8195_MFGCFG
> +       bool "Clock driver for MediaTek MT8195 mfgcfg"
> +       depends on COMMON_CLK_MT8195
> +       help
> +         This driver supports MediaTek MT8195 mfgcfg clocks.
> +

Same thing about the Kconfig option. I don't think it's necessary to have
separate Kconfig options for clock controllers within the same SoC.

>  config COMMON_CLK_MT8516
>         bool "Clock driver for MediaTek MT8516"
>         depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 991a9be7ac46..9b09e7f640d1 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -87,5 +87,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_CAMSYS) += clk-mt8195-cam.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_CCUSYS) += clk-mt8195-ccu.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_IMGSYS) += clk-mt8195-img.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_IPESYS) += clk-mt8195-ipe.o
> +obj-$(CONFIG_COMMON_CLK_MT8195_MFGCFG) += clk-mt8195-mfg.o
>  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
>  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-mfg.c b/drivers/clk/mediatek/clk-mt8195-mfg.c
> new file mode 100644
> index 000000000000..a9b1d337cd01
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-mfg.c

Code looks good.


ChenYu

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 12/22] clk: mediatek: Add MT8195 scp adsp clock support
  2021-06-16 22:47 ` [PATCH 12/22] clk: mediatek: Add MT8195 scp adsp " Chun-Jie Chen
@ 2021-07-09  6:39   ` Chen-Yu Tsai
  0 siblings, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-09  6:39 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

Hi,

On Thu, Jun 17, 2021 at 6:59 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 scp adsp clock provider
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>

Same comments about commit log and Kconfig option applies.

Code looks good otherwise. Note that the datasheet I have does not include
the registers used in this driver, so I cannot confirm them.


ChenYu

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 13/22] clk: mediatek: Add MT8195 nnasys clock support
  2021-06-16 22:47 ` [PATCH 13/22] clk: mediatek: Add MT8195 nnasys " Chun-Jie Chen
@ 2021-07-09  8:24   ` Chen-Yu Tsai
  0 siblings, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-09  8:24 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

Hi,

On Thu, Jun 17, 2021 at 7:00 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 nnasys clock provider
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  drivers/clk/mediatek/Kconfig          |   6 ++
>  drivers/clk/mediatek/Makefile         |   1 +
>  drivers/clk/mediatek/clk-mt8195-nna.c | 128 ++++++++++++++++++++++++++
>  3 files changed, 135 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt8195-nna.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 7cb745d47770..d34517728f4a 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -636,6 +636,12 @@ config COMMON_CLK_MT8195_SCP_ADSP
>         help
>           This driver supports MediaTek MT8195 scp_adsp clocks.
>
> +config COMMON_CLK_MT8195_NNASYS
> +       bool "Clock driver for MediaTek MT8195 nnasys"
> +       depends on COMMON_CLK_MT8195
> +       help
> +         This driver supports MediaTek MT8195 nnasys clocks.
> +
>  config COMMON_CLK_MT8516
>         bool "Clock driver for MediaTek MT8516"
>         depends on ARCH_MEDIATEK || COMPILE_TEST

Same comments about commit log and Kconfig option apply.

> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 058ff55468a2..49e585a7ac8e 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -89,5 +89,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_IMGSYS) += clk-mt8195-img.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_IPESYS) += clk-mt8195-ipe.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_MFGCFG) += clk-mt8195-mfg.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_SCP_ADSP) += clk-mt8195-scp_adsp.o
> +obj-$(CONFIG_COMMON_CLK_MT8195_NNASYS) += clk-mt8195-nna.o
>  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
>  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-nna.c b/drivers/clk/mediatek/clk-mt8195-nna.c
> new file mode 100644
> index 000000000000..4210c6cf5ef4
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-nna.c
> @@ -0,0 +1,128 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +
> +static const struct mtk_gate_regs nna0_cg_regs = {
> +       .set_ofs = 0x104,
> +       .clr_ofs = 0x104,
> +       .sta_ofs = 0x104,

You are using the _no_setclr_ops variant. That means the .set_ofs and
.clr_ofs fields don't have any meaning and are not used. Please just
don't initialize them.

I think this applies to some of the other patches as well.

> +};
> +
> +static const struct mtk_gate_regs nna1_cg_regs = {
> +       .set_ofs = 0x110,
> +       .clr_ofs = 0x110,
> +       .sta_ofs = 0x110,
> +};
> +
> +static const struct mtk_gate_regs nna2_cg_regs = {
> +       .set_ofs = 0x90,
> +       .clr_ofs = 0x90,
> +       .sta_ofs = 0x90,
> +};
> +
> +static const struct mtk_gate_regs nna3_cg_regs = {
> +       .set_ofs = 0x94,
> +       .clr_ofs = 0x94,
> +       .sta_ofs = 0x94,
> +};
> +
> +static const struct mtk_gate_regs nna4_cg_regs = {
> +       .set_ofs = 0x98,
> +       .clr_ofs = 0x98,
> +       .sta_ofs = 0x98,
> +};
> +
> +static const struct mtk_gate_regs nna5_cg_regs = {
> +       .set_ofs = 0x9c,
> +       .clr_ofs = 0x9c,
> +       .sta_ofs = 0x9c,
> +};
> +
> +static const struct mtk_gate_regs nna6_cg_regs = {
> +       .set_ofs = 0xa0,
> +       .clr_ofs = 0xa0,
> +       .sta_ofs = 0xa0,
> +};
> +
> +static const struct mtk_gate_regs nna7_cg_regs = {
> +       .set_ofs = 0xa4,
> +       .clr_ofs = 0xa4,
> +       .sta_ofs = 0xa4,
> +};

Unfortunately this hardware block is not documented in the datasheets,
so I can't verify these register offsets.

> +
> +#define GATE_NNA0(_id, _name, _parent, _shift)                 \
> +       GATE_MTK(_id, _name, _parent, &nna0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
> +
> +#define GATE_NNA1(_id, _name, _parent, _shift)                 \
> +       GATE_MTK(_id, _name, _parent, &nna1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
> +
> +#define GATE_NNA2(_id, _name, _parent, _shift)                 \
> +       GATE_MTK(_id, _name, _parent, &nna2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
> +
> +#define GATE_NNA3(_id, _name, _parent, _shift)                 \
> +       GATE_MTK(_id, _name, _parent, &nna3_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
> +
> +#define GATE_NNA4(_id, _name, _parent, _shift)                 \
> +       GATE_MTK(_id, _name, _parent, &nna4_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
> +
> +#define GATE_NNA5(_id, _name, _parent, _shift)                 \
> +       GATE_MTK(_id, _name, _parent, &nna5_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
> +
> +#define GATE_NNA6(_id, _name, _parent, _shift)                 \
> +       GATE_MTK(_id, _name, _parent, &nna6_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
> +
> +#define GATE_NNA7(_id, _name, _parent, _shift)                 \
> +       GATE_MTK(_id, _name, _parent, &nna7_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)

Defining a bunch of macros, only to have each of them used once doesn't
provide any gains with regards to reusing code. Please consider just using
GATE_MTK directly below.

In the general case I would probably make some derivatives of GATE_MTK,
such that the ops field (which seems to be the longest) is hidden, but
all the other fields are exposed.

> +static const struct mtk_gate nna_clks[] = {
> +       /* NNA0 */
> +       GATE_NNA0(CLK_NNA_F26M, "nna_f26m", "clk26m", 0),
> +       /* NNA1 */
> +       GATE_NNA1(CLK_NNA_AXI, "nna_axi", "axi_sel", 0),
> +       /* NNA2 */
> +       GATE_NNA2(CLK_NNA_NNA0, "nna_nna0", "nna0_sel", 0),
> +       /* NNA3 */
> +       GATE_NNA3(CLK_NNA_NNA1, "nna_nna1", "nna0_sel", 0),

Is this correct? I would expect the clock for nna1 to be fed from
"nna1_sel".

ChenYu

> +       /* NNA4 */
> +       GATE_NNA4(CLK_NNA_NNA0_EMI, "nna_nna0_emi", "mem_466m", 0),
> +       GATE_NNA4(CLK_NNA_CKGEN_MEM, "nna_ckgen_mem", "mem_466m", 4),
> +       /* NNA5 */
> +       GATE_NNA5(CLK_NNA_NNA1_EMI, "nna_nna1_emi", "mem_466m", 0),
> +       /* NNA6 */
> +       GATE_NNA6(CLK_NNA_NNA0_AXI, "nna_nna0_axi", "axi_sel", 0),
> +       /* NNA7 */
> +       GATE_NNA7(CLK_NNA_NNA1_AXI, "nna_nna1_axi", "axi_sel", 0),
> +};
> +
> +static const struct mtk_clk_desc nna_desc = {
> +       .clks = nna_clks,
> +       .num_clks = ARRAY_SIZE(nna_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8195_nna[] = {
> +       {
> +               .compatible = "mediatek,mt8195-nnasys",
> +               .data = &nna_desc,
> +       }, {
> +               /* sentinel */
> +       }
> +};
> +
> +static struct platform_driver clk_mt8195_nna_drv = {
> +       .probe = mtk_clk_simple_probe,
> +       .driver = {
> +               .name = "clk-mt8195-nna",
> +               .of_match_table = of_match_clk_mt8195_nna,
> +       },
> +};
> +
> +builtin_platform_driver(clk_mt8195_nna_drv);
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 14/22] clk: mediatek: Add MT8195 vdecsys clock support
  2021-06-16 22:47 ` [PATCH 14/22] clk: mediatek: Add MT8195 vdecsys " Chun-Jie Chen
@ 2021-07-09  8:40   ` Chen-Yu Tsai
  2021-07-12  1:34     ` Chun-Jie Chen
  0 siblings, 1 reply; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-09  8:40 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

On Thu, Jun 17, 2021 at 7:02 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 vdecsys clock providers
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  drivers/clk/mediatek/Kconfig           |   6 ++
>  drivers/clk/mediatek/Makefile          |   1 +
>  drivers/clk/mediatek/clk-mt8195-vdec.c | 106 +++++++++++++++++++++++++
>  3 files changed, 113 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt8195-vdec.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index d34517728f4a..b7881b8ebb23 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -642,6 +642,12 @@ config COMMON_CLK_MT8195_NNASYS
>         help
>           This driver supports MediaTek MT8195 nnasys clocks.
>
> +config COMMON_CLK_MT8195_VDECSYS
> +       bool "Clock driver for MediaTek MT8195 vdecsys"
> +       depends on COMMON_CLK_MT8195
> +       help
> +         This driver supports MediaTek MT8195 vdecsys clocks.
> +

Same comments about the commit log and Kconfig option.

>  config COMMON_CLK_MT8516
>         bool "Clock driver for MediaTek MT8516"
>         depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 49e585a7ac8e..9acfa705f1de 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -90,5 +90,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_IPESYS) += clk-mt8195-ipe.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_MFGCFG) += clk-mt8195-mfg.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_SCP_ADSP) += clk-mt8195-scp_adsp.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_NNASYS) += clk-mt8195-nna.o
> +obj-$(CONFIG_COMMON_CLK_MT8195_VDECSYS) += clk-mt8195-vdec.o
>  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
>  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-vdec.c b/drivers/clk/mediatek/clk-mt8195-vdec.c
> new file mode 100644
> index 000000000000..9ab84e75e1a0
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-vdec.c
> @@ -0,0 +1,106 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"

Please order alphabetically. I think this applies to all the other patches.
I missed this in the earlier ones, but please fix them nonetheless.

> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +
> +static const struct mtk_gate_regs vdec0_cg_regs = {
> +       .set_ofs = 0x0,
> +       .clr_ofs = 0x4,
> +       .sta_ofs = 0x0,
> +};
> +
> +static const struct mtk_gate_regs vdec1_cg_regs = {
> +       .set_ofs = 0x200,
> +       .clr_ofs = 0x204,
> +       .sta_ofs = 0x200,
> +};
> +
> +static const struct mtk_gate_regs vdec2_cg_regs = {
> +       .set_ofs = 0x8,
> +       .clr_ofs = 0xc,
> +       .sta_ofs = 0x8,
> +};
> +
> +#define GATE_VDEC0(_id, _name, _parent, _shift)                        \
> +       GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
> +
> +#define GATE_VDEC1(_id, _name, _parent, _shift)                        \
> +       GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
> +
> +#define GATE_VDEC2(_id, _name, _parent, _shift)                        \
> +       GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
> +
> +static const struct mtk_gate vdec_clks[] = {
> +       /* VDEC0 */
> +       GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec", "vdec_sel", 0),
> +       /* VDEC1 */
> +       GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat", "vdec_sel", 0),
> +       /* VDEC2 */
> +       GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1", "vdec_sel", 0),
> +};
> +
> +static const struct mtk_gate vdec_core1_clks[] = {
> +       /* VDEC0 */
> +       GATE_VDEC0(CLK_VDEC_CORE1_VDEC, "vdec_core1_vdec", "vdec_sel", 0),
> +       /* VDEC1 */
> +       GATE_VDEC1(CLK_VDEC_CORE1_LAT, "vdec_core1_lat", "vdec_sel", 0),
> +       /* VDEC2 */
> +       GATE_VDEC2(CLK_VDEC_CORE1_LARB1, "vdec_core1_larb1", "vdec_sel", 0),
> +};
> +
> +static const struct mtk_gate vdec_soc_clks[] = {
> +       /* VDEC0 */
> +       GATE_VDEC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec", "vdec_sel", 0),
> +       /* VDEC1 */
> +       GATE_VDEC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat", "vdec_sel", 0),
> +       /* VDEC2 */
> +       GATE_VDEC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1", "vdec_sel", 0),
> +};
> +
> +static const struct mtk_clk_desc vdec_desc = {
> +       .clks = vdec_clks,
> +       .num_clks = ARRAY_SIZE(vdec_clks),
> +};
> +
> +static const struct mtk_clk_desc vdec_core1_desc = {
> +       .clks = vdec_core1_clks,
> +       .num_clks = ARRAY_SIZE(vdec_core1_clks),
> +};
> +
> +static const struct mtk_clk_desc vdec_soc_desc = {
> +       .clks = vdec_soc_clks,
> +       .num_clks = ARRAY_SIZE(vdec_soc_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8195_vdec[] = {
> +       {
> +               .compatible = "mediatek,mt8195-vdecsys",
> +               .data = &vdec_desc,
> +       }, {
> +               .compatible = "mediatek,mt8195-vdecsys_core1",
> +               .data = &vdec_core1_desc,
> +       }, {
> +               .compatible = "mediatek,mt8195-vdecsys_soc",
> +               .data = &vdec_soc_desc,
> +       }, {
> +               /* sentinel */
> +       }
> +};
> +
> +static struct platform_driver clk_mt8195_vdec_drv = {
> +       .probe = mtk_clk_simple_probe,
> +       .driver = {
> +               .name = "clk-mt8195-vdec",
> +               .of_match_table = of_match_clk_mt8195_vdec,
> +       },
> +};
> +

Nit: you could drop the empty line here. Same in the other patches.

ChenYu


> +builtin_platform_driver(clk_mt8195_vdec_drv);
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 15/22] clk: mediatek: Add MT8195 vdosys0 clock support
  2021-06-16 22:47 ` [PATCH 15/22] clk: mediatek: Add MT8195 vdosys0 " Chun-Jie Chen
@ 2021-07-09  8:51   ` Chen-Yu Tsai
  0 siblings, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-09  8:51 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

Hi,

On Thu, Jun 17, 2021 at 7:03 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 vdosys0 clock provider
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  drivers/clk/mediatek/Kconfig           |   6 ++
>  drivers/clk/mediatek/Makefile          |   1 +
>  drivers/clk/mediatek/clk-mt8195-vdo0.c | 114 +++++++++++++++++++++++++
>  3 files changed, 121 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt8195-vdo0.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index b7881b8ebb23..6602f9ba13c7 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -648,6 +648,12 @@ config COMMON_CLK_MT8195_VDECSYS
>         help
>           This driver supports MediaTek MT8195 vdecsys clocks.
>
> +config COMMON_CLK_MT8195_VDOSYS0
> +       bool "Clock driver for MediaTek MT8195 vdosys0"
> +       depends on COMMON_CLK_MT8195
> +       help
> +         This driver supports MediaTek MT8195 vdosys0 clocks.
> +

Same comments about commit log and Kconfig option.

>  config COMMON_CLK_MT8516
>         bool "Clock driver for MediaTek MT8516"
>         depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 9acfa705f1de..6aa1ba00342a 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -91,5 +91,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_MFGCFG) += clk-mt8195-mfg.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_SCP_ADSP) += clk-mt8195-scp_adsp.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_NNASYS) += clk-mt8195-nna.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_VDECSYS) += clk-mt8195-vdec.o
> +obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS0) += clk-mt8195-vdo0.o
>  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
>  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/clk-mt8195-vdo0.c
> new file mode 100644
> index 000000000000..4a34ccb0beed
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c
> @@ -0,0 +1,114 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"

Alphabetical order within the same group please.

> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +
> +static const struct mtk_gate_regs vdo00_cg_regs = {
> +       .set_ofs = 0x104,
> +       .clr_ofs = 0x108,
> +       .sta_ofs = 0x100,
> +};
> +
> +static const struct mtk_gate_regs vdo01_cg_regs = {
> +       .set_ofs = 0x114,
> +       .clr_ofs = 0x118,
> +       .sta_ofs = 0x110,
> +};
> +
> +static const struct mtk_gate_regs vdo02_cg_regs = {
> +       .set_ofs = 0x124,
> +       .clr_ofs = 0x128,
> +       .sta_ofs = 0x120,
> +};
> +
> +#define GATE_VDO00(_id, _name, _parent, _shift)                        \
> +       GATE_MTK(_id, _name, _parent, &vdo00_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO01(_id, _name, _parent, _shift)                        \
> +       GATE_MTK(_id, _name, _parent, &vdo01_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO02(_id, _name, _parent, _shift)                        \
> +       GATE_MTK(_id, _name, _parent, &vdo02_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate vdo0_clks[] = {
> +       /* VDO00 */
> +       GATE_VDO00(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "vpp_sel", 0),
> +       GATE_VDO00(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0", "vpp_sel", 2),
> +       GATE_VDO00(CLK_VDO0_DISP_COLOR1, "vdo0_disp_color1", "vpp_sel", 3),
> +       GATE_VDO00(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0", "vpp_sel", 4),
> +       GATE_VDO00(CLK_VDO0_DISP_CCORR1, "vdo0_disp_ccorr1", "vpp_sel", 5),
> +       GATE_VDO00(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0", "vpp_sel", 6),
> +       GATE_VDO00(CLK_VDO0_DISP_AAL1, "vdo0_disp_aal1", "vpp_sel", 7),
> +       GATE_VDO00(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0", "vpp_sel", 8),
> +       GATE_VDO00(CLK_VDO0_DISP_GAMMA1, "vdo0_disp_gamma1", "vpp_sel", 9),
> +       GATE_VDO00(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0", "vpp_sel", 10),
> +       GATE_VDO00(CLK_VDO0_DISP_DITHER1, "vdo0_disp_dither1", "vpp_sel", 11),
> +       GATE_VDO00(CLK_VDO0_DISP_OVL1, "vdo0_disp_ovl1", "vpp_sel", 16),
> +       GATE_VDO00(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0", "vpp_sel", 17),
> +       GATE_VDO00(CLK_VDO0_DISP_WDMA1, "vdo0_disp_wdma1", "vpp_sel", 18),
> +       GATE_VDO00(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0", "vpp_sel", 19),
> +       GATE_VDO00(CLK_VDO0_DISP_RDMA1, "vdo0_disp_rdma1", "vpp_sel", 20),
> +       GATE_VDO00(CLK_VDO0_DSI0, "vdo0_dsi0", "vpp_sel", 21),
> +       GATE_VDO00(CLK_VDO0_DSI1, "vdo0_dsi1", "vpp_sel", 22),
> +       GATE_VDO00(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0", "vpp_sel", 23),
> +       GATE_VDO00(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0", "vpp_sel", 24),
> +       GATE_VDO00(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "vpp_sel", 25),
> +       GATE_VDO00(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0", "vpp_sel", 26),
> +       GATE_VDO00(CLK_VDO0_DISP_IL_ROT0, "vdo0_disp_il_rot0", "vpp_sel", 27),
> +       GATE_VDO00(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "vpp_sel", 28),
> +       GATE_VDO00(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0", "vpp_sel", 29),
> +       GATE_VDO00(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1", "vpp_sel", 30),
> +       /* VDO01 */
> +       GATE_VDO01(CLK_VDO0_DL_ASYNC0, "vdo0_dl_async0", "vpp_sel", 0),
> +       GATE_VDO01(CLK_VDO0_DL_ASYNC1, "vdo0_dl_async1", "vpp_sel", 1),
> +       GATE_VDO01(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2", "vpp_sel", 2),
> +       GATE_VDO01(CLK_VDO0_DL_ASYNC3, "vdo0_dl_async3", "vpp_sel", 3),
> +       GATE_VDO01(CLK_VDO0_DL_ASYNC4, "vdo0_dl_async4", "vpp_sel", 4),
> +       GATE_VDO01(CLK_VDO0_DISP_MONITOR0, "vdo0_disp_monitor0", "vpp_sel", 5),
> +       GATE_VDO01(CLK_VDO0_DISP_MONITOR1, "vdo0_disp_monitor1", "vpp_sel", 6),
> +       GATE_VDO01(CLK_VDO0_DISP_MONITOR2, "vdo0_disp_monitor2", "vpp_sel", 7),
> +       GATE_VDO01(CLK_VDO0_DISP_MONITOR3, "vdo0_disp_monitor3", "vpp_sel", 8),
> +       GATE_VDO01(CLK_VDO0_DISP_MONITOR4, "vdo0_disp_monitor4", "vpp_sel", 9),
> +       GATE_VDO01(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "vpp_sel", 10),
> +       GATE_VDO01(CLK_VDO0_SMI_COMMON, "vdo0_smi_common", "vpp_sel", 11),
> +       GATE_VDO01(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "vpp_sel", 12),
> +       GATE_VDO01(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu", "vpp_sel", 13),
> +       GATE_VDO01(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "vpp_sel", 14),
> +       GATE_VDO01(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "vpp_sel", 15),
> +       /* VDO02 */
> +       GATE_VDO02(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "dsi_occ_sel", 0),
> +       GATE_VDO02(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "dsi_occ_sel", 8),
> +       GATE_VDO02(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf", "edp_sel", 16),
> +};
> +
> +static const struct mtk_clk_desc vdo0_desc = {
> +       .clks = vdo0_clks,
> +       .num_clks = ARRAY_SIZE(vdo0_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8195_vdo0[] = {
> +       {
> +               .compatible = "mediatek,mt8195-vdosys0",
> +               .data = &vdo0_desc,
> +       }, {
> +               /* sentinel */
> +       }
> +};
> +
> +static struct platform_driver clk_mt8195_vdo0_drv = {
> +       .probe = mtk_clk_simple_probe,
> +       .driver = {
> +               .name = "clk-mt8195-vdo0",
> +               .of_match_table = of_match_clk_mt8195_vdo0,
> +       },
> +};
> +

Can drop the empty line here.

Overall the code looks good.


ChenYu


> +builtin_platform_driver(clk_mt8195_vdo0_drv);
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 16/22] clk: mediatek: Add MT8195 vdosys1 clock support
  2021-06-16 22:47 ` [PATCH 16/22] clk: mediatek: Add MT8195 vdosys1 " Chun-Jie Chen
@ 2021-07-09  9:30   ` Chen-Yu Tsai
  0 siblings, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-09  9:30 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

On Thu, Jun 17, 2021 at 7:03 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 vdosys1 clock provider
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  drivers/clk/mediatek/Kconfig           |   6 ++
>  drivers/clk/mediatek/Makefile          |   1 +
>  drivers/clk/mediatek/clk-mt8195-vdo1.c | 131 +++++++++++++++++++++++++
>  3 files changed, 138 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt8195-vdo1.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 6602f9ba13c7..1e89c68f6c6c 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -654,6 +654,12 @@ config COMMON_CLK_MT8195_VDOSYS0
>         help
>           This driver supports MediaTek MT8195 vdosys0 clocks.
>
> +config COMMON_CLK_MT8195_VDOSYS1
> +       bool "Clock driver for MediaTek MT8195 vdosys1"
> +       depends on COMMON_CLK_MT8195
> +       help
> +         This driver supports MediaTek MT8195 vdosys1 clocks.
> +
>  config COMMON_CLK_MT8516
>         bool "Clock driver for MediaTek MT8516"
>         depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 6aa1ba00342a..76c0fa837cb0 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -92,5 +92,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_SCP_ADSP) += clk-mt8195-scp_adsp.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_NNASYS) += clk-mt8195-nna.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_VDECSYS) += clk-mt8195-vdec.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS0) += clk-mt8195-vdo0.o
> +obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS1) += clk-mt8195-vdo1.o
>  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
>  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/clk-mt8195-vdo1.c
> new file mode 100644
> index 000000000000..4d16f2e9c03a
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c
> @@ -0,0 +1,131 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +
> +static const struct mtk_gate_regs vdo10_cg_regs = {

You might want to name these vdo1_X_cg_regs. This would be easier to read
and parse.

> +       .set_ofs = 0x104,
> +       .clr_ofs = 0x108,
> +       .sta_ofs = 0x100,
> +};
> +
> +static const struct mtk_gate_regs vdo11_cg_regs = {
> +       .set_ofs = 0x124,
> +       .clr_ofs = 0x128,
> +       .sta_ofs = 0x120,
> +};
> +
> +static const struct mtk_gate_regs vdo12_cg_regs = {
> +       .set_ofs = 0x134,
> +       .clr_ofs = 0x138,
> +       .sta_ofs = 0x130,
> +};
> +
> +static const struct mtk_gate_regs vdo13_cg_regs = {
> +       .set_ofs = 0x144,
> +       .clr_ofs = 0x148,
> +       .sta_ofs = 0x140,
> +};
> +
> +#define GATE_VDO10(_id, _name, _parent, _shift)                        \
> +       GATE_MTK(_id, _name, _parent, &vdo10_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO11(_id, _name, _parent, _shift)                        \
> +       GATE_MTK(_id, _name, _parent, &vdo11_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO12(_id, _name, _parent, _shift)                        \
> +       GATE_MTK(_id, _name, _parent, &vdo12_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO13(_id, _name, _parent, _shift)                        \
> +       GATE_MTK(_id, _name, _parent, &vdo13_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate vdo1_clks[] = {
> +       /* VDO10 */
> +       GATE_VDO10(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2", "vpp_sel", 0),
> +       GATE_VDO10(CLK_VDO1_SMI_LARB3, "vdo1_smi_larb3", "vpp_sel", 1),
> +       GATE_VDO10(CLK_VDO1_GALS, "vdo1_gals", "vpp_sel", 2),
> +       GATE_VDO10(CLK_VDO1_FAKE_ENG0, "vdo1_fake_eng0", "vpp_sel", 3),
> +       GATE_VDO10(CLK_VDO1_FAKE_ENG, "vdo1_fake_eng", "vpp_sel", 4),
> +       GATE_VDO10(CLK_VDO1_MDP_RDMA0, "vdo1_mdp_rdma0", "vpp_sel", 5),
> +       GATE_VDO10(CLK_VDO1_MDP_RDMA1, "vdo1_mdp_rdma1", "vpp_sel", 6),
> +       GATE_VDO10(CLK_VDO1_MDP_RDMA2, "vdo1_mdp_rdma2", "vpp_sel", 7),
> +       GATE_VDO10(CLK_VDO1_MDP_RDMA3, "vdo1_mdp_rdma3", "vpp_sel", 8),
> +       GATE_VDO10(CLK_VDO1_VPP_MERGE0, "vdo1_vpp_merge0", "vpp_sel", 9),
> +       GATE_VDO10(CLK_VDO1_VPP_MERGE1, "vdo1_vpp_merge1", "vpp_sel", 10),
> +       GATE_VDO10(CLK_VDO1_VPP_MERGE2, "vdo1_vpp_merge2", "vpp_sel", 11),
> +       GATE_VDO10(CLK_VDO1_VPP_MERGE3, "vdo1_vpp_merge3", "vpp_sel", 12),
> +       GATE_VDO10(CLK_VDO1_VPP_MERGE4, "vdo1_vpp_merge4", "vpp_sel", 13),
> +       GATE_VDO10(CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC, "vdo1_vpp2_to_vdo1_dl_async", "vpp_sel", 14),
> +       GATE_VDO10(CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC, "vdo1_vpp3_to_vdo1_dl_async", "vpp_sel", 15),
> +       GATE_VDO10(CLK_VDO1_DISP_MUTEX, "vdo1_disp_mutex", "vpp_sel", 16),
> +       GATE_VDO10(CLK_VDO1_MDP_RDMA4, "vdo1_mdp_rdma4", "vpp_sel", 17),
> +       GATE_VDO10(CLK_VDO1_MDP_RDMA5, "vdo1_mdp_rdma5", "vpp_sel", 18),
> +       GATE_VDO10(CLK_VDO1_MDP_RDMA6, "vdo1_mdp_rdma6", "vpp_sel", 19),
> +       GATE_VDO10(CLK_VDO1_MDP_RDMA7, "vdo1_mdp_rdma7", "vpp_sel", 20),
> +       GATE_VDO10(CLK_VDO1_DP_INTF0_MM, "vdo1_dp_intf0_mm", "vpp_sel", 21),
> +       GATE_VDO10(CLK_VDO1_DPI0_MM, "vdo1_dpi0_mm", "vpp_sel", 22),
> +       GATE_VDO10(CLK_VDO1_DPI1_MM, "vdo1_dpi1_mm", "vpp_sel", 23),
> +       GATE_VDO10(CLK_VDO1_DISP_MONITOR, "vdo1_disp_monitor", "vpp_sel", 24),
> +       GATE_VDO10(CLK_VDO1_MERGE0_DL_ASYNC, "vdo1_merge0_dl_async", "vpp_sel", 25),
> +       GATE_VDO10(CLK_VDO1_MERGE1_DL_ASYNC, "vdo1_merge1_dl_async", "vpp_sel", 26),
> +       GATE_VDO10(CLK_VDO1_MERGE2_DL_ASYNC, "vdo1_merge2_dl_async", "vpp_sel", 27),
> +       GATE_VDO10(CLK_VDO1_MERGE3_DL_ASYNC, "vdo1_merge3_dl_async", "vpp_sel", 28),
> +       GATE_VDO10(CLK_VDO1_MERGE4_DL_ASYNC, "vdo1_merge4_dl_async", "vpp_sel", 29),
> +       GATE_VDO10(CLK_VDO1_VDO0_DSC_TO_VDO1_DL_ASYNC, "vdo1_vdo0_dsc_to_vdo1_dl_async",
> +               "vpp_sel", 30),
> +       GATE_VDO10(CLK_VDO1_VDO0_MERGE_TO_VDO1_DL_ASYNC, "vdo1_vdo0_merge_to_vdo1_dl_async",
> +               "vpp_sel", 31),
> +       /* VDO11 */
> +       GATE_VDO11(CLK_VDO1_HDR_VDO_FE0, "vdo1_hdr_vdo_fe0", "vpp_sel", 0),
> +       GATE_VDO11(CLK_VDO1_HDR_GFX_FE0, "vdo1_hdr_gfx_fe0", "vpp_sel", 1),
> +       GATE_VDO11(CLK_VDO1_HDR_VDO_BE, "vdo1_hdr_vdo_be", "vpp_sel", 2),
> +       GATE_VDO11(CLK_VDO1_HDR_VDO_FE1, "vdo1_hdr_vdo_fe1", "vpp_sel", 16),
> +       GATE_VDO11(CLK_VDO1_HDR_GFX_FE1, "vdo1_hdr_gfx_fe1", "vpp_sel", 17),
> +       GATE_VDO11(CLK_VDO1_DISP_MIXER, "vdo1_disp_mixer", "vpp_sel", 18),
> +       GATE_VDO11(CLK_VDO1_HDR_VDO_FE0_DL_ASYNC, "vdo1_hdr_vdo_fe0_dl_async", "vpp_sel", 19),
> +       GATE_VDO11(CLK_VDO1_HDR_VDO_FE1_DL_ASYNC, "vdo1_hdr_vdo_fe1_dl_async", "vpp_sel", 20),
> +       GATE_VDO11(CLK_VDO1_HDR_GFX_FE0_DL_ASYNC, "vdo1_hdr_gfx_fe0_dl_async", "vpp_sel", 21),
> +       GATE_VDO11(CLK_VDO1_HDR_GFX_FE1_DL_ASYNC, "vdo1_hdr_gfx_fe1_dl_async", "vpp_sel", 22),
> +       GATE_VDO11(CLK_VDO1_HDR_VDO_BE_DL_ASYNC, "vdo1_hdr_vdo_be_dl_async", "vpp_sel", 23),
> +       /* VDO12 */
> +       GATE_VDO12(CLK_VDO1_DPI0, "vdo1_dpi0", "vpp_sel", 0),
> +       GATE_VDO12(CLK_VDO1_DISP_MONITOR_DPI0, "vdo1_disp_monitor_dpi0", "vpp_sel", 1),
> +       GATE_VDO12(CLK_VDO1_DPI1, "vdo1_dpi1", "vpp_sel", 8),
> +       GATE_VDO12(CLK_VDO1_DISP_MONITOR_DPI1, "vdo1_disp_monitor_dpi1", "vpp_sel", 9),
> +       GATE_VDO12(CLK_VDO1_DPINTF, "vdo1_dpintf", "vpp_sel", 16),
> +       GATE_VDO12(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf", "vpp_sel", 17),
> +       /* VDO13 */
> +       GATE_VDO13(CLK_VDO1_26M_SLOW, "vdo1_26m_slow", "clk26m", 8),
> +};
> +
> +static const struct mtk_clk_desc vdo1_desc = {
> +       .clks = vdo1_clks,
> +       .num_clks = ARRAY_SIZE(vdo1_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8195_vdo1[] = {
> +       {
> +               .compatible = "mediatek,mt8195-vdosys1",
> +               .data = &vdo1_desc,
> +       }, {
> +               /* sentinel */
> +       }
> +};
> +
> +static struct platform_driver clk_mt8195_vdo1_drv = {
> +       .probe = mtk_clk_simple_probe,
> +       .driver = {
> +               .name = "clk-mt8195-vdo1",
> +               .of_match_table = of_match_clk_mt8195_vdo1,
> +       },
> +};
> +
> +builtin_platform_driver(clk_mt8195_vdo1_drv);

Same general comments as the previous patch applies. Code looks good
otherwise.

ChenYu

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 17/22] clk: mediatek: Add MT8195 vencsys clock support
  2021-06-16 22:47 ` [PATCH 17/22] clk: mediatek: Add MT8195 vencsys " Chun-Jie Chen
@ 2021-07-09 10:26   ` Chen-Yu Tsai
  0 siblings, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-09 10:26 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

On Thu, Jun 17, 2021 at 7:10 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 vencsys clock providers
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  drivers/clk/mediatek/Kconfig           |  6 +++
>  drivers/clk/mediatek/Makefile          |  1 +
>  drivers/clk/mediatek/clk-mt8195-venc.c | 71 ++++++++++++++++++++++++++
>  3 files changed, 78 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt8195-venc.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 1e89c68f6c6c..3352686d98cf 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -660,6 +660,12 @@ config COMMON_CLK_MT8195_VDOSYS1
>         help
>           This driver supports MediaTek MT8195 vdosys1 clocks.
>
> +config COMMON_CLK_MT8195_VENCSYS
> +       bool "Clock driver for MediaTek MT8195 vencsys"
> +       depends on COMMON_CLK_MT8195
> +       help
> +         This driver supports MediaTek MT8195 vencsys clocks.
> +
>  config COMMON_CLK_MT8516
>         bool "Clock driver for MediaTek MT8516"
>         depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 76c0fa837cb0..76a6b404e34b 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -93,5 +93,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_NNASYS) += clk-mt8195-nna.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_VDECSYS) += clk-mt8195-vdec.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS0) += clk-mt8195-vdo0.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS1) += clk-mt8195-vdo1.o
> +obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
>  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
>  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-venc.c b/drivers/clk/mediatek/clk-mt8195-venc.c
> new file mode 100644
> index 000000000000..410ca69d5759
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-venc.c
> @@ -0,0 +1,71 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +
> +static const struct mtk_gate_regs venc_cg_regs = {
> +       .set_ofs = 0x4,
> +       .clr_ofs = 0x8,
> +       .sta_ofs = 0x0,
> +};
> +
> +#define GATE_VENC(_id, _name, _parent, _shift)                 \
> +       GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
> +
> +static const struct mtk_gate venc_clks[] = {
> +       GATE_VENC(CLK_VENC_LARB, "venc_larb", "venc_sel", 0),
> +       GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4),
> +       GATE_VENC(CLK_VENC_JPGENC, "venc_jpgenc", "venc_sel", 8),
> +       GATE_VENC(CLK_VENC_JPGDEC, "venc_jpgdec", "venc_sel", 12),
> +       GATE_VENC(CLK_VENC_JPGDEC_C1, "venc_jpgdec_c1", "venc_sel", 16),
> +       GATE_VENC(CLK_VENC_GALS, "venc_gals", "venc_sel", 28),
> +};
> +
> +static const struct mtk_gate venc_core1_clks[] = {
> +       GATE_VENC(CLK_VENC_CORE1_LARB, "venc_core1_larb", "venc_sel", 0),
> +       GATE_VENC(CLK_VENC_CORE1_VENC, "venc_core1_venc", "venc_sel", 4),
> +       GATE_VENC(CLK_VENC_CORE1_JPGENC, "venc_core1_jpgenc", "venc_sel", 8),
> +       GATE_VENC(CLK_VENC_CORE1_JPGDEC, "venc_core1_jpgdec", "venc_sel", 12),
> +       GATE_VENC(CLK_VENC_CORE1_JPGDEC_C1, "venc_core1_jpgdec_c1", "venc_sel", 16),
> +       GATE_VENC(CLK_VENC_CORE1_GALS, "venc_core1_gals", "venc_sel", 28),
> +};

So I'm not sure why there are two sets of clocks for each endpoint.
Since this hardware block is not documented in the datasheet, maybe
you could provide some explanation? What I'm wondering is if the
first set is actually some clock gate for bus access and the second
set is the main module clock that drives the internal logic.

The general comments from the other patches apply as well.


ChenYu

> +
> +static const struct mtk_clk_desc venc_desc = {
> +       .clks = venc_clks,
> +       .num_clks = ARRAY_SIZE(venc_clks),
> +};
> +
> +static const struct mtk_clk_desc venc_core1_desc = {
> +       .clks = venc_core1_clks,
> +       .num_clks = ARRAY_SIZE(venc_core1_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8195_venc[] = {
> +       {
> +               .compatible = "mediatek,mt8195-vencsys",
> +               .data = &venc_desc,
> +       }, {
> +               .compatible = "mediatek,mt8195-vencsys_core1",
> +               .data = &venc_core1_desc,
> +       }, {
> +               /* sentinel */
> +       }
> +};
> +
> +static struct platform_driver clk_mt8195_venc_drv = {
> +       .probe = mtk_clk_simple_probe,
> +       .driver = {
> +               .name = "clk-mt8195-venc",
> +               .of_match_table = of_match_clk_mt8195_venc,
> +       },
> +};
> +
> +builtin_platform_driver(clk_mt8195_venc_drv);
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 18/22] clk: mediatek: Add MT8195 vppsys0 clock support
  2021-06-16 22:47 ` [PATCH 18/22] clk: mediatek: Add MT8195 vppsys0 " Chun-Jie Chen
@ 2021-07-09 10:38   ` Chen-Yu Tsai
  0 siblings, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-09 10:38 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

Hi,

On Thu, Jun 17, 2021 at 7:10 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 vppsys0 clock provider
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  drivers/clk/mediatek/Kconfig           |   6 ++
>  drivers/clk/mediatek/Makefile          |   1 +
>  drivers/clk/mediatek/clk-mt8195-vpp0.c | 112 +++++++++++++++++++++++++
>  3 files changed, 119 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt8195-vpp0.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 3352686d98cf..2deef026fbb4 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -666,6 +666,12 @@ config COMMON_CLK_MT8195_VENCSYS
>         help
>           This driver supports MediaTek MT8195 vencsys clocks.
>
> +config COMMON_CLK_MT8195_VPPSYS0
> +       bool "Clock driver for MediaTek MT8195 vppsys0"
> +       depends on COMMON_CLK_MT8195
> +       help
> +         This driver supports MediaTek MT8195 vppsys0 clocks.
> +
>  config COMMON_CLK_MT8516
>         bool "Clock driver for MediaTek MT8516"
>         depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 76a6b404e34b..34cd7f2c71ac 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -94,5 +94,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VDECSYS) += clk-mt8195-vdec.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS0) += clk-mt8195-vdo0.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS1) += clk-mt8195-vdo1.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
> +obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS0) += clk-mt8195-vpp0.o
>  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
>  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-vpp0.c b/drivers/clk/mediatek/clk-mt8195-vpp0.c
> new file mode 100644
> index 000000000000..cecd8fab7b7e
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-vpp0.c
> @@ -0,0 +1,112 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +
> +static const struct mtk_gate_regs vpp00_cg_regs = {

Like with VDOSYS, please add a separator between the two indices.

> +       .set_ofs = 0x24,
> +       .clr_ofs = 0x28,
> +       .sta_ofs = 0x20,
> +};
> +
> +static const struct mtk_gate_regs vpp01_cg_regs = {
> +       .set_ofs = 0x30,
> +       .clr_ofs = 0x34,
> +       .sta_ofs = 0x2c,
> +};
> +
> +static const struct mtk_gate_regs vpp02_cg_regs = {
> +       .set_ofs = 0x3c,
> +       .clr_ofs = 0x40,
> +       .sta_ofs = 0x38,
> +};
> +
> +#define GATE_VPP00(_id, _name, _parent, _shift)                        \
> +       GATE_MTK(_id, _name, _parent, &vpp00_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VPP01(_id, _name, _parent, _shift)                        \
> +       GATE_MTK(_id, _name, _parent, &vpp01_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VPP02(_id, _name, _parent, _shift)                        \
> +       GATE_MTK(_id, _name, _parent, &vpp02_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate vpp0_clks[] = {
> +       /* VPP00 */
> +       GATE_VPP00(CLK_VPP0_MDP_FG, "vpp0_mdp_fg", "vpp_sel", 1),
> +       GATE_VPP00(CLK_VPP0_STITCH, "vpp0_stitch", "vpp_sel", 2),
> +       GATE_VPP00(CLK_VPP0_PADDING, "vpp0_padding", "vpp_sel", 7),
> +       GATE_VPP00(CLK_VPP0_MDP_TCC, "vpp0_mdp_tcc", "vpp_sel", 8),
> +       GATE_VPP00(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx", "vpp_sel", 10),
> +       GATE_VPP00(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx", "vpp_sel", 11),
> +       GATE_VPP00(CLK_VPP0_MUTEX, "vpp0_mutex", "vpp_sel", 13),
> +       GATE_VPP00(CLK_VPP0_VPP02VPP1_RELAY, "vpp0_vpp02vpp1_relay", "vpp_sel", 14),
> +       GATE_VPP00(CLK_VPP0_VPP12VPP0_ASYNC, "vpp0_vpp12vpp0_async", "vpp_sel", 15),
> +       GATE_VPP00(CLK_VPP0_MMSYSRAM_TOP, "vpp0_mmsysram_top", "vpp_sel", 16),
> +       GATE_VPP00(CLK_VPP0_MDP_AAL, "vpp0_mdp_aal", "vpp_sel", 17),
> +       GATE_VPP00(CLK_VPP0_MDP_RSZ, "vpp0_mdp_rsz", "vpp_sel", 18),
> +       /* VPP01 */
> +       GATE_VPP01(CLK_VPP0_SMI_COMMON, "vpp0_smi_common", "vpp_sel", 0),
> +       GATE_VPP01(CLK_VPP0_GALS_VDO0_LARB0, "vpp0_gals_vdo0_larb0", "vpp_sel", 1),
> +       GATE_VPP01(CLK_VPP0_GALS_VDO0_LARB1, "vpp0_gals_vdo0_larb1", "vpp_sel", 2),
> +       GATE_VPP01(CLK_VPP0_GALS_VENCSYS, "vpp0_gals_vencsys", "vpp_sel", 3),
> +       GATE_VPP01(CLK_VPP0_GALS_VENCSYS_CORE1, "vpp0_gals_vencsys_core1", "vpp_sel", 4),
> +       GATE_VPP01(CLK_VPP0_GALS_INFRA, "vpp0_gals_infra", "vpp_sel", 5),
> +       GATE_VPP01(CLK_VPP0_GALS_CAMSYS, "vpp0_gals_camsys", "vpp_sel", 6),
> +       GATE_VPP01(CLK_VPP0_GALS_VPP1_LARB5, "vpp0_gals_vpp1_larb5", "vpp_sel", 7),
> +       GATE_VPP01(CLK_VPP0_GALS_VPP1_LARB6, "vpp0_gals_vpp1_larb6", "vpp_sel", 8),
> +       GATE_VPP01(CLK_VPP0_SMI_REORDER, "vpp0_smi_reorder", "vpp_sel", 9),
> +       GATE_VPP01(CLK_VPP0_SMI_IOMMU, "vpp0_smi_iommu", "vpp_sel", 10),
> +       GATE_VPP01(CLK_VPP0_GALS_IMGSYS_CAMSYS, "vpp0_gals_imgsys_camsys", "vpp_sel", 11),
> +       GATE_VPP01(CLK_VPP0_MDP_RDMA, "vpp0_mdp_rdma", "vpp_sel", 12),
> +       GATE_VPP01(CLK_VPP0_MDP_WROT, "vpp0_mdp_wrot", "vpp_sel", 13),
> +       GATE_VPP01(CLK_VPP0_GALS_EMI0_EMI1, "vpp0_gals_emi0_emi1", "vpp_sel", 16),
> +       GATE_VPP01(CLK_VPP0_SMI_SUB_COMMON_REORDER, "vpp0_smi_sub_common_reorder", "vpp_sel", 17),
> +       GATE_VPP01(CLK_VPP0_SMI_RSI, "vpp0_smi_rsi", "vpp_sel", 18),
> +       GATE_VPP01(CLK_VPP0_SMI_COMMON_LARB4, "vpp0_smi_common_larb4", "vpp_sel", 19),
> +       GATE_VPP01(CLK_VPP0_GALS_VDEC_VDEC_CORE1, "vpp0_gals_vdec_vdec_core1", "vpp_sel", 20),
> +       GATE_VPP01(CLK_VPP0_GALS_VPP1_WPE, "vpp0_gals_vpp1_wpe", "vpp_sel", 21),
> +       GATE_VPP01(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1, "vpp0_gals_vdo0_vdo1_vencsys_core1",
> +               "vpp_sel", 22),
> +       GATE_VPP01(CLK_VPP0_FAKE_ENG, "vpp0_fake_eng", "vpp_sel", 23),
> +       GATE_VPP01(CLK_VPP0_MDP_HDR, "vpp0_mdp_hdr", "vpp_sel", 24),
> +       GATE_VPP01(CLK_VPP0_MDP_TDSHP, "vpp0_mdp_tdshp", "vpp_sel", 25),
> +       GATE_VPP01(CLK_VPP0_MDP_COLOR, "vpp0_mdp_color", "vpp_sel", 26),
> +       GATE_VPP01(CLK_VPP0_MDP_OVL, "vpp0_mdp_ovl", "vpp_sel", 27),
> +       /* VPP02 */
> +       GATE_VPP02(CLK_VPP0_WARP0_RELAY, "vpp0_warp0_relay", "wpe_vpp_sel", 0),
> +       GATE_VPP02(CLK_VPP0_WARP0_MDP_DL_ASYNC, "vpp0_warp0_mdp_dl_async", "wpe_vpp_sel", 1),
> +       GATE_VPP02(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay", "wpe_vpp_sel", 2),
> +       GATE_VPP02(CLK_VPP0_WARP1_MDP_DL_ASYNC, "vpp0_warp1_mdp_dl_async", "wpe_vpp_sel", 3),
> +};

Unfortunately bits 0 - 11 in VPP01 and bits 1 and 3 in VPP02 are marked
as reserved in our datasheet, so I can't check the validity of them.
Same goes for bits 16-22 in VPP02 which are only marked as SMI.

Same general comments as before also apply.


ChenYu

> +
> +static const struct mtk_clk_desc vpp0_desc = {
> +       .clks = vpp0_clks,
> +       .num_clks = ARRAY_SIZE(vpp0_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8195_vpp0[] = {
> +       {
> +               .compatible = "mediatek,mt8195-vppsys0",
> +               .data = &vpp0_desc,
> +       }, {
> +               /* sentinel */
> +       }
> +};
> +
> +static struct platform_driver clk_mt8195_vpp0_drv = {
> +       .probe = mtk_clk_simple_probe,
> +       .driver = {
> +               .name = "clk-mt8195-vpp0",
> +               .of_match_table = of_match_clk_mt8195_vpp0,
> +       },
> +};
> +
> +builtin_platform_driver(clk_mt8195_vpp0_drv);
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 19/22] clk: mediatek: Add MT8195 vppsys1 clock support
  2021-06-16 22:47 ` [PATCH 19/22] clk: mediatek: Add MT8195 vppsys1 " Chun-Jie Chen
@ 2021-07-09 10:45   ` Chen-Yu Tsai
  0 siblings, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-09 10:45 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

Hi,

On Thu, Jun 17, 2021 at 7:00 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 vppsys1 clock provider
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  drivers/clk/mediatek/Kconfig           |   6 ++
>  drivers/clk/mediatek/Makefile          |   1 +
>  drivers/clk/mediatek/clk-mt8195-vpp1.c | 110 +++++++++++++++++++++++++
>  3 files changed, 117 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt8195-vpp1.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 2deef026fbb4..91b1c19da1ab 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -672,6 +672,12 @@ config COMMON_CLK_MT8195_VPPSYS0
>         help
>           This driver supports MediaTek MT8195 vppsys0 clocks.
>
> +config COMMON_CLK_MT8195_VPPSYS1
> +       bool "Clock driver for MediaTek MT8195 vppsys1"
> +       depends on COMMON_CLK_MT8195
> +       help
> +         This driver supports MediaTek MT8195 vppsys1 clocks.
> +
>  config COMMON_CLK_MT8516
>         bool "Clock driver for MediaTek MT8516"
>         depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 34cd7f2c71ac..fbf57473bb91 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -95,5 +95,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS0) += clk-mt8195-vdo0.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS1) += clk-mt8195-vdo1.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS0) += clk-mt8195-vpp0.o
> +obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS1) += clk-mt8195-vpp1.o
>  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
>  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-vpp1.c b/drivers/clk/mediatek/clk-mt8195-vpp1.c
> new file mode 100644
> index 000000000000..0650ba86d5b6
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-vpp1.c
> @@ -0,0 +1,110 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +
> +static const struct mtk_gate_regs vpp10_cg_regs = {

Again, please add a separator.

> +       .set_ofs = 0x104,
> +       .clr_ofs = 0x108,
> +       .sta_ofs = 0x100,
> +};
> +
> +static const struct mtk_gate_regs vpp11_cg_regs = {
> +       .set_ofs = 0x114,
> +       .clr_ofs = 0x118,
> +       .sta_ofs = 0x110,
> +};
> +
> +#define GATE_VPP10(_id, _name, _parent, _shift)                        \
> +       GATE_MTK(_id, _name, _parent, &vpp10_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VPP11(_id, _name, _parent, _shift)                        \
> +       GATE_MTK(_id, _name, _parent, &vpp11_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate vpp1_clks[] = {
> +       /* VPP10 */
> +       GATE_VPP10(CLK_VPP1_SVPP1_MDP_OVL, "vpp1_svpp1_mdp_ovl", "vpp_sel", 0),
> +       GATE_VPP10(CLK_VPP1_SVPP1_MDP_TCC, "vpp1_svpp1_mdp_tcc", "vpp_sel", 1),
> +       GATE_VPP10(CLK_VPP1_SVPP1_MDP_WROT, "vpp1_svpp1_mdp_wrot", "vpp_sel", 2),
> +       GATE_VPP10(CLK_VPP1_SVPP1_VPP_PAD, "vpp1_svpp1_vpp_pad", "vpp_sel", 3),
> +       GATE_VPP10(CLK_VPP1_SVPP2_MDP_WROT, "vpp1_svpp2_mdp_wrot", "vpp_sel", 4),
> +       GATE_VPP10(CLK_VPP1_SVPP2_VPP_PAD, "vpp1_svpp2_vpp_pad", "vpp_sel", 5),
> +       GATE_VPP10(CLK_VPP1_SVPP3_MDP_WROT, "vpp1_svpp3_mdp_wrot", "vpp_sel", 6),
> +       GATE_VPP10(CLK_VPP1_SVPP3_VPP_PAD, "vpp1_svpp3_vpp_pad", "vpp_sel", 7),
> +       GATE_VPP10(CLK_VPP1_SVPP1_MDP_RDMA, "vpp1_svpp1_mdp_rdma", "vpp_sel", 8),
> +       GATE_VPP10(CLK_VPP1_SVPP1_MDP_FG, "vpp1_svpp1_mdp_fg", "vpp_sel", 9),
> +       GATE_VPP10(CLK_VPP1_SVPP2_MDP_RDMA, "vpp1_svpp2_mdp_rdma", "vpp_sel", 10),
> +       GATE_VPP10(CLK_VPP1_SVPP2_MDP_FG, "vpp1_svpp2_mdp_fg", "vpp_sel", 11),
> +       GATE_VPP10(CLK_VPP1_SVPP3_MDP_RDMA, "vpp1_svpp3_mdp_rdma", "vpp_sel", 12),
> +       GATE_VPP10(CLK_VPP1_SVPP3_MDP_FG, "vpp1_svpp3_mdp_fg", "vpp_sel", 13),
> +       GATE_VPP10(CLK_VPP1_VPP_SPLIT, "vpp1_vpp_split", "vpp_sel", 14),
> +       GATE_VPP10(CLK_VPP1_SVPP2_VDO0_DL_RELAY, "vpp1_svpp2_vdo0_dl_relay", "vpp_sel", 15),
> +       GATE_VPP10(CLK_VPP1_SVPP1_MDP_TDSHP, "vpp1_svpp1_mdp_tdshp", "vpp_sel", 16),
> +       GATE_VPP10(CLK_VPP1_SVPP1_MDP_COLOR, "vpp1_svpp1_mdp_color", "vpp_sel", 17),
> +       GATE_VPP10(CLK_VPP1_SVPP3_VDO1_DL_RELAY, "vpp1_svpp3_vdo1_dl_relay", "vpp_sel", 18),
> +       GATE_VPP10(CLK_VPP1_SVPP2_VPP_MERGE, "vpp1_svpp2_vpp_merge", "vpp_sel", 19),
> +       GATE_VPP10(CLK_VPP1_SVPP2_MDP_COLOR, "vpp1_svpp2_mdp_color", "vpp_sel", 20),
> +       GATE_VPP10(CLK_VPP1_VPPSYS1_GALS, "vpp1_vppsys1_gals", "vpp_sel", 21),
> +       GATE_VPP10(CLK_VPP1_SVPP3_VPP_MERGE, "vpp1_svpp3_vpp_merge", "vpp_sel", 22),
> +       GATE_VPP10(CLK_VPP1_SVPP3_MDP_COLOR, "vpp1_svpp3_mdp_color", "vpp_sel", 23),
> +       GATE_VPP10(CLK_VPP1_VPPSYS1_LARB, "vpp1_vppsys1_larb", "vpp_sel", 24),
> +       GATE_VPP10(CLK_VPP1_SVPP1_MDP_RSZ, "vpp1_svpp1_mdp_rsz", "vpp_sel", 25),
> +       GATE_VPP10(CLK_VPP1_SVPP1_MDP_HDR, "vpp1_svpp1_mdp_hdr", "vpp_sel", 26),
> +       GATE_VPP10(CLK_VPP1_SVPP1_MDP_AAL, "vpp1_svpp1_mdp_aal", "vpp_sel", 27),
> +       GATE_VPP10(CLK_VPP1_SVPP2_MDP_HDR, "vpp1_svpp2_mdp_hdr", "vpp_sel", 28),
> +       GATE_VPP10(CLK_VPP1_SVPP2_MDP_AAL, "vpp1_svpp2_mdp_aal", "vpp_sel", 29),
> +       GATE_VPP10(CLK_VPP1_DL_ASYNC, "vpp1_dl_async", "vpp_sel", 30),
> +       GATE_VPP10(CLK_VPP1_LARB5_FAKE_ENG, "vpp1_larb5_fake_eng", "vpp_sel", 31),
> +       /* VPP11 */
> +       GATE_VPP11(CLK_VPP1_SVPP3_MDP_HDR, "vpp1_svpp3_mdp_hdr", "vpp_sel", 0),
> +       GATE_VPP11(CLK_VPP1_SVPP3_MDP_AAL, "vpp1_svpp3_mdp_aal", "vpp_sel", 1),
> +       GATE_VPP11(CLK_VPP1_SVPP2_VDO1_DL_RELAY, "vpp1_svpp2_vdo1_dl_relay", "vpp_sel", 2),
> +       GATE_VPP11(CLK_VPP1_LARB6_FAKE_ENG, "vpp1_larb6_fake_eng", "vpp_sel", 3),
> +       GATE_VPP11(CLK_VPP1_SVPP2_MDP_RSZ, "vpp1_svpp2_mdp_rsz", "vpp_sel", 4),
> +       GATE_VPP11(CLK_VPP1_SVPP3_MDP_RSZ, "vpp1_svpp3_mdp_rsz", "vpp_sel", 5),
> +       GATE_VPP11(CLK_VPP1_SVPP3_VDO0_DL_RELAY, "vpp1_svpp3_vdo0_dl_relay", "vpp_sel", 6),
> +       GATE_VPP11(CLK_VPP1_DISP_MUTEX, "vpp1_disp_mutex", "vpp_sel", 7),
> +       GATE_VPP11(CLK_VPP1_SVPP2_MDP_TDSHP, "vpp1_svpp2_mdp_tdshp", "vpp_sel", 8),
> +       GATE_VPP11(CLK_VPP1_SVPP3_MDP_TDSHP, "vpp1_svpp3_mdp_tdshp", "vpp_sel", 9),
> +       GATE_VPP11(CLK_VPP1_VPP0_DL1_RELAY, "vpp1_vpp0_dl1_relay", "vpp_sel", 10),
> +       GATE_VPP11(CLK_VPP1_HDMI_META, "vpp1_hdmi_meta", "hdmirx_p", 11),
> +       GATE_VPP11(CLK_VPP1_VPP_SPLIT_HDMI, "vpp1_vpp_split_hdmi", "hdmirx_p", 12),
> +       GATE_VPP11(CLK_VPP1_DGI_IN, "vpp1_dgi_in", "in_dgi", 13),
> +       GATE_VPP11(CLK_VPP1_DGI_OUT, "vpp1_dgi_out", "dgi_out_sel", 14),
> +       GATE_VPP11(CLK_VPP1_VPP_SPLIT_DGI, "vpp1_vpp_split_dgi", "dgi_out_sel", 15),
> +       GATE_VPP11(CLK_VPP1_VPP0_DL_ASYNC, "vpp1_vpp0_dl_async", "vpp_sel", 16),
> +       GATE_VPP11(CLK_VPP1_VPP0_DL_RELAY, "vpp1_vpp0_dl_relay", "vpp_sel", 17),
> +       GATE_VPP11(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m", "clk26m", 26),

The last two aren't in the datasheet.

Same general comments apply.


ChenYu

> +};
> +
> +static const struct mtk_clk_desc vpp1_desc = {
> +       .clks = vpp1_clks,
> +       .num_clks = ARRAY_SIZE(vpp1_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8195_vpp1[] = {
> +       {
> +               .compatible = "mediatek,mt8195-vppsys1",
> +               .data = &vpp1_desc,
> +       }, {
> +               /* sentinel */
> +       }
> +};
> +
> +static struct platform_driver clk_mt8195_vpp1_drv = {
> +       .probe = mtk_clk_simple_probe,
> +       .driver = {
> +               .name = "clk-mt8195-vpp1",
> +               .of_match_table = of_match_clk_mt8195_vpp1,
> +       },
> +};
> +
> +builtin_platform_driver(clk_mt8195_vpp1_drv);
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 05/22] clk: mediatek: Add MT8195 audio clock support
  2021-07-05  9:03   ` Chen-Yu Tsai
@ 2021-07-12  1:26     ` Chun-Jie Chen
  2021-07-12  2:09       ` Chen-Yu Tsai
  0 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-07-12  1:26 UTC (permalink / raw)
  To: Chen-Yu Tsai, Trevor Wu
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group

On Mon, 2021-07-05 at 17:03 +0800, Chen-Yu Tsai wrote:
> Hi,
> 
> On Thu, Jun 17, 2021 at 06:47:26AM +0800, Chun-Jie Chen wrote:
> > Add MT8195 audio clock provider
> > 
> > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > ---
> >  drivers/clk/mediatek/Kconfig          |   6 +
> >  drivers/clk/mediatek/Makefile         |   1 +
> >  drivers/clk/mediatek/clk-mt8195-aud.c | 198
> > ++++++++++++++++++++++++++
> >  3 files changed, 205 insertions(+)
> >  create mode 100644 drivers/clk/mediatek/clk-mt8195-aud.c
> > 
> > diff --git a/drivers/clk/mediatek/Kconfig
> > b/drivers/clk/mediatek/Kconfig
> > index 6707aba3d500..e2bae9d490a4 100644
> > --- a/drivers/clk/mediatek/Kconfig
> > +++ b/drivers/clk/mediatek/Kconfig
> > @@ -588,6 +588,12 @@ config COMMON_CLK_MT8195
> >  	help
> >  	  This driver supports MediaTek MT8195 basic clocks.
> >  
> > +config COMMON_CLK_MT8195_AUDSYS
> > +	bool "Clock driver for MediaTek MT8195 audsys"
> > +	depends on COMMON_CLK_MT8195
> > +	help
> > +	  This driver supports MediaTek MT8195 audsys clocks.
> > +
> 
> The clock modules aren't shared between different chips, so either we
> enable support for all clock hardware in one chip or we don't. It
> doesn't make sense to support just some of them. So having just one
> Kconfig option and having all drivers under it is better.
> 
> >  config COMMON_CLK_MT8516
> >  	bool "Clock driver for MediaTek MT8516"
> >  	depends on ARCH_MEDIATEK || COMPILE_TEST
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index f8002d8966e1..f27c04314186 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -81,5 +81,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-
> > mt8192-scp_adsp.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
> >  obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195.o
> > +obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS) += clk-mt8195-aud.o
> >  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
> >  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> > diff --git a/drivers/clk/mediatek/clk-mt8195-aud.c
> > b/drivers/clk/mediatek/clk-mt8195-aud.c
> > new file mode 100644
> > index 000000000000..db5f80d41de0
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8195-aud.c
> > @@ -0,0 +1,198 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2021 MediaTek Inc.
> > +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> > +
> > +#include <dt-bindings/clock/mt8195-clk.h>
> > +
> > +static const struct mtk_gate_regs aud0_cg_regs = {
> > +	.set_ofs = 0x0,
> > +	.clr_ofs = 0x0,
> > +	.sta_ofs = 0x0,
> > +};
> > +
> > +static const struct mtk_gate_regs aud1_cg_regs = {
> > +	.set_ofs = 0x10,
> > +	.clr_ofs = 0x10,
> > +	.sta_ofs = 0x10,
> > +};
> > +
> > +static const struct mtk_gate_regs aud2_cg_regs = {
> > +	.set_ofs = 0x14,
> > +	.clr_ofs = 0x14,
> > +	.sta_ofs = 0x14,
> > +};
> > +
> > +static const struct mtk_gate_regs aud3_cg_regs = {
> > +	.set_ofs = 0x18,
> > +	.clr_ofs = 0x18,
> > +	.sta_ofs = 0x18,
> > +};
> > +
> > +static const struct mtk_gate_regs aud4_cg_regs = {
> > +	.set_ofs = 0x4,
> > +	.clr_ofs = 0x4,
> > +	.sta_ofs = 0x4,
> > +};
> > +
> > +static const struct mtk_gate_regs aud5_cg_regs = {
> > +	.set_ofs = 0xc,
> > +	.clr_ofs = 0xc,
> > +	.sta_ofs = 0xc,
> > +};
> > +
> > +#define GATE_AUD0(_id, _name, _parent, _shift)			
> > \
> > +	GATE_MTK(_id, _name, _parent, &aud0_cg_regs, _shift,
> > &mtk_clk_gate_ops_no_setclr)
> > +
> > +#define GATE_AUD1(_id, _name, _parent, _shift)			
> > \
> > +	GATE_MTK(_id, _name, _parent, &aud1_cg_regs, _shift,
> > &mtk_clk_gate_ops_no_setclr)
> > +
> > +#define GATE_AUD2(_id, _name, _parent, _shift)			
> > \
> > +	GATE_MTK(_id, _name, _parent, &aud2_cg_regs, _shift,
> > &mtk_clk_gate_ops_no_setclr)
> > +
> > +#define GATE_AUD3(_id, _name, _parent, _shift)			
> > \
> > +	GATE_MTK(_id, _name, _parent, &aud3_cg_regs, _shift,
> > &mtk_clk_gate_ops_no_setclr)
> > +
> > +#define GATE_AUD4(_id, _name, _parent, _shift)			
> > \
> > +	GATE_MTK(_id, _name, _parent, &aud4_cg_regs, _shift,
> > &mtk_clk_gate_ops_no_setclr)
> > +
> > +#define GATE_AUD5(_id, _name, _parent, _shift)			
> > \
> > +	GATE_MTK(_id, _name, _parent, &aud5_cg_regs, _shift,
> > &mtk_clk_gate_ops_no_setclr)
> > +
> > +static const struct mtk_gate aud_clks[] = {
> > +	/* AUD0 */
> > +	GATE_AUD0(CLK_AUD_AFE, "aud_afe", "a1sys_hp_sel", 2),
> > +	GATE_AUD0(CLK_AUD_LRCK_CNT, "aud_lrck_cnt", "a1sys_hp_sel", 4),
> > +	GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_APLL, "aud_spdifin_tuner_apll",
> > "apll4_sel", 10),
> > +	GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_DBG, "aud_spdifin_tuner_dbg",
> > "apll4_sel", 11),
> > +	GATE_AUD0(CLK_AUD_UL_TML, "aud_ul_tml", "a1sys_hp_sel", 18),
> > +	GATE_AUD0(CLK_AUD_APLL1_TUNER, "aud_apll1_tuner", "apll1_sel",
> > 19),
> > +	GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "apll2_sel",
> > 20),
> > +	GATE_AUD0(CLK_AUD_TOP0_SPDF, "aud_top0_spdf", "aud_iec_sel",
> > 21),
> > +	GATE_AUD0(CLK_AUD_APLL, "aud_apll", "apll1_sel", 23),
> > +	GATE_AUD0(CLK_AUD_APLL2, "aud_apll2", "apll2_sel", 24),
> > +	GATE_AUD0(CLK_AUD_DAC, "aud_dac", "a1sys_hp_sel", 25),
> > +	GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "a1sys_hp_sel",
> > 26),
> > +	GATE_AUD0(CLK_AUD_TML, "aud_tml", "a1sys_hp_sel", 27),
> > +	GATE_AUD0(CLK_AUD_ADC, "aud_adc", "a1sys_hp_sel", 28),
> > +	GATE_AUD0(CLK_AUD_DAC_HIRES, "aud_dac_hires", "audio_h_sel",
> > 31),
> > +	/* AUD1 */
> > +	GATE_AUD1(CLK_AUD_I2SIN, "aud_i2sin", "a1sys_hp_sel", 0),
> > +	GATE_AUD1(CLK_AUD_TDM_IN, "aud_tdm_in", "a1sys_hp_sel", 1),
> > +	GATE_AUD1(CLK_AUD_I2S_OUT, "aud_i2s_out", "a1sys_hp_sel", 6),
> > +	GATE_AUD1(CLK_AUD_TDM_OUT, "aud_tdm_out", "a1sys_hp_sel", 7),
> > +	GATE_AUD1(CLK_AUD_HDMI_OUT, "aud_hdmi_out", "a1sys_hp_sel", 8),
> > +	GATE_AUD1(CLK_AUD_ASRC11, "aud_asrc11", "a1sys_hp_sel", 16),
> > +	GATE_AUD1(CLK_AUD_ASRC12, "aud_asrc12", "a1sys_hp_sel", 17),
> > +	GATE_AUD1(CLK_AUD_MULTI_IN, "aud_multi_in", "mphone_slave_b",
> > 19),
> > +	GATE_AUD1(CLK_AUD_INTDIR, "aud_intdir", "intdir_sel", 20),
> > +	GATE_AUD1(CLK_AUD_A1SYS, "aud_a1sys", "a1sys_hp_sel", 21),
> > +	GATE_AUD1(CLK_AUD_A2SYS, "aud_a2sys", "a2sys_sel", 22),
> > +	GATE_AUD1(CLK_AUD_PCMIF, "aud_pcmif", "a1sys_hp_sel", 24),
> > +	GATE_AUD1(CLK_AUD_A3SYS, "aud_a3sys", "a3sys_sel", 30),
> > +	GATE_AUD1(CLK_AUD_A4SYS, "aud_a4sys", "a4sys_sel", 31),
> > +	/* AUD2 */
> > +	GATE_AUD2(CLK_AUD_MEMIF_UL1, "aud_memif_ul1", "a1sys_hp_sel",
> > 0),
> > +	GATE_AUD2(CLK_AUD_MEMIF_UL2, "aud_memif_ul2", "a1sys_hp_sel",
> > 1),
> > +	GATE_AUD2(CLK_AUD_MEMIF_UL3, "aud_memif_ul3", "a1sys_hp_sel",
> > 2),
> > +	GATE_AUD2(CLK_AUD_MEMIF_UL4, "aud_memif_ul4", "a1sys_hp_sel",
> > 3),
> > +	GATE_AUD2(CLK_AUD_MEMIF_UL5, "aud_memif_ul5", "a1sys_hp_sel",
> > 4),
> > +	GATE_AUD2(CLK_AUD_MEMIF_UL6, "aud_memif_ul6", "a1sys_hp_sel",
> > 5),
> > +	GATE_AUD2(CLK_AUD_MEMIF_UL8, "aud_memif_ul8", "a1sys_hp_sel",
> > 7),
> > +	GATE_AUD2(CLK_AUD_MEMIF_UL9, "aud_memif_ul9", "a1sys_hp_sel",
> > 8),
> > +	GATE_AUD2(CLK_AUD_MEMIF_UL10, "aud_memif_ul10", "a1sys_hp_sel",
> > 9),
> > +	GATE_AUD2(CLK_AUD_MEMIF_DL2, "aud_memif_dl2", "a1sys_hp_sel",
> > 18),
> > +	GATE_AUD2(CLK_AUD_MEMIF_DL3, "aud_memif_dl3", "a1sys_hp_sel",
> > 19),
> > +	GATE_AUD2(CLK_AUD_MEMIF_DL6, "aud_memif_dl6", "a1sys_hp_sel",
> > 22),
> > +	GATE_AUD2(CLK_AUD_MEMIF_DL7, "aud_memif_dl7", "a1sys_hp_sel",
> > 23),
> > +	GATE_AUD2(CLK_AUD_MEMIF_DL8, "aud_memif_dl8", "a1sys_hp_sel",
> > 24),
> > +	GATE_AUD2(CLK_AUD_MEMIF_DL10, "aud_memif_dl10", "a1sys_hp_sel",
> > 26),
> > +	GATE_AUD2(CLK_AUD_MEMIF_DL11, "aud_memif_dl11", "a1sys_hp_sel",
> > 27),
> > +	/* AUD3 */
> > +	GATE_AUD3(CLK_AUD_GASRC0, "aud_gasrc0", "asm_h_sel", 0),
> > +	GATE_AUD3(CLK_AUD_GASRC1, "aud_gasrc1", "asm_h_sel", 1),
> > +	GATE_AUD3(CLK_AUD_GASRC2, "aud_gasrc2", "asm_h_sel", 2),
> > +	GATE_AUD3(CLK_AUD_GASRC3, "aud_gasrc3", "asm_h_sel", 3),
> > +	GATE_AUD3(CLK_AUD_GASRC4, "aud_gasrc4", "asm_h_sel", 4),
> > +	GATE_AUD3(CLK_AUD_GASRC5, "aud_gasrc5", "asm_h_sel", 5),
> > +	GATE_AUD3(CLK_AUD_GASRC6, "aud_gasrc6", "asm_h_sel", 6),
> > +	GATE_AUD3(CLK_AUD_GASRC7, "aud_gasrc7", "asm_h_sel", 7),
> > +	GATE_AUD3(CLK_AUD_GASRC8, "aud_gasrc8", "asm_h_sel", 8),
> > +	GATE_AUD3(CLK_AUD_GASRC9, "aud_gasrc9", "asm_h_sel", 9),
> > +	GATE_AUD3(CLK_AUD_GASRC10, "aud_gasrc10", "asm_h_sel", 10),
> > +	GATE_AUD3(CLK_AUD_GASRC11, "aud_gasrc11", "asm_h_sel", 11),
> > +	GATE_AUD3(CLK_AUD_GASRC12, "aud_gasrc12", "asm_h_sel", 12),
> > +	GATE_AUD3(CLK_AUD_GASRC13, "aud_gasrc13", "asm_h_sel", 13),
> > +	GATE_AUD3(CLK_AUD_GASRC14, "aud_gasrc14", "asm_h_sel", 14),
> > +	GATE_AUD3(CLK_AUD_GASRC15, "aud_gasrc15", "asm_h_sel", 15),
> > +	GATE_AUD3(CLK_AUD_GASRC16, "aud_gasrc16", "asm_h_sel", 16),
> > +	GATE_AUD3(CLK_AUD_GASRC17, "aud_gasrc17", "asm_h_sel", 17),
> > +	GATE_AUD3(CLK_AUD_GASRC18, "aud_gasrc18", "asm_h_sel", 18),
> > +	GATE_AUD3(CLK_AUD_GASRC19, "aud_gasrc19", "asm_h_sel", 19),
> > +	/* AUD4 */
> > +	GATE_AUD4(CLK_AUD_A1SYS_HP, "aud_a1sys_hp", "a1sys_hp_sel", 2),
> > +	GATE_AUD4(CLK_AUD_AFE_DMIC1, "aud_afe_dmic1", "a1sys_hp_sel",
> > 10),
> > +	GATE_AUD4(CLK_AUD_AFE_DMIC2, "aud_afe_dmic2", "a1sys_hp_sel",
> > 11),
> > +	GATE_AUD4(CLK_AUD_AFE_DMIC3, "aud_afe_dmic3", "a1sys_hp_sel",
> > 12),
> > +	GATE_AUD4(CLK_AUD_AFE_DMIC4, "aud_afe_dmic4", "a1sys_hp_sel",
> > 13),
> > +	GATE_AUD4(CLK_AUD_AFE_26M_DMIC_TM, "aud_afe_26m_dmic_tm",
> > "a1sys_hp_sel", 14),
> > +	GATE_AUD4(CLK_AUD_UL_TML_HIRES, "aud_ul_tml_hires",
> > "audio_h_sel", 16),
> > +	GATE_AUD4(CLK_AUD_ADC_HIRES, "aud_adc_hires", "audio_h_sel",
> > 17),
> > +	GATE_AUD4(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "a1sys_hp_sel",
> > 18),
> > +	GATE_AUD4(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires",
> > "audio_h_sel", 19),
> > +	/* AUD5 */
> > +	GATE_AUD5(CLK_AUD_LINEIN_TUNER, "aud_linein_tuner",
> > "apll5_sel", 5),
> > +	GATE_AUD5(CLK_AUD_EARC_TUNER, "aud_earc_tuner", "apll3_sel",
> > 7),
> > +};
> 
> These are all clock gates, and are all internal to the audio
> hardware,
> i.e. not used by other drivers or modules.
> 
> So these don't actually need to be in a separate clk driver. They can
> be
> modelled within ASoC as supplies that are automatically managed by
> ASoC
> core. Otherwise just have them as bits that are toggled by the audio
> driver's start/stop sequencing code, like they are now, but through
> vastly more complicated plumbing.
> 
> Please work with the audio driver owner to see if this can be moved
> into
> the audio driver.
> 
> Regards
> ChenYu
> 

The afe device will be the child of audsys clock provider node and
audsys clock driver will use devm_of_platform_populate() to populate
afe device when audsys clock gates are registered successfully,
It means afe will be toggled by audsys clock, do you suggest to change
the toggled order?

Best Regards,
Chun-Jie

> > +
> > +static int clk_mt8195_aud_probe(struct platform_device *pdev)
> > +{
> > +	struct clk_onecell_data *clk_data;
> > +	struct device_node *node = pdev->dev.of_node;
> > +	int r;
> > +
> > +	clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
> > +	if (!clk_data)
> > +		return -ENOMEM;
> > +
> > +	r = mtk_clk_register_gates(node, aud_clks,
> > ARRAY_SIZE(aud_clks), clk_data);
> > +	if (r)
> > +		return r;
> > +
> > +	r = of_clk_add_provider(node, of_clk_src_onecell_get,
> > clk_data);
> > +	if (r)
> > +		goto err_clk_provider;
> > +
> > +	r = devm_of_platform_populate(&pdev->dev);
> > +	if (r)
> > +		goto err_plat_populate;
> > +
> > +	return 0;
> > +
> > +err_plat_populate:
> > +	of_clk_del_provider(node);
> > +err_clk_provider:
> > +	return r;
> > +}
> > +
> > +static const struct of_device_id of_match_clk_mt8195_aud[] = {
> > +	{ .compatible = "mediatek,mt8195-audsys", },
> > +	{}
> > +};
> > +
> > +static struct platform_driver clk_mt8195_aud_drv = {
> > +	.probe = clk_mt8195_aud_probe,
> > +	.driver = {
> > +		.name = "clk-mt8195-aud",
> > +		.of_match_table = of_match_clk_mt8195_aud,
> > +	},
> > +};
> > +
> > +builtin_platform_driver(clk_mt8195_aud_drv);
> > -- 
> > 2.18.0
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 14/22] clk: mediatek: Add MT8195 vdecsys clock support
  2021-07-09  8:40   ` Chen-Yu Tsai
@ 2021-07-12  1:34     ` Chun-Jie Chen
  0 siblings, 0 replies; 59+ messages in thread
From: Chun-Jie Chen @ 2021-07-12  1:34 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

On Fri, 2021-07-09 at 16:40 +0800, Chen-Yu Tsai wrote:
> On Thu, Jun 17, 2021 at 7:02 AM Chun-Jie Chen
> <chun-jie.chen@mediatek.com> wrote:
> > 
> > Add MT8195 vdecsys clock providers
> > 
> > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > ---
> >  drivers/clk/mediatek/Kconfig           |   6 ++
> >  drivers/clk/mediatek/Makefile          |   1 +
> >  drivers/clk/mediatek/clk-mt8195-vdec.c | 106
> > +++++++++++++++++++++++++
> >  3 files changed, 113 insertions(+)
> >  create mode 100644 drivers/clk/mediatek/clk-mt8195-vdec.c
> > 
> > diff --git a/drivers/clk/mediatek/Kconfig
> > b/drivers/clk/mediatek/Kconfig
> > index d34517728f4a..b7881b8ebb23 100644
> > --- a/drivers/clk/mediatek/Kconfig
> > +++ b/drivers/clk/mediatek/Kconfig
> > @@ -642,6 +642,12 @@ config COMMON_CLK_MT8195_NNASYS
> >         help
> >           This driver supports MediaTek MT8195 nnasys clocks.
> > 
> > +config COMMON_CLK_MT8195_VDECSYS
> > +       bool "Clock driver for MediaTek MT8195 vdecsys"
> > +       depends on COMMON_CLK_MT8195
> > +       help
> > +         This driver supports MediaTek MT8195 vdecsys clocks.
> > +
> 
> Same comments about the commit log and Kconfig option.
> 
> >  config COMMON_CLK_MT8516
> >         bool "Clock driver for MediaTek MT8516"
> >         depends on ARCH_MEDIATEK || COMPILE_TEST
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index 49e585a7ac8e..9acfa705f1de 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -90,5 +90,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_IPESYS) += clk-
> > mt8195-ipe.o
> >  obj-$(CONFIG_COMMON_CLK_MT8195_MFGCFG) += clk-mt8195-mfg.o
> >  obj-$(CONFIG_COMMON_CLK_MT8195_SCP_ADSP) += clk-mt8195-scp_adsp.o
> >  obj-$(CONFIG_COMMON_CLK_MT8195_NNASYS) += clk-mt8195-nna.o
> > +obj-$(CONFIG_COMMON_CLK_MT8195_VDECSYS) += clk-mt8195-vdec.o
> >  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
> >  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> > diff --git a/drivers/clk/mediatek/clk-mt8195-vdec.c
> > b/drivers/clk/mediatek/clk-mt8195-vdec.c
> > new file mode 100644
> > index 000000000000..9ab84e75e1a0
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8195-vdec.c
> > @@ -0,0 +1,106 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2021 MediaTek Inc.
> > +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> 
> Please order alphabetically. I think this applies to all the other
> patches.
> I missed this in the earlier ones, but please fix them nonetheless.
> 

I will check it in all patches of this series, thanks for you comment.

Best Regards,
Chun-Jie

> > +
> > +#include <dt-bindings/clock/mt8195-clk.h>
> > +
> > +static const struct mtk_gate_regs vdec0_cg_regs = {
> > +       .set_ofs = 0x0,
> > +       .clr_ofs = 0x4,
> > +       .sta_ofs = 0x0,
> > +};
> > +
> > +static const struct mtk_gate_regs vdec1_cg_regs = {
> > +       .set_ofs = 0x200,
> > +       .clr_ofs = 0x204,
> > +       .sta_ofs = 0x200,
> > +};
> > +
> > +static const struct mtk_gate_regs vdec2_cg_regs = {
> > +       .set_ofs = 0x8,
> > +       .clr_ofs = 0xc,
> > +       .sta_ofs = 0x8,
> > +};
> > +
> > +#define GATE_VDEC0(_id, _name, _parent,
> > _shift)                        \
> > +       GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr_inv)
> > +
> > +#define GATE_VDEC1(_id, _name, _parent,
> > _shift)                        \
> > +       GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr_inv)
> > +
> > +#define GATE_VDEC2(_id, _name, _parent,
> > _shift)                        \
> > +       GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr_inv)
> > +
> > +static const struct mtk_gate vdec_clks[] = {
> > +       /* VDEC0 */
> > +       GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec", "vdec_sel", 0),
> > +       /* VDEC1 */
> > +       GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat", "vdec_sel", 0),
> > +       /* VDEC2 */
> > +       GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1", "vdec_sel", 0),
> > +};
> > +
> > +static const struct mtk_gate vdec_core1_clks[] = {
> > +       /* VDEC0 */
> > +       GATE_VDEC0(CLK_VDEC_CORE1_VDEC, "vdec_core1_vdec",
> > "vdec_sel", 0),
> > +       /* VDEC1 */
> > +       GATE_VDEC1(CLK_VDEC_CORE1_LAT, "vdec_core1_lat",
> > "vdec_sel", 0),
> > +       /* VDEC2 */
> > +       GATE_VDEC2(CLK_VDEC_CORE1_LARB1, "vdec_core1_larb1",
> > "vdec_sel", 0),
> > +};
> > +
> > +static const struct mtk_gate vdec_soc_clks[] = {
> > +       /* VDEC0 */
> > +       GATE_VDEC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec", "vdec_sel",
> > 0),
> > +       /* VDEC1 */
> > +       GATE_VDEC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat", "vdec_sel",
> > 0),
> > +       /* VDEC2 */
> > +       GATE_VDEC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1",
> > "vdec_sel", 0),
> > +};
> > +
> > +static const struct mtk_clk_desc vdec_desc = {
> > +       .clks = vdec_clks,
> > +       .num_clks = ARRAY_SIZE(vdec_clks),
> > +};
> > +
> > +static const struct mtk_clk_desc vdec_core1_desc = {
> > +       .clks = vdec_core1_clks,
> > +       .num_clks = ARRAY_SIZE(vdec_core1_clks),
> > +};
> > +
> > +static const struct mtk_clk_desc vdec_soc_desc = {
> > +       .clks = vdec_soc_clks,
> > +       .num_clks = ARRAY_SIZE(vdec_soc_clks),
> > +};
> > +
> > +static const struct of_device_id of_match_clk_mt8195_vdec[] = {
> > +       {
> > +               .compatible = "mediatek,mt8195-vdecsys",
> > +               .data = &vdec_desc,
> > +       }, {
> > +               .compatible = "mediatek,mt8195-vdecsys_core1",
> > +               .data = &vdec_core1_desc,
> > +       }, {
> > +               .compatible = "mediatek,mt8195-vdecsys_soc",
> > +               .data = &vdec_soc_desc,
> > +       }, {
> > +               /* sentinel */
> > +       }
> > +};
> > +
> > +static struct platform_driver clk_mt8195_vdec_drv = {
> > +       .probe = mtk_clk_simple_probe,
> > +       .driver = {
> > +               .name = "clk-mt8195-vdec",
> > +               .of_match_table = of_match_clk_mt8195_vdec,
> > +       },
> > +};
> > +
> 
> Nit: you could drop the empty line here. Same in the other patches.
> 
> ChenYu
> 

I will check it in all patches of this series, thanks for you comment.

Best Regards,
Chun-Jie

> 
> > +builtin_platform_driver(clk_mt8195_vdec_drv);
> > --
> > 2.18.0
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > 
https://urldefense.com/v3/__http://lists.infradead.org/mailman/listinfo/linux-mediatek__;!!CTRNKA9wMg0ARbw!29GLBpjACRCpc5FxaHdrGgafZTaEALh8IjHiOrQ9T_GuJJzdOlwhLRehPS8v5ciHUo9W$
> >  

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 05/22] clk: mediatek: Add MT8195 audio clock support
  2021-07-12  1:26     ` Chun-Jie Chen
@ 2021-07-12  2:09       ` Chen-Yu Tsai
  2021-07-12  4:35         ` Chun-Jie Chen
  0 siblings, 1 reply; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-12  2:09 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Trevor Wu, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
	Rob Herring, linux-arm-kernel, linux-kernel, linux-mediatek,
	linux-clk, devicetree, srv_heupstream,
	Project_Global_Chrome_Upstream_Group

Hi,

On Mon, Jul 12, 2021 at 9:26 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> On Mon, 2021-07-05 at 17:03 +0800, Chen-Yu Tsai wrote:
> > Hi,
> >
> > On Thu, Jun 17, 2021 at 06:47:26AM +0800, Chun-Jie Chen wrote:
> > > Add MT8195 audio clock provider
> > >
> > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > > ---
> > >  drivers/clk/mediatek/Kconfig          |   6 +
> > >  drivers/clk/mediatek/Makefile         |   1 +
> > >  drivers/clk/mediatek/clk-mt8195-aud.c | 198
> > > ++++++++++++++++++++++++++
> > >  3 files changed, 205 insertions(+)
> > >  create mode 100644 drivers/clk/mediatek/clk-mt8195-aud.c
> > >
> > > diff --git a/drivers/clk/mediatek/Kconfig
> > > b/drivers/clk/mediatek/Kconfig
> > > index 6707aba3d500..e2bae9d490a4 100644
> > > --- a/drivers/clk/mediatek/Kconfig
> > > +++ b/drivers/clk/mediatek/Kconfig
> > > @@ -588,6 +588,12 @@ config COMMON_CLK_MT8195
> > >     help
> > >       This driver supports MediaTek MT8195 basic clocks.
> > >
> > > +config COMMON_CLK_MT8195_AUDSYS
> > > +   bool "Clock driver for MediaTek MT8195 audsys"
> > > +   depends on COMMON_CLK_MT8195
> > > +   help
> > > +     This driver supports MediaTek MT8195 audsys clocks.
> > > +
> >
> > The clock modules aren't shared between different chips, so either we
> > enable support for all clock hardware in one chip or we don't. It
> > doesn't make sense to support just some of them. So having just one
> > Kconfig option and having all drivers under it is better.
> >
> > >  config COMMON_CLK_MT8516
> > >     bool "Clock driver for MediaTek MT8516"
> > >     depends on ARCH_MEDIATEK || COMPILE_TEST
> > > diff --git a/drivers/clk/mediatek/Makefile
> > > b/drivers/clk/mediatek/Makefile
> > > index f8002d8966e1..f27c04314186 100644
> > > --- a/drivers/clk/mediatek/Makefile
> > > +++ b/drivers/clk/mediatek/Makefile
> > > @@ -81,5 +81,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-
> > > mt8192-scp_adsp.o
> > >  obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
> > >  obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
> > >  obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195.o
> > > +obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS) += clk-mt8195-aud.o
> > >  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
> > >  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> > > diff --git a/drivers/clk/mediatek/clk-mt8195-aud.c
> > > b/drivers/clk/mediatek/clk-mt8195-aud.c
> > > new file mode 100644
> > > index 000000000000..db5f80d41de0
> > > --- /dev/null
> > > +++ b/drivers/clk/mediatek/clk-mt8195-aud.c
> > > @@ -0,0 +1,198 @@
> > > +// SPDX-License-Identifier: GPL-2.0-only
> > > +//
> > > +// Copyright (c) 2021 MediaTek Inc.
> > > +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > > +
> > > +#include <linux/clk-provider.h>
> > > +#include <linux/of_platform.h>
> > > +#include <linux/platform_device.h>
> > > +
> > > +#include "clk-mtk.h"
> > > +#include "clk-gate.h"
> > > +
> > > +#include <dt-bindings/clock/mt8195-clk.h>
> > > +
> > > +static const struct mtk_gate_regs aud0_cg_regs = {
> > > +   .set_ofs = 0x0,
> > > +   .clr_ofs = 0x0,
> > > +   .sta_ofs = 0x0,
> > > +};
> > > +
> > > +static const struct mtk_gate_regs aud1_cg_regs = {
> > > +   .set_ofs = 0x10,
> > > +   .clr_ofs = 0x10,
> > > +   .sta_ofs = 0x10,
> > > +};
> > > +
> > > +static const struct mtk_gate_regs aud2_cg_regs = {
> > > +   .set_ofs = 0x14,
> > > +   .clr_ofs = 0x14,
> > > +   .sta_ofs = 0x14,
> > > +};
> > > +
> > > +static const struct mtk_gate_regs aud3_cg_regs = {
> > > +   .set_ofs = 0x18,
> > > +   .clr_ofs = 0x18,
> > > +   .sta_ofs = 0x18,
> > > +};
> > > +
> > > +static const struct mtk_gate_regs aud4_cg_regs = {
> > > +   .set_ofs = 0x4,
> > > +   .clr_ofs = 0x4,
> > > +   .sta_ofs = 0x4,
> > > +};
> > > +
> > > +static const struct mtk_gate_regs aud5_cg_regs = {
> > > +   .set_ofs = 0xc,
> > > +   .clr_ofs = 0xc,
> > > +   .sta_ofs = 0xc,
> > > +};
> > > +
> > > +#define GATE_AUD0(_id, _name, _parent, _shift)
> > > \
> > > +   GATE_MTK(_id, _name, _parent, &aud0_cg_regs, _shift,
> > > &mtk_clk_gate_ops_no_setclr)
> > > +
> > > +#define GATE_AUD1(_id, _name, _parent, _shift)
> > > \
> > > +   GATE_MTK(_id, _name, _parent, &aud1_cg_regs, _shift,
> > > &mtk_clk_gate_ops_no_setclr)
> > > +
> > > +#define GATE_AUD2(_id, _name, _parent, _shift)
> > > \
> > > +   GATE_MTK(_id, _name, _parent, &aud2_cg_regs, _shift,
> > > &mtk_clk_gate_ops_no_setclr)
> > > +
> > > +#define GATE_AUD3(_id, _name, _parent, _shift)
> > > \
> > > +   GATE_MTK(_id, _name, _parent, &aud3_cg_regs, _shift,
> > > &mtk_clk_gate_ops_no_setclr)
> > > +
> > > +#define GATE_AUD4(_id, _name, _parent, _shift)
> > > \
> > > +   GATE_MTK(_id, _name, _parent, &aud4_cg_regs, _shift,
> > > &mtk_clk_gate_ops_no_setclr)
> > > +
> > > +#define GATE_AUD5(_id, _name, _parent, _shift)
> > > \
> > > +   GATE_MTK(_id, _name, _parent, &aud5_cg_regs, _shift,
> > > &mtk_clk_gate_ops_no_setclr)
> > > +
> > > +static const struct mtk_gate aud_clks[] = {
> > > +   /* AUD0 */
> > > +   GATE_AUD0(CLK_AUD_AFE, "aud_afe", "a1sys_hp_sel", 2),
> > > +   GATE_AUD0(CLK_AUD_LRCK_CNT, "aud_lrck_cnt", "a1sys_hp_sel", 4),
> > > +   GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_APLL, "aud_spdifin_tuner_apll",
> > > "apll4_sel", 10),
> > > +   GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_DBG, "aud_spdifin_tuner_dbg",
> > > "apll4_sel", 11),
> > > +   GATE_AUD0(CLK_AUD_UL_TML, "aud_ul_tml", "a1sys_hp_sel", 18),
> > > +   GATE_AUD0(CLK_AUD_APLL1_TUNER, "aud_apll1_tuner", "apll1_sel",
> > > 19),
> > > +   GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "apll2_sel",
> > > 20),
> > > +   GATE_AUD0(CLK_AUD_TOP0_SPDF, "aud_top0_spdf", "aud_iec_sel",
> > > 21),
> > > +   GATE_AUD0(CLK_AUD_APLL, "aud_apll", "apll1_sel", 23),
> > > +   GATE_AUD0(CLK_AUD_APLL2, "aud_apll2", "apll2_sel", 24),
> > > +   GATE_AUD0(CLK_AUD_DAC, "aud_dac", "a1sys_hp_sel", 25),
> > > +   GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "a1sys_hp_sel",
> > > 26),
> > > +   GATE_AUD0(CLK_AUD_TML, "aud_tml", "a1sys_hp_sel", 27),
> > > +   GATE_AUD0(CLK_AUD_ADC, "aud_adc", "a1sys_hp_sel", 28),
> > > +   GATE_AUD0(CLK_AUD_DAC_HIRES, "aud_dac_hires", "audio_h_sel",
> > > 31),
> > > +   /* AUD1 */
> > > +   GATE_AUD1(CLK_AUD_I2SIN, "aud_i2sin", "a1sys_hp_sel", 0),
> > > +   GATE_AUD1(CLK_AUD_TDM_IN, "aud_tdm_in", "a1sys_hp_sel", 1),
> > > +   GATE_AUD1(CLK_AUD_I2S_OUT, "aud_i2s_out", "a1sys_hp_sel", 6),
> > > +   GATE_AUD1(CLK_AUD_TDM_OUT, "aud_tdm_out", "a1sys_hp_sel", 7),
> > > +   GATE_AUD1(CLK_AUD_HDMI_OUT, "aud_hdmi_out", "a1sys_hp_sel", 8),
> > > +   GATE_AUD1(CLK_AUD_ASRC11, "aud_asrc11", "a1sys_hp_sel", 16),
> > > +   GATE_AUD1(CLK_AUD_ASRC12, "aud_asrc12", "a1sys_hp_sel", 17),
> > > +   GATE_AUD1(CLK_AUD_MULTI_IN, "aud_multi_in", "mphone_slave_b",
> > > 19),
> > > +   GATE_AUD1(CLK_AUD_INTDIR, "aud_intdir", "intdir_sel", 20),
> > > +   GATE_AUD1(CLK_AUD_A1SYS, "aud_a1sys", "a1sys_hp_sel", 21),
> > > +   GATE_AUD1(CLK_AUD_A2SYS, "aud_a2sys", "a2sys_sel", 22),
> > > +   GATE_AUD1(CLK_AUD_PCMIF, "aud_pcmif", "a1sys_hp_sel", 24),
> > > +   GATE_AUD1(CLK_AUD_A3SYS, "aud_a3sys", "a3sys_sel", 30),
> > > +   GATE_AUD1(CLK_AUD_A4SYS, "aud_a4sys", "a4sys_sel", 31),
> > > +   /* AUD2 */
> > > +   GATE_AUD2(CLK_AUD_MEMIF_UL1, "aud_memif_ul1", "a1sys_hp_sel",
> > > 0),
> > > +   GATE_AUD2(CLK_AUD_MEMIF_UL2, "aud_memif_ul2", "a1sys_hp_sel",
> > > 1),
> > > +   GATE_AUD2(CLK_AUD_MEMIF_UL3, "aud_memif_ul3", "a1sys_hp_sel",
> > > 2),
> > > +   GATE_AUD2(CLK_AUD_MEMIF_UL4, "aud_memif_ul4", "a1sys_hp_sel",
> > > 3),
> > > +   GATE_AUD2(CLK_AUD_MEMIF_UL5, "aud_memif_ul5", "a1sys_hp_sel",
> > > 4),
> > > +   GATE_AUD2(CLK_AUD_MEMIF_UL6, "aud_memif_ul6", "a1sys_hp_sel",
> > > 5),
> > > +   GATE_AUD2(CLK_AUD_MEMIF_UL8, "aud_memif_ul8", "a1sys_hp_sel",
> > > 7),
> > > +   GATE_AUD2(CLK_AUD_MEMIF_UL9, "aud_memif_ul9", "a1sys_hp_sel",
> > > 8),
> > > +   GATE_AUD2(CLK_AUD_MEMIF_UL10, "aud_memif_ul10", "a1sys_hp_sel",
> > > 9),
> > > +   GATE_AUD2(CLK_AUD_MEMIF_DL2, "aud_memif_dl2", "a1sys_hp_sel",
> > > 18),
> > > +   GATE_AUD2(CLK_AUD_MEMIF_DL3, "aud_memif_dl3", "a1sys_hp_sel",
> > > 19),
> > > +   GATE_AUD2(CLK_AUD_MEMIF_DL6, "aud_memif_dl6", "a1sys_hp_sel",
> > > 22),
> > > +   GATE_AUD2(CLK_AUD_MEMIF_DL7, "aud_memif_dl7", "a1sys_hp_sel",
> > > 23),
> > > +   GATE_AUD2(CLK_AUD_MEMIF_DL8, "aud_memif_dl8", "a1sys_hp_sel",
> > > 24),
> > > +   GATE_AUD2(CLK_AUD_MEMIF_DL10, "aud_memif_dl10", "a1sys_hp_sel",
> > > 26),
> > > +   GATE_AUD2(CLK_AUD_MEMIF_DL11, "aud_memif_dl11", "a1sys_hp_sel",
> > > 27),
> > > +   /* AUD3 */
> > > +   GATE_AUD3(CLK_AUD_GASRC0, "aud_gasrc0", "asm_h_sel", 0),
> > > +   GATE_AUD3(CLK_AUD_GASRC1, "aud_gasrc1", "asm_h_sel", 1),
> > > +   GATE_AUD3(CLK_AUD_GASRC2, "aud_gasrc2", "asm_h_sel", 2),
> > > +   GATE_AUD3(CLK_AUD_GASRC3, "aud_gasrc3", "asm_h_sel", 3),
> > > +   GATE_AUD3(CLK_AUD_GASRC4, "aud_gasrc4", "asm_h_sel", 4),
> > > +   GATE_AUD3(CLK_AUD_GASRC5, "aud_gasrc5", "asm_h_sel", 5),
> > > +   GATE_AUD3(CLK_AUD_GASRC6, "aud_gasrc6", "asm_h_sel", 6),
> > > +   GATE_AUD3(CLK_AUD_GASRC7, "aud_gasrc7", "asm_h_sel", 7),
> > > +   GATE_AUD3(CLK_AUD_GASRC8, "aud_gasrc8", "asm_h_sel", 8),
> > > +   GATE_AUD3(CLK_AUD_GASRC9, "aud_gasrc9", "asm_h_sel", 9),
> > > +   GATE_AUD3(CLK_AUD_GASRC10, "aud_gasrc10", "asm_h_sel", 10),
> > > +   GATE_AUD3(CLK_AUD_GASRC11, "aud_gasrc11", "asm_h_sel", 11),
> > > +   GATE_AUD3(CLK_AUD_GASRC12, "aud_gasrc12", "asm_h_sel", 12),
> > > +   GATE_AUD3(CLK_AUD_GASRC13, "aud_gasrc13", "asm_h_sel", 13),
> > > +   GATE_AUD3(CLK_AUD_GASRC14, "aud_gasrc14", "asm_h_sel", 14),
> > > +   GATE_AUD3(CLK_AUD_GASRC15, "aud_gasrc15", "asm_h_sel", 15),
> > > +   GATE_AUD3(CLK_AUD_GASRC16, "aud_gasrc16", "asm_h_sel", 16),
> > > +   GATE_AUD3(CLK_AUD_GASRC17, "aud_gasrc17", "asm_h_sel", 17),
> > > +   GATE_AUD3(CLK_AUD_GASRC18, "aud_gasrc18", "asm_h_sel", 18),
> > > +   GATE_AUD3(CLK_AUD_GASRC19, "aud_gasrc19", "asm_h_sel", 19),
> > > +   /* AUD4 */
> > > +   GATE_AUD4(CLK_AUD_A1SYS_HP, "aud_a1sys_hp", "a1sys_hp_sel", 2),
> > > +   GATE_AUD4(CLK_AUD_AFE_DMIC1, "aud_afe_dmic1", "a1sys_hp_sel",
> > > 10),
> > > +   GATE_AUD4(CLK_AUD_AFE_DMIC2, "aud_afe_dmic2", "a1sys_hp_sel",
> > > 11),
> > > +   GATE_AUD4(CLK_AUD_AFE_DMIC3, "aud_afe_dmic3", "a1sys_hp_sel",
> > > 12),
> > > +   GATE_AUD4(CLK_AUD_AFE_DMIC4, "aud_afe_dmic4", "a1sys_hp_sel",
> > > 13),
> > > +   GATE_AUD4(CLK_AUD_AFE_26M_DMIC_TM, "aud_afe_26m_dmic_tm",
> > > "a1sys_hp_sel", 14),
> > > +   GATE_AUD4(CLK_AUD_UL_TML_HIRES, "aud_ul_tml_hires",
> > > "audio_h_sel", 16),
> > > +   GATE_AUD4(CLK_AUD_ADC_HIRES, "aud_adc_hires", "audio_h_sel",
> > > 17),
> > > +   GATE_AUD4(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "a1sys_hp_sel",
> > > 18),
> > > +   GATE_AUD4(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires",
> > > "audio_h_sel", 19),
> > > +   /* AUD5 */
> > > +   GATE_AUD5(CLK_AUD_LINEIN_TUNER, "aud_linein_tuner",
> > > "apll5_sel", 5),
> > > +   GATE_AUD5(CLK_AUD_EARC_TUNER, "aud_earc_tuner", "apll3_sel",
> > > 7),
> > > +};
> >
> > These are all clock gates, and are all internal to the audio
> > hardware,
> > i.e. not used by other drivers or modules.
> >
> > So these don't actually need to be in a separate clk driver. They can
> > be
> > modelled within ASoC as supplies that are automatically managed by
> > ASoC
> > core. Otherwise just have them as bits that are toggled by the audio
> > driver's start/stop sequencing code, like they are now, but through
> > vastly more complicated plumbing.
> >
> > Please work with the audio driver owner to see if this can be moved
> > into
> > the audio driver.
> >
> > Regards
> > ChenYu
> >
>
> The afe device will be the child of audsys clock provider node and
> audsys clock driver will use devm_of_platform_populate() to populate
> afe device when audsys clock gates are registered successfully,
> It means afe will be toggled by audsys clock, do you suggest to change
> the toggled order?

What I'm saying is that they shouldn't be represented as two drivers
and two devices in Linux. They are in the same address space, and the
clocks aren't used by any other hardware block. In the device tree we
should represent them as one unified device, unless there is a good
reason, such as hardware design, not to do so. In the drivers, we can
actually just get rid of the audsys clock driver, and have the afe
driver toggle the clock enable bits directly. Treat them as any other
"enable bits" that exist in any hardware.


ChenYu

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 05/22] clk: mediatek: Add MT8195 audio clock support
  2021-07-12  2:09       ` Chen-Yu Tsai
@ 2021-07-12  4:35         ` Chun-Jie Chen
  2021-07-12  7:06           ` Chen-Yu Tsai
  0 siblings, 1 reply; 59+ messages in thread
From: Chun-Jie Chen @ 2021-07-12  4:35 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Trevor Wu, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
	Rob Herring, linux-arm-kernel, linux-kernel, linux-mediatek,
	linux-clk, devicetree, srv_heupstream,
	Project_Global_Chrome_Upstream_Group

On Mon, 2021-07-12 at 10:09 +0800, Chen-Yu Tsai wrote:
> Hi,
> 
> On Mon, Jul 12, 2021 at 9:26 AM Chun-Jie Chen
> <chun-jie.chen@mediatek.com> wrote:
> > 
> > On Mon, 2021-07-05 at 17:03 +0800, Chen-Yu Tsai wrote:
> > > Hi,
> > > 
> > > On Thu, Jun 17, 2021 at 06:47:26AM +0800, Chun-Jie Chen wrote:
> > > > Add MT8195 audio clock provider
> > > > 
> > > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > > > ---
> > > >  drivers/clk/mediatek/Kconfig          |   6 +
> > > >  drivers/clk/mediatek/Makefile         |   1 +
> > > >  drivers/clk/mediatek/clk-mt8195-aud.c | 198
> > > > ++++++++++++++++++++++++++
> > > >  3 files changed, 205 insertions(+)
> > > >  create mode 100644 drivers/clk/mediatek/clk-mt8195-aud.c
> > > > 
> > > > diff --git a/drivers/clk/mediatek/Kconfig
> > > > b/drivers/clk/mediatek/Kconfig
> > > > index 6707aba3d500..e2bae9d490a4 100644
> > > > --- a/drivers/clk/mediatek/Kconfig
> > > > +++ b/drivers/clk/mediatek/Kconfig
> > > > @@ -588,6 +588,12 @@ config COMMON_CLK_MT8195
> > > >     help
> > > >       This driver supports MediaTek MT8195 basic clocks.
> > > > 
> > > > +config COMMON_CLK_MT8195_AUDSYS
> > > > +   bool "Clock driver for MediaTek MT8195 audsys"
> > > > +   depends on COMMON_CLK_MT8195
> > > > +   help
> > > > +     This driver supports MediaTek MT8195 audsys clocks.
> > > > +
> > > 
> > > The clock modules aren't shared between different chips, so
> > > either we
> > > enable support for all clock hardware in one chip or we don't. It
> > > doesn't make sense to support just some of them. So having just
> > > one
> > > Kconfig option and having all drivers under it is better.
> > > 
> > > >  config COMMON_CLK_MT8516
> > > >     bool "Clock driver for MediaTek MT8516"
> > > >     depends on ARCH_MEDIATEK || COMPILE_TEST
> > > > diff --git a/drivers/clk/mediatek/Makefile
> > > > b/drivers/clk/mediatek/Makefile
> > > > index f8002d8966e1..f27c04314186 100644
> > > > --- a/drivers/clk/mediatek/Makefile
> > > > +++ b/drivers/clk/mediatek/Makefile
> > > > @@ -81,5 +81,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) +=
> > > > clk-
> > > > mt8192-scp_adsp.o
> > > >  obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
> > > >  obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
> > > >  obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195.o
> > > > +obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS) += clk-mt8195-aud.o
> > > >  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
> > > >  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> > > > diff --git a/drivers/clk/mediatek/clk-mt8195-aud.c
> > > > b/drivers/clk/mediatek/clk-mt8195-aud.c
> > > > new file mode 100644
> > > > index 000000000000..db5f80d41de0
> > > > --- /dev/null
> > > > +++ b/drivers/clk/mediatek/clk-mt8195-aud.c
> > > > @@ -0,0 +1,198 @@
> > > > +// SPDX-License-Identifier: GPL-2.0-only
> > > > +//
> > > > +// Copyright (c) 2021 MediaTek Inc.
> > > > +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > > > +
> > > > +#include <linux/clk-provider.h>
> > > > +#include <linux/of_platform.h>
> > > > +#include <linux/platform_device.h>
> > > > +
> > > > +#include "clk-mtk.h"
> > > > +#include "clk-gate.h"
> > > > +
> > > > +#include <dt-bindings/clock/mt8195-clk.h>
> > > > +
> > > > +static const struct mtk_gate_regs aud0_cg_regs = {
> > > > +   .set_ofs = 0x0,
> > > > +   .clr_ofs = 0x0,
> > > > +   .sta_ofs = 0x0,
> > > > +};
> > > > +
> > > > +static const struct mtk_gate_regs aud1_cg_regs = {
> > > > +   .set_ofs = 0x10,
> > > > +   .clr_ofs = 0x10,
> > > > +   .sta_ofs = 0x10,
> > > > +};
> > > > +
> > > > +static const struct mtk_gate_regs aud2_cg_regs = {
> > > > +   .set_ofs = 0x14,
> > > > +   .clr_ofs = 0x14,
> > > > +   .sta_ofs = 0x14,
> > > > +};
> > > > +
> > > > +static const struct mtk_gate_regs aud3_cg_regs = {
> > > > +   .set_ofs = 0x18,
> > > > +   .clr_ofs = 0x18,
> > > > +   .sta_ofs = 0x18,
> > > > +};
> > > > +
> > > > +static const struct mtk_gate_regs aud4_cg_regs = {
> > > > +   .set_ofs = 0x4,
> > > > +   .clr_ofs = 0x4,
> > > > +   .sta_ofs = 0x4,
> > > > +};
> > > > +
> > > > +static const struct mtk_gate_regs aud5_cg_regs = {
> > > > +   .set_ofs = 0xc,
> > > > +   .clr_ofs = 0xc,
> > > > +   .sta_ofs = 0xc,
> > > > +};
> > > > +
> > > > +#define GATE_AUD0(_id, _name, _parent, _shift)
> > > > \
> > > > +   GATE_MTK(_id, _name, _parent, &aud0_cg_regs, _shift,
> > > > &mtk_clk_gate_ops_no_setclr)
> > > > +
> > > > +#define GATE_AUD1(_id, _name, _parent, _shift)
> > > > \
> > > > +   GATE_MTK(_id, _name, _parent, &aud1_cg_regs, _shift,
> > > > &mtk_clk_gate_ops_no_setclr)
> > > > +
> > > > +#define GATE_AUD2(_id, _name, _parent, _shift)
> > > > \
> > > > +   GATE_MTK(_id, _name, _parent, &aud2_cg_regs, _shift,
> > > > &mtk_clk_gate_ops_no_setclr)
> > > > +
> > > > +#define GATE_AUD3(_id, _name, _parent, _shift)
> > > > \
> > > > +   GATE_MTK(_id, _name, _parent, &aud3_cg_regs, _shift,
> > > > &mtk_clk_gate_ops_no_setclr)
> > > > +
> > > > +#define GATE_AUD4(_id, _name, _parent, _shift)
> > > > \
> > > > +   GATE_MTK(_id, _name, _parent, &aud4_cg_regs, _shift,
> > > > &mtk_clk_gate_ops_no_setclr)
> > > > +
> > > > +#define GATE_AUD5(_id, _name, _parent, _shift)
> > > > \
> > > > +   GATE_MTK(_id, _name, _parent, &aud5_cg_regs, _shift,
> > > > &mtk_clk_gate_ops_no_setclr)
> > > > +
> > > > +static const struct mtk_gate aud_clks[] = {
> > > > +   /* AUD0 */
> > > > +   GATE_AUD0(CLK_AUD_AFE, "aud_afe", "a1sys_hp_sel", 2),
> > > > +   GATE_AUD0(CLK_AUD_LRCK_CNT, "aud_lrck_cnt", "a1sys_hp_sel",
> > > > 4),
> > > > +   GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_APLL,
> > > > "aud_spdifin_tuner_apll",
> > > > "apll4_sel", 10),
> > > > +   GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_DBG,
> > > > "aud_spdifin_tuner_dbg",
> > > > "apll4_sel", 11),
> > > > +   GATE_AUD0(CLK_AUD_UL_TML, "aud_ul_tml", "a1sys_hp_sel",
> > > > 18),
> > > > +   GATE_AUD0(CLK_AUD_APLL1_TUNER, "aud_apll1_tuner",
> > > > "apll1_sel",
> > > > 19),
> > > > +   GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner",
> > > > "apll2_sel",
> > > > 20),
> > > > +   GATE_AUD0(CLK_AUD_TOP0_SPDF, "aud_top0_spdf",
> > > > "aud_iec_sel",
> > > > 21),
> > > > +   GATE_AUD0(CLK_AUD_APLL, "aud_apll", "apll1_sel", 23),
> > > > +   GATE_AUD0(CLK_AUD_APLL2, "aud_apll2", "apll2_sel", 24),
> > > > +   GATE_AUD0(CLK_AUD_DAC, "aud_dac", "a1sys_hp_sel", 25),
> > > > +   GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis",
> > > > "a1sys_hp_sel",
> > > > 26),
> > > > +   GATE_AUD0(CLK_AUD_TML, "aud_tml", "a1sys_hp_sel", 27),
> > > > +   GATE_AUD0(CLK_AUD_ADC, "aud_adc", "a1sys_hp_sel", 28),
> > > > +   GATE_AUD0(CLK_AUD_DAC_HIRES, "aud_dac_hires",
> > > > "audio_h_sel",
> > > > 31),
> > > > +   /* AUD1 */
> > > > +   GATE_AUD1(CLK_AUD_I2SIN, "aud_i2sin", "a1sys_hp_sel", 0),
> > > > +   GATE_AUD1(CLK_AUD_TDM_IN, "aud_tdm_in", "a1sys_hp_sel", 1),
> > > > +   GATE_AUD1(CLK_AUD_I2S_OUT, "aud_i2s_out", "a1sys_hp_sel",
> > > > 6),
> > > > +   GATE_AUD1(CLK_AUD_TDM_OUT, "aud_tdm_out", "a1sys_hp_sel",
> > > > 7),
> > > > +   GATE_AUD1(CLK_AUD_HDMI_OUT, "aud_hdmi_out", "a1sys_hp_sel",
> > > > 8),
> > > > +   GATE_AUD1(CLK_AUD_ASRC11, "aud_asrc11", "a1sys_hp_sel",
> > > > 16),
> > > > +   GATE_AUD1(CLK_AUD_ASRC12, "aud_asrc12", "a1sys_hp_sel",
> > > > 17),
> > > > +   GATE_AUD1(CLK_AUD_MULTI_IN, "aud_multi_in",
> > > > "mphone_slave_b",
> > > > 19),
> > > > +   GATE_AUD1(CLK_AUD_INTDIR, "aud_intdir", "intdir_sel", 20),
> > > > +   GATE_AUD1(CLK_AUD_A1SYS, "aud_a1sys", "a1sys_hp_sel", 21),
> > > > +   GATE_AUD1(CLK_AUD_A2SYS, "aud_a2sys", "a2sys_sel", 22),
> > > > +   GATE_AUD1(CLK_AUD_PCMIF, "aud_pcmif", "a1sys_hp_sel", 24),
> > > > +   GATE_AUD1(CLK_AUD_A3SYS, "aud_a3sys", "a3sys_sel", 30),
> > > > +   GATE_AUD1(CLK_AUD_A4SYS, "aud_a4sys", "a4sys_sel", 31),
> > > > +   /* AUD2 */
> > > > +   GATE_AUD2(CLK_AUD_MEMIF_UL1, "aud_memif_ul1",
> > > > "a1sys_hp_sel",
> > > > 0),
> > > > +   GATE_AUD2(CLK_AUD_MEMIF_UL2, "aud_memif_ul2",
> > > > "a1sys_hp_sel",
> > > > 1),
> > > > +   GATE_AUD2(CLK_AUD_MEMIF_UL3, "aud_memif_ul3",
> > > > "a1sys_hp_sel",
> > > > 2),
> > > > +   GATE_AUD2(CLK_AUD_MEMIF_UL4, "aud_memif_ul4",
> > > > "a1sys_hp_sel",
> > > > 3),
> > > > +   GATE_AUD2(CLK_AUD_MEMIF_UL5, "aud_memif_ul5",
> > > > "a1sys_hp_sel",
> > > > 4),
> > > > +   GATE_AUD2(CLK_AUD_MEMIF_UL6, "aud_memif_ul6",
> > > > "a1sys_hp_sel",
> > > > 5),
> > > > +   GATE_AUD2(CLK_AUD_MEMIF_UL8, "aud_memif_ul8",
> > > > "a1sys_hp_sel",
> > > > 7),
> > > > +   GATE_AUD2(CLK_AUD_MEMIF_UL9, "aud_memif_ul9",
> > > > "a1sys_hp_sel",
> > > > 8),
> > > > +   GATE_AUD2(CLK_AUD_MEMIF_UL10, "aud_memif_ul10",
> > > > "a1sys_hp_sel",
> > > > 9),
> > > > +   GATE_AUD2(CLK_AUD_MEMIF_DL2, "aud_memif_dl2",
> > > > "a1sys_hp_sel",
> > > > 18),
> > > > +   GATE_AUD2(CLK_AUD_MEMIF_DL3, "aud_memif_dl3",
> > > > "a1sys_hp_sel",
> > > > 19),
> > > > +   GATE_AUD2(CLK_AUD_MEMIF_DL6, "aud_memif_dl6",
> > > > "a1sys_hp_sel",
> > > > 22),
> > > > +   GATE_AUD2(CLK_AUD_MEMIF_DL7, "aud_memif_dl7",
> > > > "a1sys_hp_sel",
> > > > 23),
> > > > +   GATE_AUD2(CLK_AUD_MEMIF_DL8, "aud_memif_dl8",
> > > > "a1sys_hp_sel",
> > > > 24),
> > > > +   GATE_AUD2(CLK_AUD_MEMIF_DL10, "aud_memif_dl10",
> > > > "a1sys_hp_sel",
> > > > 26),
> > > > +   GATE_AUD2(CLK_AUD_MEMIF_DL11, "aud_memif_dl11",
> > > > "a1sys_hp_sel",
> > > > 27),
> > > > +   /* AUD3 */
> > > > +   GATE_AUD3(CLK_AUD_GASRC0, "aud_gasrc0", "asm_h_sel", 0),
> > > > +   GATE_AUD3(CLK_AUD_GASRC1, "aud_gasrc1", "asm_h_sel", 1),
> > > > +   GATE_AUD3(CLK_AUD_GASRC2, "aud_gasrc2", "asm_h_sel", 2),
> > > > +   GATE_AUD3(CLK_AUD_GASRC3, "aud_gasrc3", "asm_h_sel", 3),
> > > > +   GATE_AUD3(CLK_AUD_GASRC4, "aud_gasrc4", "asm_h_sel", 4),
> > > > +   GATE_AUD3(CLK_AUD_GASRC5, "aud_gasrc5", "asm_h_sel", 5),
> > > > +   GATE_AUD3(CLK_AUD_GASRC6, "aud_gasrc6", "asm_h_sel", 6),
> > > > +   GATE_AUD3(CLK_AUD_GASRC7, "aud_gasrc7", "asm_h_sel", 7),
> > > > +   GATE_AUD3(CLK_AUD_GASRC8, "aud_gasrc8", "asm_h_sel", 8),
> > > > +   GATE_AUD3(CLK_AUD_GASRC9, "aud_gasrc9", "asm_h_sel", 9),
> > > > +   GATE_AUD3(CLK_AUD_GASRC10, "aud_gasrc10", "asm_h_sel", 10),
> > > > +   GATE_AUD3(CLK_AUD_GASRC11, "aud_gasrc11", "asm_h_sel", 11),
> > > > +   GATE_AUD3(CLK_AUD_GASRC12, "aud_gasrc12", "asm_h_sel", 12),
> > > > +   GATE_AUD3(CLK_AUD_GASRC13, "aud_gasrc13", "asm_h_sel", 13),
> > > > +   GATE_AUD3(CLK_AUD_GASRC14, "aud_gasrc14", "asm_h_sel", 14),
> > > > +   GATE_AUD3(CLK_AUD_GASRC15, "aud_gasrc15", "asm_h_sel", 15),
> > > > +   GATE_AUD3(CLK_AUD_GASRC16, "aud_gasrc16", "asm_h_sel", 16),
> > > > +   GATE_AUD3(CLK_AUD_GASRC17, "aud_gasrc17", "asm_h_sel", 17),
> > > > +   GATE_AUD3(CLK_AUD_GASRC18, "aud_gasrc18", "asm_h_sel", 18),
> > > > +   GATE_AUD3(CLK_AUD_GASRC19, "aud_gasrc19", "asm_h_sel", 19),
> > > > +   /* AUD4 */
> > > > +   GATE_AUD4(CLK_AUD_A1SYS_HP, "aud_a1sys_hp", "a1sys_hp_sel",
> > > > 2),
> > > > +   GATE_AUD4(CLK_AUD_AFE_DMIC1, "aud_afe_dmic1",
> > > > "a1sys_hp_sel",
> > > > 10),
> > > > +   GATE_AUD4(CLK_AUD_AFE_DMIC2, "aud_afe_dmic2",
> > > > "a1sys_hp_sel",
> > > > 11),
> > > > +   GATE_AUD4(CLK_AUD_AFE_DMIC3, "aud_afe_dmic3",
> > > > "a1sys_hp_sel",
> > > > 12),
> > > > +   GATE_AUD4(CLK_AUD_AFE_DMIC4, "aud_afe_dmic4",
> > > > "a1sys_hp_sel",
> > > > 13),
> > > > +   GATE_AUD4(CLK_AUD_AFE_26M_DMIC_TM, "aud_afe_26m_dmic_tm",
> > > > "a1sys_hp_sel", 14),
> > > > +   GATE_AUD4(CLK_AUD_UL_TML_HIRES, "aud_ul_tml_hires",
> > > > "audio_h_sel", 16),
> > > > +   GATE_AUD4(CLK_AUD_ADC_HIRES, "aud_adc_hires",
> > > > "audio_h_sel",
> > > > 17),
> > > > +   GATE_AUD4(CLK_AUD_ADDA6_ADC, "aud_adda6_adc",
> > > > "a1sys_hp_sel",
> > > > 18),
> > > > +   GATE_AUD4(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires",
> > > > "audio_h_sel", 19),
> > > > +   /* AUD5 */
> > > > +   GATE_AUD5(CLK_AUD_LINEIN_TUNER, "aud_linein_tuner",
> > > > "apll5_sel", 5),
> > > > +   GATE_AUD5(CLK_AUD_EARC_TUNER, "aud_earc_tuner",
> > > > "apll3_sel",
> > > > 7),
> > > > +};
> > > 
> > > These are all clock gates, and are all internal to the audio
> > > hardware,
> > > i.e. not used by other drivers or modules.
> > > 
> > > So these don't actually need to be in a separate clk driver. They
> > > can
> > > be
> > > modelled within ASoC as supplies that are automatically managed
> > > by
> > > ASoC
> > > core. Otherwise just have them as bits that are toggled by the
> > > audio
> > > driver's start/stop sequencing code, like they are now, but
> > > through
> > > vastly more complicated plumbing.
> > > 
> > > Please work with the audio driver owner to see if this can be
> > > moved
> > > into
> > > the audio driver.
> > > 
> > > Regards
> > > ChenYu
> > > 
> > 
> > The afe device will be the child of audsys clock provider node and
> > audsys clock driver will use devm_of_platform_populate() to
> > populate
> > afe device when audsys clock gates are registered successfully,
> > It means afe will be toggled by audsys clock, do you suggest to
> > change
> > the toggled order?
> 
> What I'm saying is that they shouldn't be represented as two drivers
> and two devices in Linux. They are in the same address space, and the
> clocks aren't used by any other hardware block. In the device tree we
> should represent them as one unified device, unless there is a good
> reason, such as hardware design, not to do so. In the drivers, we can
> actually just get rid of the audsys clock driver, and have the afe
> driver toggle the clock enable bits directly. Treat them as any other
> "enable bits" that exist in any hardware.
> 
> 
> ChenYu

Because the parent source of audio clock gate is other clocks model in
CCF, if we get rid of the audsys clock driver then audio driver need to
guarantee the clock dependence by itself, that makes the control of
audsys clock gate more complicated.

Best Regards,
Chun-Jie

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 05/22] clk: mediatek: Add MT8195 audio clock support
  2021-07-12  4:35         ` Chun-Jie Chen
@ 2021-07-12  7:06           ` Chen-Yu Tsai
  0 siblings, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-12  7:06 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Trevor Wu, Matthias Brugger, Stephen Boyd, Nicolas Boichat,
	Rob Herring, linux-arm-kernel, linux-kernel, linux-mediatek,
	linux-clk, devicetree, srv_heupstream,
	Project_Global_Chrome_Upstream_Group

On Mon, Jul 12, 2021 at 12:35 PM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> On Mon, 2021-07-12 at 10:09 +0800, Chen-Yu Tsai wrote:
> > Hi,
> >
> > On Mon, Jul 12, 2021 at 9:26 AM Chun-Jie Chen
> > <chun-jie.chen@mediatek.com> wrote:
> > >
> > > On Mon, 2021-07-05 at 17:03 +0800, Chen-Yu Tsai wrote:
> > > > Hi,
> > > >
> > > > On Thu, Jun 17, 2021 at 06:47:26AM +0800, Chun-Jie Chen wrote:
> > > > > Add MT8195 audio clock provider
> > > > >
> > > > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > > > > ---
> > > > >  drivers/clk/mediatek/Kconfig          |   6 +
> > > > >  drivers/clk/mediatek/Makefile         |   1 +
> > > > >  drivers/clk/mediatek/clk-mt8195-aud.c | 198
> > > > > ++++++++++++++++++++++++++
> > > > >  3 files changed, 205 insertions(+)
> > > > >  create mode 100644 drivers/clk/mediatek/clk-mt8195-aud.c
> > > > >
> > > > > diff --git a/drivers/clk/mediatek/Kconfig
> > > > > b/drivers/clk/mediatek/Kconfig
> > > > > index 6707aba3d500..e2bae9d490a4 100644
> > > > > --- a/drivers/clk/mediatek/Kconfig
> > > > > +++ b/drivers/clk/mediatek/Kconfig
> > > > > @@ -588,6 +588,12 @@ config COMMON_CLK_MT8195
> > > > >     help
> > > > >       This driver supports MediaTek MT8195 basic clocks.
> > > > >
> > > > > +config COMMON_CLK_MT8195_AUDSYS
> > > > > +   bool "Clock driver for MediaTek MT8195 audsys"
> > > > > +   depends on COMMON_CLK_MT8195
> > > > > +   help
> > > > > +     This driver supports MediaTek MT8195 audsys clocks.
> > > > > +
> > > >
> > > > The clock modules aren't shared between different chips, so
> > > > either we
> > > > enable support for all clock hardware in one chip or we don't. It
> > > > doesn't make sense to support just some of them. So having just
> > > > one
> > > > Kconfig option and having all drivers under it is better.
> > > >
> > > > >  config COMMON_CLK_MT8516
> > > > >     bool "Clock driver for MediaTek MT8516"
> > > > >     depends on ARCH_MEDIATEK || COMPILE_TEST
> > > > > diff --git a/drivers/clk/mediatek/Makefile
> > > > > b/drivers/clk/mediatek/Makefile
> > > > > index f8002d8966e1..f27c04314186 100644
> > > > > --- a/drivers/clk/mediatek/Makefile
> > > > > +++ b/drivers/clk/mediatek/Makefile
> > > > > @@ -81,5 +81,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) +=
> > > > > clk-
> > > > > mt8192-scp_adsp.o
> > > > >  obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
> > > > >  obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
> > > > >  obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195.o
> > > > > +obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS) += clk-mt8195-aud.o
> > > > >  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
> > > > >  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> > > > > diff --git a/drivers/clk/mediatek/clk-mt8195-aud.c
> > > > > b/drivers/clk/mediatek/clk-mt8195-aud.c
> > > > > new file mode 100644
> > > > > index 000000000000..db5f80d41de0
> > > > > --- /dev/null
> > > > > +++ b/drivers/clk/mediatek/clk-mt8195-aud.c
> > > > > @@ -0,0 +1,198 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0-only
> > > > > +//
> > > > > +// Copyright (c) 2021 MediaTek Inc.
> > > > > +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > > > > +
> > > > > +#include <linux/clk-provider.h>
> > > > > +#include <linux/of_platform.h>
> > > > > +#include <linux/platform_device.h>
> > > > > +
> > > > > +#include "clk-mtk.h"
> > > > > +#include "clk-gate.h"
> > > > > +
> > > > > +#include <dt-bindings/clock/mt8195-clk.h>
> > > > > +
> > > > > +static const struct mtk_gate_regs aud0_cg_regs = {
> > > > > +   .set_ofs = 0x0,
> > > > > +   .clr_ofs = 0x0,
> > > > > +   .sta_ofs = 0x0,
> > > > > +};
> > > > > +
> > > > > +static const struct mtk_gate_regs aud1_cg_regs = {
> > > > > +   .set_ofs = 0x10,
> > > > > +   .clr_ofs = 0x10,
> > > > > +   .sta_ofs = 0x10,
> > > > > +};
> > > > > +
> > > > > +static const struct mtk_gate_regs aud2_cg_regs = {
> > > > > +   .set_ofs = 0x14,
> > > > > +   .clr_ofs = 0x14,
> > > > > +   .sta_ofs = 0x14,
> > > > > +};
> > > > > +
> > > > > +static const struct mtk_gate_regs aud3_cg_regs = {
> > > > > +   .set_ofs = 0x18,
> > > > > +   .clr_ofs = 0x18,
> > > > > +   .sta_ofs = 0x18,
> > > > > +};
> > > > > +
> > > > > +static const struct mtk_gate_regs aud4_cg_regs = {
> > > > > +   .set_ofs = 0x4,
> > > > > +   .clr_ofs = 0x4,
> > > > > +   .sta_ofs = 0x4,
> > > > > +};
> > > > > +
> > > > > +static const struct mtk_gate_regs aud5_cg_regs = {
> > > > > +   .set_ofs = 0xc,
> > > > > +   .clr_ofs = 0xc,
> > > > > +   .sta_ofs = 0xc,
> > > > > +};
> > > > > +
> > > > > +#define GATE_AUD0(_id, _name, _parent, _shift)
> > > > > \
> > > > > +   GATE_MTK(_id, _name, _parent, &aud0_cg_regs, _shift,
> > > > > &mtk_clk_gate_ops_no_setclr)
> > > > > +
> > > > > +#define GATE_AUD1(_id, _name, _parent, _shift)
> > > > > \
> > > > > +   GATE_MTK(_id, _name, _parent, &aud1_cg_regs, _shift,
> > > > > &mtk_clk_gate_ops_no_setclr)
> > > > > +
> > > > > +#define GATE_AUD2(_id, _name, _parent, _shift)
> > > > > \
> > > > > +   GATE_MTK(_id, _name, _parent, &aud2_cg_regs, _shift,
> > > > > &mtk_clk_gate_ops_no_setclr)
> > > > > +
> > > > > +#define GATE_AUD3(_id, _name, _parent, _shift)
> > > > > \
> > > > > +   GATE_MTK(_id, _name, _parent, &aud3_cg_regs, _shift,
> > > > > &mtk_clk_gate_ops_no_setclr)
> > > > > +
> > > > > +#define GATE_AUD4(_id, _name, _parent, _shift)
> > > > > \
> > > > > +   GATE_MTK(_id, _name, _parent, &aud4_cg_regs, _shift,
> > > > > &mtk_clk_gate_ops_no_setclr)
> > > > > +
> > > > > +#define GATE_AUD5(_id, _name, _parent, _shift)
> > > > > \
> > > > > +   GATE_MTK(_id, _name, _parent, &aud5_cg_regs, _shift,
> > > > > &mtk_clk_gate_ops_no_setclr)
> > > > > +
> > > > > +static const struct mtk_gate aud_clks[] = {
> > > > > +   /* AUD0 */
> > > > > +   GATE_AUD0(CLK_AUD_AFE, "aud_afe", "a1sys_hp_sel", 2),
> > > > > +   GATE_AUD0(CLK_AUD_LRCK_CNT, "aud_lrck_cnt", "a1sys_hp_sel",
> > > > > 4),
> > > > > +   GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_APLL,
> > > > > "aud_spdifin_tuner_apll",
> > > > > "apll4_sel", 10),
> > > > > +   GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_DBG,
> > > > > "aud_spdifin_tuner_dbg",
> > > > > "apll4_sel", 11),
> > > > > +   GATE_AUD0(CLK_AUD_UL_TML, "aud_ul_tml", "a1sys_hp_sel",
> > > > > 18),
> > > > > +   GATE_AUD0(CLK_AUD_APLL1_TUNER, "aud_apll1_tuner",
> > > > > "apll1_sel",
> > > > > 19),
> > > > > +   GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner",
> > > > > "apll2_sel",
> > > > > 20),
> > > > > +   GATE_AUD0(CLK_AUD_TOP0_SPDF, "aud_top0_spdf",
> > > > > "aud_iec_sel",
> > > > > 21),
> > > > > +   GATE_AUD0(CLK_AUD_APLL, "aud_apll", "apll1_sel", 23),
> > > > > +   GATE_AUD0(CLK_AUD_APLL2, "aud_apll2", "apll2_sel", 24),
> > > > > +   GATE_AUD0(CLK_AUD_DAC, "aud_dac", "a1sys_hp_sel", 25),
> > > > > +   GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis",
> > > > > "a1sys_hp_sel",
> > > > > 26),
> > > > > +   GATE_AUD0(CLK_AUD_TML, "aud_tml", "a1sys_hp_sel", 27),
> > > > > +   GATE_AUD0(CLK_AUD_ADC, "aud_adc", "a1sys_hp_sel", 28),
> > > > > +   GATE_AUD0(CLK_AUD_DAC_HIRES, "aud_dac_hires",
> > > > > "audio_h_sel",
> > > > > 31),
> > > > > +   /* AUD1 */
> > > > > +   GATE_AUD1(CLK_AUD_I2SIN, "aud_i2sin", "a1sys_hp_sel", 0),
> > > > > +   GATE_AUD1(CLK_AUD_TDM_IN, "aud_tdm_in", "a1sys_hp_sel", 1),
> > > > > +   GATE_AUD1(CLK_AUD_I2S_OUT, "aud_i2s_out", "a1sys_hp_sel",
> > > > > 6),
> > > > > +   GATE_AUD1(CLK_AUD_TDM_OUT, "aud_tdm_out", "a1sys_hp_sel",
> > > > > 7),
> > > > > +   GATE_AUD1(CLK_AUD_HDMI_OUT, "aud_hdmi_out", "a1sys_hp_sel",
> > > > > 8),
> > > > > +   GATE_AUD1(CLK_AUD_ASRC11, "aud_asrc11", "a1sys_hp_sel",
> > > > > 16),
> > > > > +   GATE_AUD1(CLK_AUD_ASRC12, "aud_asrc12", "a1sys_hp_sel",
> > > > > 17),
> > > > > +   GATE_AUD1(CLK_AUD_MULTI_IN, "aud_multi_in",
> > > > > "mphone_slave_b",
> > > > > 19),
> > > > > +   GATE_AUD1(CLK_AUD_INTDIR, "aud_intdir", "intdir_sel", 20),
> > > > > +   GATE_AUD1(CLK_AUD_A1SYS, "aud_a1sys", "a1sys_hp_sel", 21),
> > > > > +   GATE_AUD1(CLK_AUD_A2SYS, "aud_a2sys", "a2sys_sel", 22),
> > > > > +   GATE_AUD1(CLK_AUD_PCMIF, "aud_pcmif", "a1sys_hp_sel", 24),
> > > > > +   GATE_AUD1(CLK_AUD_A3SYS, "aud_a3sys", "a3sys_sel", 30),
> > > > > +   GATE_AUD1(CLK_AUD_A4SYS, "aud_a4sys", "a4sys_sel", 31),
> > > > > +   /* AUD2 */
> > > > > +   GATE_AUD2(CLK_AUD_MEMIF_UL1, "aud_memif_ul1",
> > > > > "a1sys_hp_sel",
> > > > > 0),
> > > > > +   GATE_AUD2(CLK_AUD_MEMIF_UL2, "aud_memif_ul2",
> > > > > "a1sys_hp_sel",
> > > > > 1),
> > > > > +   GATE_AUD2(CLK_AUD_MEMIF_UL3, "aud_memif_ul3",
> > > > > "a1sys_hp_sel",
> > > > > 2),
> > > > > +   GATE_AUD2(CLK_AUD_MEMIF_UL4, "aud_memif_ul4",
> > > > > "a1sys_hp_sel",
> > > > > 3),
> > > > > +   GATE_AUD2(CLK_AUD_MEMIF_UL5, "aud_memif_ul5",
> > > > > "a1sys_hp_sel",
> > > > > 4),
> > > > > +   GATE_AUD2(CLK_AUD_MEMIF_UL6, "aud_memif_ul6",
> > > > > "a1sys_hp_sel",
> > > > > 5),
> > > > > +   GATE_AUD2(CLK_AUD_MEMIF_UL8, "aud_memif_ul8",
> > > > > "a1sys_hp_sel",
> > > > > 7),
> > > > > +   GATE_AUD2(CLK_AUD_MEMIF_UL9, "aud_memif_ul9",
> > > > > "a1sys_hp_sel",
> > > > > 8),
> > > > > +   GATE_AUD2(CLK_AUD_MEMIF_UL10, "aud_memif_ul10",
> > > > > "a1sys_hp_sel",
> > > > > 9),
> > > > > +   GATE_AUD2(CLK_AUD_MEMIF_DL2, "aud_memif_dl2",
> > > > > "a1sys_hp_sel",
> > > > > 18),
> > > > > +   GATE_AUD2(CLK_AUD_MEMIF_DL3, "aud_memif_dl3",
> > > > > "a1sys_hp_sel",
> > > > > 19),
> > > > > +   GATE_AUD2(CLK_AUD_MEMIF_DL6, "aud_memif_dl6",
> > > > > "a1sys_hp_sel",
> > > > > 22),
> > > > > +   GATE_AUD2(CLK_AUD_MEMIF_DL7, "aud_memif_dl7",
> > > > > "a1sys_hp_sel",
> > > > > 23),
> > > > > +   GATE_AUD2(CLK_AUD_MEMIF_DL8, "aud_memif_dl8",
> > > > > "a1sys_hp_sel",
> > > > > 24),
> > > > > +   GATE_AUD2(CLK_AUD_MEMIF_DL10, "aud_memif_dl10",
> > > > > "a1sys_hp_sel",
> > > > > 26),
> > > > > +   GATE_AUD2(CLK_AUD_MEMIF_DL11, "aud_memif_dl11",
> > > > > "a1sys_hp_sel",
> > > > > 27),
> > > > > +   /* AUD3 */
> > > > > +   GATE_AUD3(CLK_AUD_GASRC0, "aud_gasrc0", "asm_h_sel", 0),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC1, "aud_gasrc1", "asm_h_sel", 1),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC2, "aud_gasrc2", "asm_h_sel", 2),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC3, "aud_gasrc3", "asm_h_sel", 3),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC4, "aud_gasrc4", "asm_h_sel", 4),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC5, "aud_gasrc5", "asm_h_sel", 5),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC6, "aud_gasrc6", "asm_h_sel", 6),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC7, "aud_gasrc7", "asm_h_sel", 7),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC8, "aud_gasrc8", "asm_h_sel", 8),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC9, "aud_gasrc9", "asm_h_sel", 9),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC10, "aud_gasrc10", "asm_h_sel", 10),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC11, "aud_gasrc11", "asm_h_sel", 11),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC12, "aud_gasrc12", "asm_h_sel", 12),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC13, "aud_gasrc13", "asm_h_sel", 13),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC14, "aud_gasrc14", "asm_h_sel", 14),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC15, "aud_gasrc15", "asm_h_sel", 15),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC16, "aud_gasrc16", "asm_h_sel", 16),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC17, "aud_gasrc17", "asm_h_sel", 17),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC18, "aud_gasrc18", "asm_h_sel", 18),
> > > > > +   GATE_AUD3(CLK_AUD_GASRC19, "aud_gasrc19", "asm_h_sel", 19),
> > > > > +   /* AUD4 */
> > > > > +   GATE_AUD4(CLK_AUD_A1SYS_HP, "aud_a1sys_hp", "a1sys_hp_sel",
> > > > > 2),
> > > > > +   GATE_AUD4(CLK_AUD_AFE_DMIC1, "aud_afe_dmic1",
> > > > > "a1sys_hp_sel",
> > > > > 10),
> > > > > +   GATE_AUD4(CLK_AUD_AFE_DMIC2, "aud_afe_dmic2",
> > > > > "a1sys_hp_sel",
> > > > > 11),
> > > > > +   GATE_AUD4(CLK_AUD_AFE_DMIC3, "aud_afe_dmic3",
> > > > > "a1sys_hp_sel",
> > > > > 12),
> > > > > +   GATE_AUD4(CLK_AUD_AFE_DMIC4, "aud_afe_dmic4",
> > > > > "a1sys_hp_sel",
> > > > > 13),
> > > > > +   GATE_AUD4(CLK_AUD_AFE_26M_DMIC_TM, "aud_afe_26m_dmic_tm",
> > > > > "a1sys_hp_sel", 14),
> > > > > +   GATE_AUD4(CLK_AUD_UL_TML_HIRES, "aud_ul_tml_hires",
> > > > > "audio_h_sel", 16),
> > > > > +   GATE_AUD4(CLK_AUD_ADC_HIRES, "aud_adc_hires",
> > > > > "audio_h_sel",
> > > > > 17),
> > > > > +   GATE_AUD4(CLK_AUD_ADDA6_ADC, "aud_adda6_adc",
> > > > > "a1sys_hp_sel",
> > > > > 18),
> > > > > +   GATE_AUD4(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires",
> > > > > "audio_h_sel", 19),
> > > > > +   /* AUD5 */
> > > > > +   GATE_AUD5(CLK_AUD_LINEIN_TUNER, "aud_linein_tuner",
> > > > > "apll5_sel", 5),
> > > > > +   GATE_AUD5(CLK_AUD_EARC_TUNER, "aud_earc_tuner",
> > > > > "apll3_sel",
> > > > > 7),
> > > > > +};
> > > >
> > > > These are all clock gates, and are all internal to the audio
> > > > hardware,
> > > > i.e. not used by other drivers or modules.
> > > >
> > > > So these don't actually need to be in a separate clk driver. They
> > > > can
> > > > be
> > > > modelled within ASoC as supplies that are automatically managed
> > > > by
> > > > ASoC
> > > > core. Otherwise just have them as bits that are toggled by the
> > > > audio
> > > > driver's start/stop sequencing code, like they are now, but
> > > > through
> > > > vastly more complicated plumbing.
> > > >
> > > > Please work with the audio driver owner to see if this can be
> > > > moved
> > > > into
> > > > the audio driver.
> > > >
> > > > Regards
> > > > ChenYu
> > > >
> > >
> > > The afe device will be the child of audsys clock provider node and
> > > audsys clock driver will use devm_of_platform_populate() to
> > > populate
> > > afe device when audsys clock gates are registered successfully,
> > > It means afe will be toggled by audsys clock, do you suggest to
> > > change
> > > the toggled order?
> >
> > What I'm saying is that they shouldn't be represented as two drivers
> > and two devices in Linux. They are in the same address space, and the
> > clocks aren't used by any other hardware block. In the device tree we
> > should represent them as one unified device, unless there is a good
> > reason, such as hardware design, not to do so. In the drivers, we can
> > actually just get rid of the audsys clock driver, and have the afe
> > driver toggle the clock enable bits directly. Treat them as any other
> > "enable bits" that exist in any hardware.
> >
> >
> > ChenYu
>
> Because the parent source of audio clock gate is other clocks model in
> CCF, if we get rid of the audsys clock driver then audio driver need to
> guarantee the clock dependence by itself, that makes the control of
> audsys clock gate more complicated.

Could you elaborate on "guarantee clock dependence"?

There is no need to model the audio clock gates in the CCF. That is
actually overcomplicating things. If you really wanted to you could
still do it in the audio driver, either using the CCF, only using
ASoC supplies. The whole audio subsystem hardware is self-contained,
so the representation and driver should be as well, unless there is
a very good reason to split it up.

Also, if a clock driver is present, then maybe it should model all
clocks, not just some of them? For example, the PLLs in the audio
subsystem aren't modeled here, but handled internally in the audio
driver. So why can't the clock gates be handled there as well?

And the audio driver is already reaching into the other clock controllers
with direct references to PLLs and other clock parents, which IMO is a bad
representation. The only clocks the audio driver should reference are the
ones that actually feed the hardware directly. Anything before that should
be handled by the parent clock driver. If a specific clock rate needs to
be set, the audio driver should set it on the clock that feeds it, and
the CCF, though the CLK_SET_RATE_PARENT flag, passed the request up the
clock tree. Same thing for reparenting, it should be automatic.


Regards
ChenYu

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 21/22] clk: mediatek: Add MT8195 imp i2c wrapper clock support
  2021-06-16 22:47 ` [PATCH 21/22] clk: mediatek: Add MT8195 imp i2c wrapper " Chun-Jie Chen
@ 2021-07-12  8:34   ` Chen-Yu Tsai
  0 siblings, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-12  8:34 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

Hi,

On Thu, Jun 17, 2021 at 6:59 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 imp i2c wrapper clock providers
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  drivers/clk/mediatek/Kconfig                  |  6 ++
>  drivers/clk/mediatek/Makefile                 |  1 +
>  .../clk/mediatek/clk-mt8195-imp_iic_wrap.c    | 68 +++++++++++++++++++
>  3 files changed, 75 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 5089bacdf0a5..ade85a52b7ed 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -684,6 +684,12 @@ config COMMON_CLK_MT8195_WPESYS
>         help
>           This driver supports MediaTek MT8195 wpesys clocks.
>
> +config COMMON_CLK_MT8195_IMP_IIC_WRAP
> +       bool "Clock driver for MediaTek MT8195 imp_iic_wrap"
> +       depends on COMMON_CLK_MT8195
> +       help
> +         This driver supports MediaTek MT8195 imp_iic_wrap clocks.
> +

General comments from other patches also apply.

>  config COMMON_CLK_MT8516
>         bool "Clock driver for MediaTek MT8516"
>         depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 32cfb0030d92..b10c6267ba98 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -97,5 +97,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS0) += clk-mt8195-vpp0.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS1) += clk-mt8195-vpp1.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
> +obj-$(CONFIG_COMMON_CLK_MT8195_IMP_IIC_WRAP) += clk-mt8195-imp_iic_wrap.o
>  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
>  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c
> new file mode 100644
> index 000000000000..efb62f484bbe
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c
> @@ -0,0 +1,68 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +
> +static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
> +       .set_ofs = 0xe08,
> +       .clr_ofs = 0xe04,
> +       .sta_ofs = 0xe00,
> +};
> +
> +#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift)                         \
> +       GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift,      \
> +               &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
> +
> +static const struct mtk_gate imp_iic_wrap_s_clks[] = {
> +       GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C5, "imp_iic_wrap_s_i2c5", "i2c_sel", 0),
> +       GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C6, "imp_iic_wrap_s_i2c6", "i2c_sel", 1),
> +       GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C7, "imp_iic_wrap_s_i2c7", "i2c_sel", 2),
> +};
> +
> +static const struct mtk_gate imp_iic_wrap_w_clks[] = {
> +       GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C0, "imp_iic_wrap_w_i2c0", "i2c_sel", 0),
> +       GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C1, "imp_iic_wrap_w_i2c1", "i2c_sel", 1),
> +       GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C2, "imp_iic_wrap_w_i2c2", "i2c_sel", 2),
> +       GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C3, "imp_iic_wrap_w_i2c3", "i2c_sel", 3),
> +       GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C4, "imp_iic_wrap_w_i2c4", "i2c_sel", 4),

The datasheet doesn't provide the actual index numbers for each bit,
but based on the address range groupings I'd say the numbering here
is reasonable.


ChenYu

> +};
> +
> +static const struct mtk_clk_desc imp_iic_wrap_s_desc = {
> +       .clks = imp_iic_wrap_s_clks,
> +       .num_clks = ARRAY_SIZE(imp_iic_wrap_s_clks),
> +};
> +
> +static const struct mtk_clk_desc imp_iic_wrap_w_desc = {
> +       .clks = imp_iic_wrap_w_clks,
> +       .num_clks = ARRAY_SIZE(imp_iic_wrap_w_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8195_imp_iic_wrap[] = {
> +       {
> +               .compatible = "mediatek,mt8195-imp_iic_wrap_s",
> +               .data = &imp_iic_wrap_s_desc,
> +       }, {
> +               .compatible = "mediatek,mt8195-imp_iic_wrap_w",
> +               .data = &imp_iic_wrap_w_desc,
> +       }, {
> +               /* sentinel */
> +       }
> +};
> +
> +static struct platform_driver clk_mt8195_imp_iic_wrap_drv = {
> +       .probe = mtk_clk_simple_probe,
> +       .driver = {
> +               .name = "clk-mt8195-imp_iic_wrap",
> +               .of_match_table = of_match_clk_mt8195_imp_iic_wrap,
> +       },
> +};
> +
> +builtin_platform_driver(clk_mt8195_imp_iic_wrap_drv);
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 22/22] clk: mediatek: Add MT8195 apusys clock support
  2021-06-16 22:47 ` [PATCH 22/22] clk: mediatek: Add MT8195 apusys " Chun-Jie Chen
@ 2021-07-12  8:51   ` Chen-Yu Tsai
  0 siblings, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-12  8:51 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

Hi,

On Thu, Jun 17, 2021 at 7:00 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 apusys clock provider
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  drivers/clk/mediatek/Kconfig                 |  6 ++
>  drivers/clk/mediatek/Makefile                |  1 +
>  drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 84 ++++++++++++++++++++
>  3 files changed, 91 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt8195-apusys_pll.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index ade85a52b7ed..9bd1ebff61f2 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -690,6 +690,12 @@ config COMMON_CLK_MT8195_IMP_IIC_WRAP
>         help
>           This driver supports MediaTek MT8195 imp_iic_wrap clocks.
>
> +config COMMON_CLK_MT8195_APUSYS_PLL
> +       bool "Clock driver for MediaTek MT8195 apusys_pll"
> +       depends on COMMON_CLK_MT8195
> +       help
> +         This driver supports MediaTek MT8195 apusys_pll clocks.
> +
>  config COMMON_CLK_MT8516
>         bool "Clock driver for MediaTek MT8516"
>         depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index b10c6267ba98..676ed7d665b7 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -98,5 +98,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS0) += clk-mt8195-vpp0.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS1) += clk-mt8195-vpp1.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_IMP_IIC_WRAP) += clk-mt8195-imp_iic_wrap.o
> +obj-$(CONFIG_COMMON_CLK_MT8195_APUSYS_PLL) += clk-mt8195-apusys_pll.o
>  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
>  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c
> new file mode 100644
> index 000000000000..d9b49cf71281
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c
> @@ -0,0 +1,84 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +
> +#define MT8195_PLL_FMAX                (3800UL * MHZ)
> +#define MT8195_PLL_FMIN                (1500UL * MHZ)
> +#define MT8195_INTEGER_BITS    8
> +
> +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags,      \
> +                       _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift,    \
> +                       _tuner_reg, _tuner_en_reg, _tuner_en_bit,       \
> +                       _pcw_reg, _pcw_shift, _pcw_chg_reg,                             \
> +                       _en_reg, _pll_en_bit) {                                 \

Some of these fields are always set to zero in this driver. Either they
use the same value, or it means the particular function is not supported
in the hardware.

You could move the fixed value for unsupported functions, such as rst_bar_mask,
or even all common values, into the macro to simplify the macro argument list.
And if you do so, please also add comments explaining which values are shared,
and why they can be shared.

I believe the same could also be done for the APLL driver.

> +               .id = _id,                                              \
> +               .name = _name,                                          \
> +               .reg = _reg,                                            \
> +               .pwr_reg = _pwr_reg,                                    \
> +               .en_mask = _en_mask,                                    \
> +               .flags = _flags,                                        \
> +               .rst_bar_mask = _rst_bar_mask,                          \
> +               .fmax = MT8195_PLL_FMAX,                                \
> +               .fmin = MT8195_PLL_FMIN,                                \
> +               .pcwbits = _pcwbits,                                    \
> +               .pcwibits = MT8195_INTEGER_BITS,                        \
> +               .pd_reg = _pd_reg,                                      \
> +               .pd_shift = _pd_shift,                                  \
> +               .tuner_reg = _tuner_reg,                                \
> +               .tuner_en_reg = _tuner_en_reg,                          \
> +               .tuner_en_bit = _tuner_en_bit,                          \
> +               .pcw_reg = _pcw_reg,                                    \
> +               .pcw_shift = _pcw_shift,                                \
> +               .pcw_chg_reg = _pcw_chg_reg,                            \
> +               .en_reg = _en_reg,                                      \
> +               .pll_en_bit = _pll_en_bit,                              \
> +       }
> +
> +static const struct mtk_pll_data apusys_plls[] = {
> +       PLL(CLK_APUSYS_PLL_APUPLL, "apusys_pll_apupll", 0x008, 0x014, 0,
> +               0, 0, 22, 0x00c, 24, 0, 0, 0, 0x00c, 0, 0, 0, 0),
> +       PLL(CLK_APUSYS_PLL_NPUPLL, "apusys_pll_npupll", 0x018, 0x024, 0,
> +               0, 0, 22, 0x01c, 24, 0, 0, 0, 0x01c, 0, 0, 0, 0),
> +       PLL(CLK_APUSYS_PLL_APUPLL1, "apusys_pll_apupll1", 0x028, 0x034, 0,
> +               0, 0, 22, 0x02c, 24, 0, 0, 0, 0x02c, 0, 0, 0, 0),
> +       PLL(CLK_APUSYS_PLL_APUPLL2, "apusys_pll_apupll2", 0x038, 0x044, 0,
> +               0, 0, 22, 0x03c, 24, 0, 0, 0, 0x03c, 0, 0, 0, 0),

The datasheet doesn't provide names for these clocks. The values here look
correct though.

> +};
> +
> +static int clk_mt8195_apusys_pll_probe(struct platform_device *pdev)
> +{
> +       struct clk_onecell_data *clk_data;
> +       struct device_node *node = pdev->dev.of_node;
> +
> +       clk_data = mtk_alloc_clk_data(CLK_APUSYS_PLL_NR_CLK);
> +       if (!clk_data)
> +               return -ENOMEM;
> +
> +       mtk_clk_register_plls(node, apusys_plls, ARRAY_SIZE(apusys_plls), clk_data);
> +
> +       return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> +static const struct of_device_id of_match_clk_mt8195_apusys_pll[] = {
> +       { .compatible = "mediatek,mt8195-apusys_pll", },
> +       {}
> +};
> +
> +static struct platform_driver clk_mt8195_apusys_pll_drv = {
> +       .probe = clk_mt8195_apusys_pll_probe,
> +       .driver = {
> +               .name = "clk-mt8195-apusys_pll",
> +               .of_match_table = of_match_clk_mt8195_apusys_pll,
> +       },
> +};
> +

The general comments from the other patches apply as well


Regards
ChenYu


> +builtin_platform_driver(clk_mt8195_apusys_pll_drv);
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock
  2021-06-16 22:47 ` [PATCH 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock Chun-Jie Chen
  2021-06-24 21:21   ` Rob Herring
@ 2021-07-12  9:32   ` Chen-Yu Tsai
  1 sibling, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-12  9:32 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

Hi,

On Thu, Jun 17, 2021 at 6:49 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> This patch adds the new binding documentation for system clock
> and functional clock on Mediatek MT8195.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  .../arm/mediatek/mediatek,mt8195-clock.yaml   | 287 ++++++++++++++++++
>  .../mediatek/mediatek,mt8195-sys-clock.yaml   |  66 ++++
>  2 files changed, 353 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
>  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> new file mode 100644
> index 000000000000..21554b3515cf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> @@ -0,0 +1,287 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: MediaTek Functional Clock Controller for MT8195
> +
> +maintainers:
> +  - Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +description:
> +  The Mediatek functional clock controller provides various clocks on MT8195.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - enum:
> +              - mediatek,mt8195-nnasys
> +              - mediatek,mt8195-scp_adsp
> +              - mediatek,mt8195-audsys
> +              - mediatek,mt8195-audsys_src
> +              - mediatek,mt8195-imp_iic_wrap_s
> +              - mediatek,mt8195-imp_iic_wrap_w
> +              - mediatek,mt8195-mfgcfg
> +              - mediatek,mt8195-vppsys0
> +              - mediatek,mt8195-wpesys
> +              - mediatek,mt8195-wpesys_vpp0
> +              - mediatek,mt8195-wpesys_vpp1
> +              - mediatek,mt8195-vppsys1
> +              - mediatek,mt8195-imgsys
> +              - mediatek,mt8195-imgsys1_dip_top
> +              - mediatek,mt8195-imgsys1_dip_nr
> +              - mediatek,mt8195-imgsys1_wpe
> +              - mediatek,mt8195-ipesys
> +              - mediatek,mt8195-camsys
> +              - mediatek,mt8195-camsys_rawa
> +              - mediatek,mt8195-camsys_yuva
> +              - mediatek,mt8195-camsys_rawb
> +              - mediatek,mt8195-camsys_yuvb
> +              - mediatek,mt8195-camsys_mraw
> +              - mediatek,mt8195-ccusys
> +              - mediatek,mt8195-vdecsys_soc
> +              - mediatek,mt8195-vdecsys
> +              - mediatek,mt8195-vdecsys_core1
> +              - mediatek,mt8195-apusys_pll
> +              - mediatek,mt8195-vencsys
> +              - mediatek,mt8195-vencsys_core1
> +              - mediatek,mt8195-vdosys0
> +              - mediatek,mt8195-vdosys1
> +  reg:
> +    maxItems: 1
> +
> +  '#clock-cells':
> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +
> +additionalProperties: false

I think this really needs to describe some of the clock relations
between the various clock controllers. For example, both
"mediatek,mt8195-imp_iic_wrap_s" and "mediatek,mt8195-imp_iic_wrap_w"
take the CLK_TOP_I2C_SEL clock from "mediatek,mt8195-topckgen",
but it is not described.

> +
> +examples:
> +  - |
> +    nnasys: clock-controller@10211000 {
> +        compatible = "mediatek,mt8195-nnasys";
> +        reg = <0x10211000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    scp_adsp: clock-controller@10720000 {
> +        compatible = "mediatek,mt8195-scp_adsp";
> +        reg = <0x10720000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    audsys: clock-controller@10890000 {
> +        compatible = "mediatek,mt8195-audsys";
> +        reg = <0x10890000 0x10000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    audsys_src: clock-controller@108a0000 {
> +        compatible = "mediatek,mt8195-audsys_src";
> +        reg = <0x108a0000 0x2000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    imp_iic_wrap_s: clock-controller@11d03000 {
> +        compatible = "mediatek,mt8195-imp_iic_wrap_s";
> +        reg = <0x11d03000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    imp_iic_wrap_w: clock-controller@11e05000 {
> +        compatible = "mediatek,mt8195-imp_iic_wrap_w";
> +        reg = <0x11e05000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    mfgcfg: clock-controller@13fbf000 {
> +        compatible = "mediatek,mt8195-mfgcfg";
> +        reg = <0x13fbf000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    vppsys0: clock-controller@14000000 {
> +        compatible = "mediatek,mt8195-vppsys0";
> +        reg = <0x14000000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    wpesys: clock-controller@14e00000 {
> +        compatible = "mediatek,mt8195-wpesys";
> +        reg = <0x14e00000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    wpesys_vpp0: clock-controller@14e02000 {
> +        compatible = "mediatek,mt8195-wpesys_vpp0";
> +        reg = <0x14e02000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    wpesys_vpp1: clock-controller@14e03000 {
> +        compatible = "mediatek,mt8195-wpesys_vpp1";
> +        reg = <0x14e03000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    vppsys1: clock-controller@14f00000 {
> +        compatible = "mediatek,mt8195-vppsys1";
> +        reg = <0x14f00000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    imgsys: clock-controller@15000000 {
> +        compatible = "mediatek,mt8195-imgsys";
> +        reg = <0x15000000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    imgsys1_dip_top: clock-controller@15110000 {
> +        compatible = "mediatek,mt8195-imgsys1_dip_top";
> +        reg = <0x15110000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    imgsys1_dip_nr: clock-controller@15130000 {
> +        compatible = "mediatek,mt8195-imgsys1_dip_nr";
> +        reg = <0x15130000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    imgsys1_wpe: clock-controller@15220000 {
> +        compatible = "mediatek,mt8195-imgsys1_wpe";
> +        reg = <0x15220000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    ipesys: clock-controller@15330000 {
> +        compatible = "mediatek,mt8195-ipesys";
> +        reg = <0x15330000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    camsys: clock-controller@16000000 {
> +        compatible = "mediatek,mt8195-camsys";
> +        reg = <0x16000000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    camsys_rawa: clock-controller@1604f000 {
> +        compatible = "mediatek,mt8195-camsys_rawa";
> +        reg = <0x1604f000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    camsys_yuva: clock-controller@1606f000 {
> +        compatible = "mediatek,mt8195-camsys_yuva";
> +        reg = <0x1606f000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    camsys_rawb: clock-controller@1608f000 {
> +        compatible = "mediatek,mt8195-camsys_rawb";
> +        reg = <0x1608f000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    camsys_yuvb: clock-controller@160af000 {
> +        compatible = "mediatek,mt8195-camsys_yuvb";
> +        reg = <0x160af000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    camsys_mraw: clock-controller@16140000 {
> +        compatible = "mediatek,mt8195-camsys_mraw";
> +        reg = <0x16140000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    ccusys: clock-controller@17200000 {
> +        compatible = "mediatek,mt8195-ccusys";
> +        reg = <0x17200000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    vdecsys_soc: clock-controller@1800f000 {
> +        compatible = "mediatek,mt8195-vdecsys_soc";
> +        reg = <0x1800f000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    vdecsys: clock-controller@1802f000 {
> +        compatible = "mediatek,mt8195-vdecsys";
> +        reg = <0x1802f000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    vdecsys_core1: clock-controller@1803f000 {
> +        compatible = "mediatek,mt8195-vdecsys_core1";
> +        reg = <0x1803f000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    apusys_pll: clock-controller@190f3000 {
> +        compatible = "mediatek,mt8195-apusys_pll";
> +        reg = <0x190f3000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    vencsys: clock-controller@1a000000 {
> +        compatible = "mediatek,mt8195-vencsys";
> +        reg = <0x1a000000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    vencsys_core1: clock-controller@1b000000 {
> +        compatible = "mediatek,mt8195-vencsys_core1";
> +        reg = <0x1b000000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    vdosys0: clock-controller@1c01a000 {
> +        compatible = "mediatek,mt8195-vdosys0";
> +        reg = <0x1c01a000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    vdosys1: clock-controller@1c100000 {
> +        compatible = "mediatek,mt8195-vdosys1";
> +        reg = <0x1c100000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
> new file mode 100644
> index 000000000000..ea379452ba91
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
> @@ -0,0 +1,66 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: MediaTek System Clock Controller for MT8195
> +
> +maintainers:
> +  - Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +description:
> +  The Mediatek system clock controller provides various clocks and system configuration
> +  like reset and bus protection on MT8195.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - enum:
> +              - mediatek,mt8195-topckgen
> +              - mediatek,mt8195-infracfg_ao
> +              - mediatek,mt8195-apmixedsys
> +              - mediatek,mt8195-pericfg_ao
> +          - const: syscon
> +
> +  reg:
> +    maxItems: 1
> +
> +  '#clock-cells':
> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +
> +additionalProperties: false

Same thing for "mediatek,mt8195-topckgen". This clock controller takes
a bunch of the PLLs from "mediatek,mt8195-apmixedsys" as well as an
external oscillator, and muxes and divides them to produce various
clock ouptuts. These clock parents are not described.

In the external oscillator's case, the oscillator is described in the
device tree, but the clock parent relationship is described in the
clock driver in this series with a hard-coded clock name.

This really applies to all clock controllers. Unless it includes some
internal oscillator, it will always have some clock input used to produce
other clock outputs.


Regards
ChenYu

> +
> +examples:
> +  - |
> +    topckgen: syscon@10000000 {
> +        compatible = "mediatek,mt8195-topckgen", "syscon";
> +        reg = <0x10000000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    infracfg_ao: syscon@10001000 {
> +        compatible = "mediatek,mt8195-infracfg_ao", "syscon";
> +        reg = <0x10001000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    apmixedsys: syscon@1000c000 {
> +        compatible = "mediatek,mt8195-apmixedsys", "syscon";
> +        reg = <0x1000c000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> +
> +  - |
> +    pericfg_ao: syscon@11003000 {
> +        compatible = "mediatek,mt8195-pericfg_ao", "syscon";
> +        reg = <0x11003000 0x1000>;
> +        #clock-cells = <1>;
> +    };
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 02/22] clk: mediatek: Add dt-bindings of MT8195 clocks
  2021-06-16 22:47 ` [PATCH 02/22] clk: mediatek: Add dt-bindings of MT8195 clocks Chun-Jie Chen
  2021-06-24 21:22   ` Rob Herring
@ 2021-07-12  9:37   ` Chen-Yu Tsai
  1 sibling, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-12  9:37 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

Hi,

On Thu, Jun 17, 2021 at 7:02 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 clock dt-bindings, include topckgen, apmixedsys,
> infracfg_ao, pericfg_ao and subsystem clocks.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  include/dt-bindings/clock/mt8195-clk.h | 989 +++++++++++++++++++++++++
>  1 file changed, 989 insertions(+)

This is a really long list. I don't think all of them need to be exposed,
especially the intermediate ones in TOPCKGEN. In such cases the not-to-be-
exposed clock indices could be moved to a header file in the driver directory,
or simply left out.

The Allwinner/sunxi-ng drivers do the former while the Rockchip drivers do
the latter. The Mediatek clock drivers are more similar in structure and
design to the Rockchip ones.


Regards
ChenYu

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 04/22] clk: mediatek: Add MT8195 basic clocks support
       [not found]     ` <1626913060.1546.4.camel@mtksdaap41>
@ 2021-07-22  7:44       ` Chen-Yu Tsai
  2021-08-11  4:31         ` Chun-Jie Chen
  0 siblings, 1 reply; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-07-22  7:44 UTC (permalink / raw)
  To: Chun-Jie Chen
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group

Hi,

It seems your reply included HTML, which means that it never reached
the mailing lists. Please always use plaintext only.

On Thu, Jul 22, 2021 at 08:17:40AM +0800, Chun-Jie Chen wrote:
> On Fri, 2021-07-02 at 19:44 +0800, Chen-Yu Tsai wrote:
> > > On Thu, Jun 17, 2021 at 7:05 AM Chun-Jie Chen
> > > <chun-jie.chen@mediatek.com> wrote:
> >
> > > > >
> > >
> > > > > Add MT8195 basic clock providers, include topckgen, apmixedsys,
> > > > > infracfg_ao and pericfg_ao.
> > > > >
> > >
> > > > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > > > > ---
> > > > >  drivers/clk/mediatek/Kconfig      |    8 +
> > > > >  drivers/clk/mediatek/Makefile     |    1 +
> > > > >  drivers/clk/mediatek/clk-mt8195.c | 1958
> > > > > +++++++++++++++++++++++++++++
> > > > >  3 files changed, 1967 insertions(+)
> > > > >  create mode 100644 drivers/clk/mediatek/clk-mt8195.c
> > > > >
> > >
> > > > > diff --git a/drivers/clk/mediatek/Kconfig
> > > > > b/drivers/clk/mediatek/Kconfig
> > > > > index 576babd86f98..6707aba3d500 100644
> > > > > --- a/drivers/clk/mediatek/Kconfig
> > > > > +++ b/drivers/clk/mediatek/Kconfig
> > > > > @@ -580,6 +580,14 @@ config COMMON_CLK_MT8192_VENCSYS
> > > > >         help
> > > > >           This driver supports MediaTek MT8192 vencsys clocks.
> > > > >
> > >
> > > > > +config COMMON_CLK_MT8195
> > > > > +       bool "Clock driver for MediaTek MT8195"
> > > > > +       depends on ARM64 || COMPILE_TEST
> > > > > +       select COMMON_CLK_MEDIATEK
> > > > > +       default ARM64
> > > > > +       help
> > > > > +         This driver supports MediaTek MT8195 basic clocks.
> > > > > +
> > > > >  config COMMON_CLK_MT8516
> > > > >         bool "Clock driver for MediaTek MT8516"
> > > > >         depends on ARCH_MEDIATEK || COMPILE_TEST
> > > > > diff --git a/drivers/clk/mediatek/Makefile
> > > > > b/drivers/clk/mediatek/Makefile
> > > > > index 15bc045f0b71..f8002d8966e1 100644
> > > > > --- a/drivers/clk/mediatek/Makefile
> > > > > +++ b/drivers/clk/mediatek/Makefile
> > > > > @@ -80,5 +80,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk-
> > > > > mt8192-msdc.o
> > > > >  obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) +=
> > > clk-mt8192-scp_adsp.o
> > > > >  obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
> > > > >  obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
> > > > > +obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195.o
> > > > >  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
> > > > >  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> > > > > diff --git a/drivers/clk/mediatek/clk-mt8195.c
> > > > > b/drivers/clk/mediatek/clk-mt8195.c
> > > > > new file mode 100644
> > > > > index 000000000000..aea9ebe4c051
> > > > > --- /dev/null
> > > > > +++ b/drivers/clk/mediatek/clk-mt8195.c
> > > > > @@ -0,0 +1,1958 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0-only
> > > > > +//
> > > > > +// Copyright (c) 2021 MediaTek Inc.
> > > > > +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > > > > +
> > > > > +#include <linux/clk.h>
> > > > > +#include <linux/delay.h>
> > > > > +#include <linux/mfd/syscon.h>
> > > > > +#include <linux/of.h>
> > > > > +#include <linux/of_address.h>
> > > > > +#include <linux/of_device.h>
> > > > > +#include <linux/platform_device.h>
> > > > > +#include <linux/slab.h>
> > > > > +
> > > > > +#include "clk-mtk.h"
> > > > > +#include "clk-mux.h"
> > > > > +#include "clk-gate.h"
> > > > > +
> > > > > +#include <dt-bindings/clock/mt8195-clk.h>
> > > > > +
> > > > > +static DEFINE_SPINLOCK(mt8195_clk_lock);
> > > > > +
> > > > > +static const struct mtk_fixed_clk top_fixed_clks[] = {
> > > > > +       FIXED_CLK(CLK_TOP_IN_DGI, "in_dgi", NULL, 165000000),
> > > > > +       FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 248000000),
> > > > > +       FIXED_CLK(CLK_TOP_ULPOSC2, "ulposc2", NULL, 326000000),
> > > > > +       FIXED_CLK(CLK_TOP_MEM_466M, "mem_466m", NULL,
> > > 533000000),
> > > > > +       FIXED_CLK(CLK_TOP_MPHONE_SLAVE_B, "mphone_slave_b",
> > > NULL,
> > > > > 49152000),
> > > > > +       FIXED_CLK(CLK_TOP_PEXTP_PIPE, "pextp_pipe", NULL,
> > > > > 250000000),
> > > > > +       FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL, "ufs_rx_symbol", NULL,
> > > > > 166000000),
> > > > > +       FIXED_CLK(CLK_TOP_UFS_TX_SYMBOL, "ufs_tx_symbol", NULL,
> > > > > 166000000),
> > > > > +       FIXED_CLK(CLK_TOP_SSUSB_U3PHY_P1_P_P0,
> > > > > "ssusb_u3phy_p1_p_p0", NULL, 131000000),
> > > > > +       FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL1, "ufs_rx_symbol1",
> > > NULL,
> > > > > 166000000),
> > > > > +       FIXED_CLK(CLK_TOP_FPC, "fpc", NULL, 50000000),
> > > > > +       FIXED_CLK(CLK_TOP_HDMIRX_P, "hdmirx_p", NULL,
> > > 594000000),
> >
> > >
> >
> > > I assume these are fixed PLLs? They should have inputs (parents).
> > >
> >
> > > Moreover, at least ULPOSC and ULPOSC2 look like they are in
> > > APMIXEDSYS
> > >
> >
>
> The clock in top_fixed_clks is special clock that generated from the
> specific hardware block, not PLLs in APMIXEDSYS. ULPOSC and ULPOSC2 has
> configuration register in APMIXEDSYS, but their clock source are not
> "clk26m" (other plls in APMIXEDSYS in is generated from "clk26m")

I see. Surely they have some input though. It would be nice to be able
to have them described.

> > > > > +};T
> > > > > +
> > > > > +static const struct mtk_fixed_factor top_early_divs[] = {
> > > > > +       FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
> > > > > +};
> > > > > +
> > > > > +static const struct mtk_fixed_factor top_divs[] = {
> > > > > +       FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m", 1,
> > > 52),
> > > > > +       FACTOR(CLK_TOP_IN_DGI_D2, "in_dgi_d2", "in_dgi", 1, 2),
> > > > > +       FACTOR(CLK_TOP_IN_DGI_D4, "in_dgi_d4", "in_dgi", 1, 4),
> > > > > +       FACTOR(CLK_TOP_IN_DGI_D6, "in_dgi_d6", "in_dgi", 1, 6),
> > > > > +       FACTOR(CLK_TOP_IN_DGI_D8, "in_dgi_d8", "in_dgi", 1, 8),
> > > > > +       FACTOR(CLK_TOP_MFGPLL_OPP, "mfgpll_opp", "mfgpll", 1,
> > > 1),
> > > > > +       FACTOR(CLK_TOP_MAINPLL, "mainpll_ck", "mainpll", 1, 1),
> >
> > >
> >
> > > Why are this and other 1:1 factor clks needed? They look like
> > > placeholders.
> > > Please remove them.
>
>
>
> These 1:1 factors make more readable between dividers. For example,
> CLK_APMIXED_MAINPLL and CLK_TOP_MAINPLL_D3 is not easy to see the
> relation, but CLK_TOP_MAINPLL and CLK_TOP_MAINPLL_D3 is more clear to
> see the relation.

If the clocks are named appropriately, it should be clear that "mainpll_dX"
is derived from "mainpll". We really don't need an extra "mainpll_ck" in
between.

The only thing gained here is having the parent clock in the same driver.
But that is only a problem because we are directly using global clock names
for parent names. This isn't the preferred way for clock parenting.

For proper parenting, the driver should be using `struct clk_parent_data`
if possible, or using of_clk_get_parent_name() or of_clk_get_hw() manually
to get the parent's global name or a reference to it. This is something
the clk drivers should slowly be converted to doing.

I'm not saying we should do everything now, but we can start by getting
rid of some of the excess baggage.

[...]

> > > > > +static const char * const dsp7_parents[] = {
> > > > > +       "clk26m",
> > > > > +       "univpll_d6_d2",
> > > > > +       "univpll_d4_d2",
> > > > > +       "univpll_d5",
> > > > > +       "univpll_d4",
> > > > > +       "mmpll_d4",
> > > > > +       "mainpll_d3",
> > > > > +       "univpll_d3"
> > > > > +};
> >
> > >
> >
> > > If dsp~dsp7_parents are all the same, please merge them and share
> > one
> > > instance. And since they are located a bit far from the clock
> > > definitions
> > > in this file, please add comments describing which clocks share the
> > > same
> > > set of parents.
> > >
> >
>
> I will merge it if they can share the same parent source data (include
> you mention below), thanks for your comment.

Great!

[...]

Tip: You can trim out portions of the original email from your reply, like
what I did here, so that the emails are shorter. Keeping just the bits that
are relevant to the discussion is better for the reader. In cases here a
lot of it are related cases, you could keep just the one nearest to your
reply.

> > > > > +static const char * const spinor_parents[] = {
> > > > > +       "clk26m",
> >
> > >
> >
> > > Datasheet says first parent is "univpll_d5_d8". Please check with
> > > hardware
> > > engineers. If the datasheet is wrong please add a comment saying so.
> > >
> >
> >
> > > > > +       "clk26m_d2",
> > > > > +       "mainpll_d7_d8",
> > > > > +       "univpll_d6_d8"
> > > > > +};
> > > > > +
>
> The parent source here is correct, but not update to the latest in
> datasheet.

For future reference, could you leave a comment stating that the datasheet
has not been updated then? Please include the version of the datasheet.

> > > > > +static const char * const dvio_dgi_ref_parents[] = {
> > > > > +       "clk26m",
> > > > > +       "in_dgi",
> > > > > +       "in_dgi_d2",
> > > > > +       "in_dgi_d4",
> > > > > +       "in_dgi_d6",
> > > > > +       "in_dgi_d8",
> > > > > +       "mmpll_d4_d4"
> > > > > +};
> > > > > +
> > > > > +static const char * const srck_parents[] = {
> > > > > +       "ulposc_d10",
> > > > > +       "clk26m"
> > > > > +};
> > > > > +
> > > > > +static const char * const rsvd1_parents[] = {
> > > > > +       "clk26m",
> > > > > +       "mainpll_d4_d4",
> > > > > +       "mainpll_d5_d4",
> > > > > +       "mainpll_d6_d4",
> > > > > +       "mainpll_d7_d4",
> > > > > +       "univpll_d6_d4",
> >
> > >
> >
> > > These are completely different from the datasheet. Please check.
> > >
> >
> >
> > > > > +       "ulposc",
> > > > > +       "ulposc2"
> > > > > +};
> > > > > +
>
> The parent source here is correct, but not update to the latest in
> datasheet.

Same for this one.

> > > > > +static const char * const mfg_fast_parents[] = {
> > > > > +       "mfg_sel",
> > > > > +       "mfgpll_opp"
> > > > > +};
> > > > > +
> > > > > +static const struct mtk_mux top_mtk_muxes[] = {
> > > > > +       /* CLK_CFG_0 */
> > > > > +       MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel",
> >
> > >
> >
> > > Please drop the "_sel" suffix from the clock names. It would have
> > > made
> > > sense if this were purely a mux, and there was another clock gate.
> > > But
> > > since the driver combines the two components into one
> > representation,
> > > please just drop the suffix that implies just a mux. This goes for
> > > all
> > > clocks in the series and also the macro bindings.
> >
>
>
>
> If we move the "_sel" suffix from clock names, it's hard to represent
> this mux with gate control. Do you think revise it to "XXX_sel_gate" in
> CCF name but keep the binding name because change the binding name need
> all CCF consumer changes.

Please elaborate. Does the "type" of the clock matter? All that is
really needed is that the name is unique, matches the datasheet more or
less, and describes the usage or purpose of the clock.

For example, on Allwinner sunxi platforms, we don't include the type
of the clock in the clock names. Only the base clock name is used.
That is because the clocks are modeled as composite-ish clocks, so
only one clock is needed to describe a full mux+divider+gate.

On other platforms, the clock driver deliberately uses base clock types,
mux, div, and gate, to build up a representation of the full clock unit.
In these cases, we end up with "XXX_mux", "XXX_div", and "XXX_gate".

Since the Mediatek clock driver is more like the first case, I would
prefer to see clock names with just the base name, and none of the
typing.

And regarding binding names, please change them as well. Right now the
only place that needs to be changed are the header files. This is the
time to get them right.

> > > > > +               axi_parents, 0x020, 0x024, 0x028, 0, 3, 7, 0x04,
> > > 0,
> > > > > CLK_IS_CRITICAL),
> > > > > +       MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel",
> > > > > +               spm_parents, 0x020, 0x024, 0x028, 8, 2, 15,
> > > 0x04,
> > > > > 1, CLK_IS_CRITICAL),
> >
> > >
> >
> > > Where is the SCP clock?
>
>
>
> Because SCP is always on and no other clock gates need to reference it,
> so move it.

Please add a comment as a placeholder then. The comment could simply
state "clock is always on and should not be handled by Linux".

[...]

> > > > > +       /* CLK_CFG_11 */
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SEL, "usb_sel",
> >
> > >
> >
> > > The datasheet lists these as "usb_top" and "usb_top_Xp". Please keep
> > > the name
> > > the same as the datasheet so it is easy to search for. Also note the
> > > discrepency
> > > between the macro name and the clock name. Same goes for the three
> > > other USB
> > > clocks.
>
>
>
> Do you think revise the name the same as datasheet in CCF name but keep
> binding name?

Please have them match each other. The whole point of keeping names
consistent is to be able to search for them easily.

> > >
> >
> >
> > > > > +               usb_parents, 0x0A4, 0x0A8, 0x0AC, 0, 2, 7, 0x08,
> > > > > 12),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL,
> > > > > "ssusb_xhci_sel",
> > > > > +               ssusb_xhci_parents, 0x0A4, 0x0A8, 0x0AC, 8, 2,
> > > 15,
> > > > > 0x08, 13),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_1P_SEL, "usb_1p_sel",
> > > > > +               usb_1p_parents, 0x0A4, 0x0A8, 0x0AC, 16, 2, 23,
> > > > > 0x08, 14),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_1P_SEL,
> > > > > "ssusb_xhci_1p_sel",
> > > > > +               ssusb_xhci_1p_parents, 0x0A4, 0x0A8, 0x0AC, 24,
> > > 2,
> > > > > 31, 0x08, 15),
> > > > > +       /* CLK_CFG_12 */
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_2P_SEL, "usb_2p_sel",
> > > > > +               usb_2p_parents, 0x0B0, 0x0B4, 0x0B8, 0, 2, 7,
> > > 0x08,
> > > > > 16),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P_SEL,
> > > > > "ssusb_xhci_2p_sel",
> > > > > +               ssusb_xhci_2p_parents, 0x0B0, 0x0B4, 0x0B8, 8,
> > > 2,
> > > > > 15, 0x08, 17),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_3P_SEL, "usb_3p_sel",
> > > > > +               usb_3p_parents, 0x0B0, 0x0B4, 0x0B8, 16, 2, 23,
> > > > > 0x08, 18),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P_SEL,
> > > > > "ssusb_xhci_3p_sel",
> > > > > +               ssusb_xhci_3p_parents, 0x0B0, 0x0B4, 0x0B8, 24,
> > > 2,
> > > > > 31, 0x08, 19),
> > > > > +       /* CLK_CFG_13 */
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel",
> > > > > +               i2c_parents, 0x0BC, 0x0C0, 0x0C4, 0, 2, 7, 0x08,
> > > > > 20),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel",
> > > > > +               seninf_parents, 0x0BC, 0x0C0, 0x0C4, 8, 3, 15,
> > > > > 0x08, 21),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL,
> > > "seninf1_sel",
> > > > > +               seninf1_parents, 0x0BC, 0x0C0, 0x0C4, 16, 3, 23,
> > > > > 0x08, 22),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2_SEL,
> > > "seninf2_sel",
> > > > > +               seninf2_parents, 0x0BC, 0x0C0, 0x0C4, 24, 3, 31,
> > > > > 0x08, 23),
> > > > > +       /* CLK_CFG_14 */
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3_SEL,
> > > "seninf3_sel",
> > > > > +               seninf3_parents, 0x0C8, 0x0CC, 0x0D0, 0, 3, 7,
> > > > > 0x08, 24),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, "gcpu_sel",
> > > > > +               gcpu_parents, 0x0C8, 0x0CC, 0x0D0, 8, 3, 15,
> > > 0x08,
> > > > > 25),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel",
> > > > > +               dxcc_parents, 0x0C8, 0x0CC, 0x0D0, 16, 2, 23,
> > > 0x08,
> > > > > 26),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_SEL, "dpmaif_sel",
> > > > > +               dpmaif_parents, 0x0C8, 0x0CC, 0x0D0, 24, 3, 31,
> > > > > 0x08, 27),
> > > > > +       /* CLK_CFG_15 */
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL,
> > > > > "aes_ufsfde_sel",
> > > > > +               aes_ufsfde_parents, 0x0D4, 0x0D8, 0x0DC, 0, 3,
> > > 7,
> > > > > 0x08, 28),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_SEL, "ufs_sel",
> > > > > +               ufs_parents, 0x0D4, 0x0D8, 0x0DC, 8, 3, 15,
> > > 0x08,
> > > > > 29),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_TICK1US_SEL,
> > > > > "ufs_tick1us_sel",
> > > > > +               ufs_tick1us_parents, 0x0D4, 0x0D8, 0x0DC, 16, 1,
> > > > > 23, 0x08, 30),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_MP_SAP_SEL,
> > > > > "ufs_mp_sap_sel",
> > > > > +               ufs_mp_sap_parents, 0x0D4, 0x0D8, 0x0DC, 24, 1,
> > > 31,
> > > > > 0x08, 31),
> > > > > +       /* CLK_CFG_16 */
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel",
> > > > > +               venc_parents, 0x0E0, 0x0E4, 0x0E8, 0, 4, 7,
> > > 0x0C,
> > > > > 0),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel",
> > > > > +               vdec_parents, 0x0E0, 0x0E4, 0x0E8, 8, 4, 15,
> > > 0x0C,
> > > > > 1),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel",
> > > > > +               pwm_parents, 0x0E0, 0x0E4, 0x0E8, 16, 1, 23,
> > > 0x0C,
> > > > > 2),
> >
> > >
> >
> > > MCU clock? Not sure what it's supposed to be called since the naming
> > > has a
> > > slightly different format.
> > >
> >
> > > If you are skipping clocks, please leave a comment in the list
> > > explaining
> > > why.
> > >
> >
> > "mcupm" is another micro-processor and is always on, and no others
> > clock gates need to reference it, so remove it.

Please add a comment, just like in the SCP clock case.

> > > > > +       /* CLK_CFG_17 */
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST_SEL,
> > > > > "spmi_p_mst_sel",
> > > > > +               spmi_p_mst_parents, 0x0EC, 0x0F0, 0x0F4, 0, 4,
> > > 7,
> > > > > 0x0C, 4),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST_SEL,
> > > > > "spmi_m_mst_sel",
> > > > > +               spmi_m_mst_parents, 0x0EC, 0x0F0, 0x0F4, 8, 4,
> > > 15,
> > > > > 0x0C, 5),
> >
> > >
> >
> > > DVFSRC clock?
> > >
> >
> > "DVFSRC" IP block is always on  and no others clock gates need to
> > reference it, so remove it.

This one as well.

[...]

> > > > > +       /* CLK_CFG_24 */
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5_SEL, "apll5_sel",
> > > > > +               apll5_parents, 0x0140, 0x0144, 0x0148, 0, 1, 7,
> > > > > 0x010, 0),
> >
> > >
> >
> > > For the APLLs, you will need to differentiate them from the actual
> > > PLLs in
> > > the APMIXEDSYS block.
> > >
> >
> > APLLX providers more precise clock so it has more configuration
> > register, but it still has same control flow like other PLLs in
> > APMIXEDSYS.

I think what I meant was, because I asked to remove the "_sel" suffix,
the global clock names here now collide with the ones in APMIXEDSYS.
So what I was asking was the names here need to be changed, maybe to
something like "top_apllX".

> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1_M_SEL,
> > > "i2so1_m_sel",
> > > > > +               i2so1_m_parents, 0x0140, 0x0144, 0x0148, 8, 3,
> > > 15,
> > > > > 0x010, 1),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2_M_SEL,
> > > "i2so2_m_sel",
> > > > > +               i2so2_m_parents, 0x0140, 0x0144, 0x0148, 16, 3,
> > > 23,
> > > > > 0x010, 2),
> >
> > >
> >
> > > I2SO4_M?
> > >
> >
> >
> > > > > +       /* CLK_CFG_25 */
> >
> > >
> >
> > > I2SO5_M?
> > >
> >
> >
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1_M_SEL,
> > > "i2si1_m_sel",
> > > > > +               i2si1_m_parents, 0x014C, 0x0150, 0x0154, 8, 3,
> > > 15,
> > > > > 0x010, 5),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2_M_SEL,
> > > "i2si2_m_sel",
> > > > > +               i2si2_m_parents, 0x014C, 0x0150, 0x0154, 16, 3,
> > > 23,
> > > > > 0x010, 6),
> >
> > >
> >
> > > I2SI4_M?
> > >
> >
> >
> > > > > +       /* CLK_CFG_26 */
> >
> > >
> >
> > > I2SI5_M?
> > >
> >
> > I2SO4/I2SO5/I2SI4_M/I2SI5_M is not used in MT8195, so remove it here.

Please add comments as placeholders for them. The comment could state
that the clock is unused in the hardware design, so it was skipped.

> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX_M_SEL, "dptx_m_sel",
> > > > > +               dptx_m_parents, 0x0158, 0x015C, 0x0160, 8, 3,
> > > 15,
> > > > > 0x010, 9),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC_SEL,
> > > "aud_iec_sel",
> > > > > +               aud_iec_parents, 0x0158, 0x015C, 0x0160, 16, 3,
> > > 23,
> > > > > 0x010, 10),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP_SEL,
> > > "a1sys_hp_sel",
> > > > > +               a1sys_hp_parents, 0x0158, 0x015C, 0x0160, 24, 1,
> > > > > 31, 0x010, 11),
> > > > > +       /* CLK_CFG_27 */
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS_SEL, "a2sys_sel",
> > > > > +               a2sys_parents, 0x0164, 0x0168, 0x016C, 0, 1, 7,
> > > > > 0x010, 12),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS_SEL, "a3sys_sel",
> > > > > +               a3sys_parents, 0x0164, 0x0168, 0x016C, 8, 3, 15,
> > > > > 0x010, 13),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS_SEL, "a4sys_sel",
> > > > > +               a4sys_parents, 0x0164, 0x0168, 0x016C, 16, 3,
> > > 23,
> > > > > 0x010, 14),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_B_SEL,
> > > "spinfi_b_sel",
> > > > > +               spinfi_b_parents, 0x0164, 0x0168, 0x016C, 24, 3,
> > > > > 31, 0x010, 15),
> > > > > +       /* CLK_CFG_28 */
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel",
> > > > > +               nfi1x_parents, 0x0170, 0x0174, 0x0178, 0, 3, 7,
> > > > > 0x010, 16),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, "ecc_sel",
> > > > > +               ecc_parents, 0x0170, 0x0174, 0x0178, 8, 3, 15,
> > > > > 0x010, 17),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS_SEL,
> > > > > "audio_local_bus_sel",
> > > > > +               audio_local_bus_parents, 0x0170, 0x0174, 0x0178,
> > > > > 16, 4, 23, 0x010, 18),
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR_SEL, "spinor_sel",
> > > > > +               spinor_parents, 0x0170, 0x0174, 0x0178, 24, 2,
> > > 31,
> > > > > 0x010, 19),
> > > > > +       /* CLK_CFG_29 */
> > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DVIO_DGI_REF_SEL,
> > > > > "dvio_dgi_ref_sel",
> > > > > +               dvio_dgi_ref_parents, 0x017C, 0x0180, 0x0184, 0,
> > > 3,
> > > > > 7, 0x010, 20),
> >
> > >
> >
> > > ULPOSC and ULPOSC_CORE?
> > >
> >
>
>
>
> ULPOSC and ULPOSC_CORE is always on and no other clock gate needs to
> reference it, so just remove it.

Please add placeholder comments describing them, specifically why they
are missing from the driver. Are the clocks used at all in the hardware
design? If so then it might be better to add them to the clock driver.

Also, even if they, including SCP and MCU above, are always on, it might
still be nice to have driver support for them, just to be able to read
their state from Linux. We could have CLK_IS_CRITICAL set so they don't
get disabled, and CLK_GET_RATE_NOCACHE if the clocks are expected to be
changed by firmware running alongside of Linux.

> > > > > +       MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK_SEL,
> > > "srck_sel",
> > > > > +               srck_parents, 0x017C, 0x0180, 0x0184, 24, 1, 31,
> > > > > 0x010, 23, CLK_IS_CRITICAL),
> >
> > >
> >
> > > What happened to CLK_CFG_30~36?
> > >
> >
>
> The muxes in CLK_CFG_30 ~ 36 are not used, so just remove it from CCF.

Please add placeholder comments about them.

> > > > > +       /* CLK_CFG_37 */
> > > > > +       MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_RSVD1_SEL,
> > > "rsvd1_sel",
> > > > > +               rsvd1_parents, 0x01DC, 0x01E0, 0x01E4, 0, 3, 7,
> > > > > 0x014, 20, CLK_IS_CRITICAL),
> >
> > >
> >
> > > What about the other three?
> > >
> >
>
>
> "rsvd2" and "rsvd3" is not used, so remove it.

Same here.

To be honest, a "rsvd", which I interpret as "reserved", clock being
used seems kind of contradicting. Do we know what hardware is using
rsvd1?

> > > > > +};
> > > > > +
> > > > > +static struct mtk_composite top_muxes[] = {
> > > > > +       /* CLK_MISC_CFG_3 */
> > > > > +       MUX(CLK_TOP_MFG_FAST_SEL, "mfg_fast_sel",
> > > mfg_fast_parents,
> > > > > 0x0250, 8, 1),
> > > > > +};
> > > > > +
> > > > > +static const struct mtk_composite top_adj_divs[] = {
> > > > > +       DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0",
> > > "i2si1_m_sel",
> > > > > 0x0320, 0, 0x0328, 8, 0),
> > > > > +       DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1",
> > > "i2si2_m_sel",
> > > > > 0x0320, 1, 0x0328, 8, 8),
> > > > > +       DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2",
> > > "i2so1_m_sel",
> > > > > 0x0320, 2, 0x0328, 8, 16),
> > > > > +       DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3",
> > > "i2so2_m_sel",
> > > > > 0x0320, 3, 0x0328, 8, 24),
> > > > > +       DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4",
> > > "aud_iec_sel",
> > > > > 0x0320, 4, 0x0334, 8, 0),
> >
> > >
> >
> > > What about 5~8?
> > >
> >
> > div5 ~ 8 are not used in MT8195, so remove it.

Placeholder comments please.

[...]

> > > > > +static const struct mtk_gate_regs top0_cg_regs = {
> > > > > +       .set_ofs = 0x238,
> > > > > +       .clr_ofs = 0x238,
> > > > > +       .sta_ofs = 0x238,
> > > > > +};
> > > > > +
> > > > > +static const struct mtk_gate_regs top1_cg_regs = {
> > > > > +       .set_ofs = 0x250,
> > > > > +       .clr_ofs = 0x250,
> > > > > +       .sta_ofs = 0x250,
> > > > > +};
> > > > > +
> > > > > +#define GATE_TOP0_FLAGS(_id, _name, _parent, _shift,
> > > > > _flag)            \
> > > > > +       GATE_MTK_FLAGS(_id, _name, _parent, &top0_cg_regs,
> > > > > _shift,      \
> > > > > +               &mtk_clk_gate_ops_no_setclr_inv, _flag)
> > > > > +
> > > > > +#define GATE_TOP0(_id, _name, _parent,
> > > _shift)                 \
> > > > > +       GATE_TOP0_FLAGS(_id, _name, _parent, _shift, 0)
> > > > > +
> > > > > +#define GATE_TOP1(_id, _name, _parent,
> > > _shift)                 \
> > > > > +       GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift,
> > > > > &mtk_clk_gate_ops_no_setclr_inv)
> > > > > +
> > > > > +static const struct mtk_gate top_clks[] = {
> > > > > +       /* TOP0 */
> > > > > +       GATE_TOP0(CLK_TOP_CFG_VPP0, "cfg_vpp0", "vpp_sel", 0),
> > > > > +       GATE_TOP0(CLK_TOP_CFG_VPP1, "cfg_vpp1", "vpp_sel", 1),
> > > > > +       GATE_TOP0(CLK_TOP_CFG_VDO0, "cfg_vdo0", "vpp_sel", 2),
> > > > > +       GATE_TOP0(CLK_TOP_CFG_VDO1, "cfg_vdo1", "vpp_sel", 3),
> > > > > +       GATE_TOP0(CLK_TOP_CFG_UNIPLL_SES, "cfg_unipll_ses",
> > > > > "univpll_d2", 4),
> > > > > +       GATE_TOP0(CLK_TOP_CFG_26M_VPP0, "cfg_26m_vpp0",
> > > "clk26m",
> > > > > 5),
> > > > > +       GATE_TOP0(CLK_TOP_CFG_26M_VPP1, "cfg_26m_vpp1",
> > > "clk26m",
> > > > > 6),
> > > > > +       GATE_TOP0(CLK_TOP_CFG_26M_AUD, "cfg_26m_aud", "clk26m",
> > > 9),
> > > > > +       GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST, "cfg_axi_east",
> > > > > "axi_sel", 10, CLK_IS_CRITICAL),
> > > > > +       GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST_NORTH,
> > > > > "cfg_axi_east_north", "axi_sel", 11,
> > > > > +               CLK_IS_CRITICAL),
> > > > > +       GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_NORTH, "cfg_axi_north",
> > > > > "axi_sel", 12, CLK_IS_CRITICAL),
> > > > > +       GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_SOUTH, "cfg_axi_south",
> > > > > "axi_sel", 13, CLK_IS_CRITICAL),
> > > > > +       GATE_TOP0(CLK_TOP_CFG_EXT_TEST, "cfg_ext_test",
> > > > > "msdcpll_d2", 15),
> > > > > +       /* TOP1 */
> > > > > +       GATE_TOP1(CLK_TOP_SSUSB_REF, "ssusb_ref", "clk26m", 0),
> > > > > +       GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref",
> > > "clk26m",
> > > > > 1),
> > > > > +       GATE_TOP1(CLK_TOP_SSUSB_P1_REF, "ssusb_p1_ref",
> > > "clk26m",
> > > > > 2),
> > > > > +       GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, "ssusb_phy_p1_ref",
> > > > > "clk26m", 3),
> > > > > +       GATE_TOP1(CLK_TOP_SSUSB_P2_REF, "ssusb_p2_ref",
> > > "clk26m",
> > > > > 4),
> > > > > +       GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, "ssusb_phy_p2_ref",
> > > > > "clk26m", 5),
> > > > > +       GATE_TOP1(CLK_TOP_SSUSB_P3_REF, "ssusb_p3_ref",
> > > "clk26m",
> > > > > 6),
> > > > > +       GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, "ssusb_phy_p3_ref",
> > > > > "clk26m", 7),
> > > > > +};
> >
> > >
> >
> > > These should be grouped with the other TOPCKGEN clocks. Another
> > > reason to
> > > split this driver into multiple ones.
> > >
> >
>
>
>
> These clocks are "clock gate" in TOPCKGEN, so we separate the data of
> "clock gate" from "clock mux".

Right, but it gets really confusing when the driver is mixing clocks
from different clock controllers. Code that gets used together should
be grouped together. In this case, code for the same hardware block
should be grouped together. So please split the drivers up if they end
up being really big, and then group the remaining ones by hardware
block first, then type second.

> > > > > +
> > > > > +static const struct mtk_gate_regs apmixed_cg_regs = {
> > > > > +       .set_ofs = 0x8,
> > > > > +       .clr_ofs = 0x8,
> > > > > +       .sta_ofs = 0x8,
> > > > > +};
> > > > > +
> > > > > +#define GATE_APMIXED(_id, _name, _parent,
> > > > > _shift)                      \
> > > > > +       GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift,
> > > > > &mtk_clk_gate_ops_no_setclr_inv)
> > > > > +
> > > > > +static const struct mtk_gate apmixed_clks[] = {
> > > > > +       GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M, "pll_ssusb26m",
> > > > > "clk26m", 1),
> > > > > +};
> > > > > +
> > > > > +#define MT8195_PLL_FMAX                (3800UL * MHZ)
> > > > > +#define MT8195_PLL_FMIN                (1500UL * MHZ)
> > > > > +#define MT8195_INTEGER_BITS    8
> > > > > +
> > > > > +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask,
> > > _flags,      \
> > > > > +                       _rst_bar_mask, _pcwbits, _pd_reg,
> > > > > _pd_shift,    \
> > > > > +                       _tuner_reg, _tuner_en_reg,
> > > > > _tuner_en_bit,       \
> > > > > +                       _pcw_reg, _pcw_shift,
> > > > > _pcw_chg_reg,                             \
> > > > > +                       _en_reg, _pll_en_bit)
> > > > > {                                 \
> > > > > +               .id =
> > > > > _id,                                              \
> > > > > +               .name =
> > > > > _name,                                          \
> > > > > +               .reg =
> > > > > _reg,                                            \
> > > > > +               .pwr_reg =
> > > > > _pwr_reg,                                    \
> > > > > +               .en_mask =
> > > > > _en_mask,                                    \
> > > > > +               .flags =
> > > > > _flags,                                        \
> > > > > +               .rst_bar_mask =
> > > > > _rst_bar_mask,                          \
> > > > > +               .fmax =
> > > > > MT8195_PLL_FMAX,                                \
> > > > > +               .fmin =
> > > > > MT8195_PLL_FMIN,                                \
> > > > > +               .pcwbits =
> > > > > _pcwbits,                                    \
> > > > > +               .pcwibits =
> > > > > MT8195_INTEGER_BITS,                        \
> > > > > +               .pd_reg =
> > > > > _pd_reg,                                      \
> > > > > +               .pd_shift =
> > > > > _pd_shift,                                  \
> > > > > +               .tuner_reg =
> > > > > _tuner_reg,                                \
> > > > > +               .tuner_en_reg =
> > > > > _tuner_en_reg,                          \
> > > > > +               .tuner_en_bit =
> > > > > _tuner_en_bit,                          \
> > > > > +               .pcw_reg =
> > > > > _pcw_reg,                                    \
> > > > > +               .pcw_shift =
> > > > > _pcw_shift,                                \
> > > > > +               .pcw_chg_reg =
> > > > > _pcw_chg_reg,                            \
> > > > > +               .en_reg =
> > > > > _en_reg,                                      \
> > > > > +               .pll_en_bit =
> > > > > _pll_en_bit,                              \
> > > > > +       }
> > > > > +
> > > > > +static const struct mtk_pll_data plls[] = {
> > > > > +       PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0, 0,
> > > > > +               0, 0, 22, 0x0398, 24, 0, 0, 0, 0x0398, 0,
> > > 0x0398,
> > > > > 0, 9),
> > > > > +       PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320, 0,
> > > > > +               0, 0, 22, 0x0198, 24, 0, 0, 0, 0x0198, 0,
> > > 0x0198,
> > > > > 0, 9),
> > > > > +       PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370, 0,
> > > > > +               0, 0, 22, 0x0368, 24, 0, 0, 0, 0x0368, 0,
> > > 0x0368,
> > > > > 0, 9),
> > > > > +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
> > > > > +               0, 0, 22, 0x0718, 24, 0, 0, 0, 0x0718, 0,
> > > 0x0718,
> > > > > 0, 9),
> > > > > +       PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x00a0, 0x00b0, 0,
> > > > > +               0, 0, 22, 0x00a8, 24, 0, 0, 0, 0x00a8, 0,
> > > 0x00a8,
> > > > > 0, 9),
> > > > > +       PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x00c0, 0x00d0, 0,
> > > > > +               0, 0, 22, 0x00c8, 24, 0, 0, 0, 0x00c8, 0,
> > > 0x00c8,
> > > > > 0, 9),
> > > > > +       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x00e0, 0x00f0,
> > > 0xff000000,
> > > > > +               HAVE_RST_BAR, BIT(23), 22, 0x00e8, 24, 0, 0, 0,
> > > > > 0x00e8, 0, 0x00e8, 0, 9),
> > > > > +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x01d0, 0x01e0,
> > > > > 0xff000000,
> > > > > +               HAVE_RST_BAR, BIT(23), 22, 0x01d8, 24, 0, 0, 0,
> > > > > 0x01d8, 0, 0x01d8, 0, 9),
> > > > > +       PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x0890, 0x08a0, 0,
> > > > > +               0, 0, 22, 0x0898, 24, 0, 0, 0, 0x0898, 0,
> > > 0x0898,
> > > > > 0, 9),
> > > > > +       PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0100, 0x0110, 0,
> > > > > +               0, 0, 22, 0x0108, 24, 0, 0, 0, 0x0108, 0,
> > > 0x0108,
> > > > > 0, 9),
> > > > > +       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x01f0, 0x0700,
> > > > > 0xff000000,
> > > > > +               HAVE_RST_BAR, BIT(23), 22, 0x01f8, 24, 0, 0, 0,
> > > > > 0x01f8, 0, 0x01f8, 0, 9),
> > > > > +       PLL(CLK_APMIXED_HDMIPLL1, "hdmipll1", 0x08c0, 0x08d0,
> > > 0,
> > > > > +               0, 0, 22, 0x08c8, 24, 0, 0, 0, 0x08c8, 0,
> > > 0x08c8,
> > > > > 0, 9),
> > > > > +       PLL(CLK_APMIXED_HDMIPLL2, "hdmipll2", 0x0870, 0x0880,
> > > 0,
> > > > > +               0, 0, 22, 0x0878, 24, 0, 0, 0, 0x0878, 0,
> > > 0x0878,
> > > > > 0, 9),
> > > > > +       PLL(CLK_APMIXED_HDMIRX_APLL, "hdmirx_apll", 0x08e0,
> > > 0x0dd4,
> > > > > 0,
> > > > > +               0, 0, 32, 0x08e8, 24, 0, 0, 0, 0x08ec, 0,
> > > 0x08e8,
> > > > > 0, 9),
> > > > > +       PLL(CLK_APMIXED_USB1PLL, "usb1pll", 0x01a0, 0x01b0, 0,
> > > > > +               0, 0, 22, 0x01a8, 24, 0, 0, 0, 0x01a8, 0,
> > > 0x01a8,
> > > > > 0, 9),
> > > > > +       PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x07e0, 0x07f0, 0,
> > > > > +               0, 0, 22, 0x07e8, 24, 0, 0, 0, 0x07e8, 0,
> > > 0x07e8,
> > > > > 0, 9),
> > > > > +       PLL(CLK_APMIXED_APLL1, "apll1", 0x07c0, 0x0dc0, 0,
> > > > > +               0, 0, 32, 0x07c8, 24, 0x0470, 0x0000, 12,
> > > 0x07cc,
> > > > > 0, 0x07c8, 0, 9),
> > > > > +       PLL(CLK_APMIXED_APLL2, "apll2", 0x0780, 0x0dc4, 0,
> > > > > +               0, 0, 32, 0x0788, 24, 0x0474, 0x0000, 13,
> > > 0x078c,
> > > > > 0, 0x0788, 0, 9),
> > > > > +       PLL(CLK_APMIXED_APLL3, "apll3", 0x0760, 0x0dc8, 0,
> > > > > +               0, 0, 32, 0x0768, 24, 0x0478, 0x0000, 14,
> > > 0x076c,
> > > > > 0, 0x0768, 0, 9),
> > > > > +       PLL(CLK_APMIXED_APLL4, "apll4", 0x0740, 0x0dcc, 0,
> > > > > +               0, 0, 32, 0x0748, 24, 0x047C, 0x0000, 15,
> > > 0x074c,
> > > > > 0, 0x0748, 0, 9),
> > > > > +       PLL(CLK_APMIXED_APLL5, "apll5", 0x07a0, 0x0dd0,
> > > 0x100000,
> > > > > +               0, 0, 32, 0x07a8, 24, 0x0480, 0x0000, 16,
> > > 0x07ac,
> > > > > 0, 0x07a8, 0, 9),
> > > > > +       PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x0350, 0,
> > > > > +               0, 0, 22, 0x0348, 24, 0, 0, 0, 0x0348, 0,
> > > 0x0348,
> > > > > 0, 9),
> > > > > +       PLL(CLK_APMIXED_DGIPLL, "dgipll", 0x0150, 0x0160, 0,
> > > > > +               0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0,
> > > 0x0158,
> > > > > 0, 9),
> > > > > +};
> > > > > +
> > > > > +static struct clk_onecell_data *top_clk_data;
> > > > > +
> > > > > +static void clk_mt8195_top_init_early(struct device_node
> > > *node)
> > > > > +{
> > > > > +       int i;
> > > > > +
> > > > > +       top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
> > > > > +       if (!top_clk_data)
> > > > > +               return;
> > > > > +
> > > > > +       for (i = 0; i < CLK_TOP_NR_CLK; i++)
> > > > > +               top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
> > > > > +
> > > > > +       mtk_clk_register_factors(top_early_divs,
> > > > > ARRAY_SIZE(top_early_divs), top_clk_data);
> > > > > +
> > > > > +       of_clk_add_provider(node, of_clk_src_onecell_get,
> > > > > top_clk_data);
> > > > > +}
> > > > > +
> > > > > +CLK_OF_DECLARE_DRIVER(mt8195_topckgen,
> > > "mediatek,mt8195-topckgen",
> > > > > +                       clk_mt8195_top_init_early);
> > > > > +
> > > > > +static int clk_mt8195_top_probe(struct platform_device *pdev)
> > > > > +{
> > > > > +       struct device_node *node = pdev->dev.of_node;
> > > > > +       int r;
> > > > > +       void __iomem *base;
> > > > > +
> > > > > +       base = devm_platform_ioremap_resource(pdev, 0);
> > > > > +       if (IS_ERR(base))
> > > > > +               return PTR_ERR(base);
> > > > > +
> > > > > +       mtk_clk_register_fixed_clks(top_fixed_clks,
> > > > > ARRAY_SIZE(top_fixed_clks),
> > > > > +                       top_clk_data);
> > > > > +       mtk_clk_register_factors(top_early_divs,
> > > > > ARRAY_SIZE(top_early_divs), top_clk_data);
> > > > > +       mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
> > > > > top_clk_data);
> > > > > +       mtk_clk_register_muxes(top_mtk_muxes,
> > > > > ARRAY_SIZE(top_mtk_muxes), node,
> > > > > +                       &mt8195_clk_lock, top_clk_data);
> > > > > +       mtk_clk_register_composites(top_muxes,
> > > > > ARRAY_SIZE(top_muxes), base,
> > > > > +                       &mt8195_clk_lock, top_clk_data);
> > > > > +       mtk_clk_register_composites(top_adj_divs,
> > > > > ARRAY_SIZE(top_adj_divs), base,
> > > > > +                       &mt8195_clk_lock, top_clk_data);
> >
> > >
> >
> > > Future work: these functions probably should be made to return
> > > errors.
> > >
> >
> >
> > > > > +       r = mtk_clk_register_gates(node, top_clks,
> > > > > ARRAY_SIZE(top_clks), top_clk_data);
> > > > > +       if (r)
> > > > > +               return r;
> > > > > +
> > > > > +       return of_clk_add_provider(node, of_clk_src_onecell_get,
> > > > > top_clk_data);
> > > > > +}
> > > > > +
> > > > > +static int clk_mt8195_infra_ao_probe(struct platform_device
> > > *pdev)
> > > > > +{
> > > > > +       struct clk_onecell_data *clk_data;
> > > > > +       struct device_node *node = pdev->dev.of_node;
> > > > > +       int r;
> > > > > +
> > > > > +       clk_data = mtk_alloc_clk_data(CLK_INFRA_AO_NR_CLK);
> > > > > +       if (!clk_data)
> > > > > +               return -ENOMEM;
> > > > > +
> > > > > +       r = mtk_clk_register_gates(node, infra_ao_clks,
> > > > > ARRAY_SIZE(infra_ao_clks), clk_data);
> > > > > +       if (r)
> > > > > +               return r;
> > > > > +
> > > > > +       return of_clk_add_provider(node, of_clk_src_onecell_get,
> > > > > clk_data);
> >
> > >
> >
> > > You are leaking clk_data if mtk_clk_register_gates() or
> > > of_clk_add_provider()
> > > fail.
> > >
> >
>
>
>
> Ok, I will fix it include you mention below, thanks for you comment.
>
>
> > > > > +}
> > > > > +
> > > > > +static int clk_mt8195_apmixed_probe(struct platform_device
> > > *pdev)
> > > > > +{
> > > > > +       struct clk_onecell_data *clk_data;
> > > > > +       struct device_node *node = pdev->dev.of_node;
> > > > > +       int r;
> > > > > +
> > > > > +       clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
> > > > > +       if (!clk_data)
> > > > > +               return -ENOMEM;
> > > > > +
> > > > > +       mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
> > > > > clk_data);
> > > > > +       r = mtk_clk_register_gates(node, apmixed_clks,
> > > > > ARRAY_SIZE(apmixed_clks), clk_data);
> > > > > +       if (r)
> > > > > +               return r;
> > > > > +
> > > > > +       return of_clk_add_provider(node, of_clk_src_onecell_get,
> > > > > clk_data);
> >
> > >
> >
> > > Same here.
> > >
> >
> >
> > > > > +}
> > > > > +
> > > > > +static int clk_mt8195_peri_ao_probe(struct platform_device
> > > *pdev)
> > > > > +{
> > > > > +       struct clk_onecell_data *clk_data;
> > > > > +       struct device_node *node = pdev->dev.of_node;
> > > > > +       int r;
> > > > > +
> > > > > +       clk_data = mtk_alloc_clk_data(CLK_PERI_AO_NR_CLK);
> > > > > +       if (!clk_data)
> > > > > +               return -ENOMEM;
> > > > > +
> > > > > +       r = mtk_clk_register_gates(node, peri_ao_clks,
> > > > > ARRAY_SIZE(peri_ao_clks), clk_data);
> > > > > +       if (r)
> > > > > +               return r;
> > > > > +
> > > > > +       return of_clk_add_provider(node, of_clk_src_onecell_get,
> > > > > clk_data);
> >
> > >
> >
> > > And here.
> > >
> >
> >
> > > > > +}
> > > > > +
> > > > > +static const struct of_device_id of_match_clk_mt8195[] = {
> > > > > +       {
> > > > > +               .compatible = "mediatek,mt8195-apmixedsys",
> > > > > +               .data = clk_mt8195_apmixed_probe,
> > > > > +       }, {
> > > > > +               .compatible = "mediatek,mt8195-topckgen",
> > > > > +               .data = clk_mt8195_top_probe,
> > > > > +       }, {
> > > > > +               .compatible = "mediatek,mt8195-infracfg_ao",
> > > > > +               .data = clk_mt8195_infra_ao_probe,
> > > > > +       }, {
> > > > > +               .compatible = "mediatek,mt8195-pericfg_ao",
> > > > > +               .data = clk_mt8195_peri_ao_probe,
> >
> > >
> >
> > > This file contains four drivers. They do not have depend on each
> > > other,
> > > and do not need to be in the same file. Please split them into
> > > different
> > > files and preferably different patches so people reading them don't
> > > have
> > > to look through unrelated data. Then you don't need the pointer to
> > > the
> > > probe function.
> > >
> >
>
>
>
> Ok, I will split to different driver.
>
>
> > > You can keep them under the same Kconfig symbol.
> > >
> >
> >
> > > > > +       }, {
> > > > > +               /* sentinel */
> > > > > +       }
> > > > > +};
> > > > > +
> > > > > +static int clk_mt8195_probe(struct platform_device *pdev)
> > > > > +{
> > > > > +       int (*clk_probe)(struct platform_device *pdev);
> > > > > +       int r;
> > > > > +
> > > > > +       clk_probe = of_device_get_match_data(&pdev->dev);
> > > > > +       if (!clk_probe)
> > > > > +               return -EINVAL;
> > > > > +
> > > > > +       r = clk_probe(pdev);
> > > > > +       if (r)
> > > > > +               dev_err(&pdev->dev,
> > > > > +                       "could not register clock provider: %s:
> > > > > %d\n",
> > > > > +                       pdev->name, r);
> > > > > +
> > > > > +       return r;
> > > > > +}
> > > > > +
> > > > > +static struct platform_driver clk_mt8195_drv = {
> > > > > +       .probe = clk_mt8195_probe,
> > > > > +       .driver = {
> > > > > +               .name = "clk-mt8195",
> > > > > +               .of_match_table = of_match_clk_mt8195,
> > > > > +       },
> > > > > +};
> > > > > +
> > > > > +static int __init clk_mt8195_init(void)
> > > > > +{
> > > > > +       return platform_driver_register(&clk_mt8195_drv);
> > > > > +}
> > > > > +
> > > > > +arch_initcall(clk_mt8195_init);
> >
> > >
> >
> > > Is there any particular reason for arch_initcall?
> > >
> >
>
>
> APMIXEDSYS/TOPCKGEN are clock source of others IP block and
> PERICFG/INFRACFG provide peripheral and bus clocks control, so we want
> to init early.

Sure, but this should really be done through standard dependency
handling, and not trying to sequence them by hand.

Is there an observable benefit to having arch_initcall() vs the standard
order with builtin_platform_driver()? If so, this should be documented
here as a justifcation for arch_initcall().


Regards
ChenYu

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 04/22] clk: mediatek: Add MT8195 basic clocks support
  2021-07-22  7:44       ` Chen-Yu Tsai
@ 2021-08-11  4:31         ` Chun-Jie Chen
  0 siblings, 0 replies; 59+ messages in thread
From: Chun-Jie Chen @ 2021-08-11  4:31 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk,
	devicetree, srv_heupstream, Project_Global_Chrome_Upstream_Group

On Thu, 2021-07-22 at 15:44 +0800, Chen-Yu Tsai wrote:
> Hi,
> 
> It seems your reply included HTML, which means that it never reached
> the mailing lists. Please always use plaintext only.
> 
> On Thu, Jul 22, 2021 at 08:17:40AM +0800, Chun-Jie Chen wrote:
> > On Fri, 2021-07-02 at 19:44 +0800, Chen-Yu Tsai wrote:
> > > > On Thu, Jun 17, 2021 at 7:05 AM Chun-Jie Chen
> > > > <chun-jie.chen@mediatek.com> wrote:
> > > > > > 
> > > > > > Add MT8195 basic clock providers, include topckgen,
> > > > > > apmixedsys,
> > > > > > infracfg_ao and pericfg_ao.
> > > > > > 
> > > > > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > > > > > ---
> > > > > >  drivers/clk/mediatek/Kconfig      |    8 +
> > > > > >  drivers/clk/mediatek/Makefile     |    1 +
> > > > > >  drivers/clk/mediatek/clk-mt8195.c | 1958
> > > > > > +++++++++++++++++++++++++++++
> > > > > >  3 files changed, 1967 insertions(+)
> > > > > >  create mode 100644 drivers/clk/mediatek/clk-mt8195.c
> > > > > > 
> > > > > > diff --git a/drivers/clk/mediatek/Kconfig
> > > > > > b/drivers/clk/mediatek/Kconfig
> > > > > > index 576babd86f98..6707aba3d500 100644
> > > > > > --- a/drivers/clk/mediatek/Kconfig
> > > > > > +++ b/drivers/clk/mediatek/Kconfig
> > > > > > @@ -580,6 +580,14 @@ config COMMON_CLK_MT8192_VENCSYS
> > > > > >         help
> > > > > >           This driver supports MediaTek MT8192 vencsys
> > > > > > clocks.
> > > > > > 
> > > > > > +config COMMON_CLK_MT8195
> > > > > > +       bool "Clock driver for MediaTek MT8195"
> > > > > > +       depends on ARM64 || COMPILE_TEST
> > > > > > +       select COMMON_CLK_MEDIATEK
> > > > > > +       default ARM64
> > > > > > +       help
> > > > > > +         This driver supports MediaTek MT8195 basic
> > > > > > clocks.
> > > > > > +
> > > > > >  config COMMON_CLK_MT8516
> > > > > >         bool "Clock driver for MediaTek MT8516"
> > > > > >         depends on ARCH_MEDIATEK || COMPILE_TEST
> > > > > > diff --git a/drivers/clk/mediatek/Makefile
> > > > > > b/drivers/clk/mediatek/Makefile
> > > > > > index 15bc045f0b71..f8002d8966e1 100644
> > > > > > --- a/drivers/clk/mediatek/Makefile
> > > > > > +++ b/drivers/clk/mediatek/Makefile
> > > > > > @@ -80,5 +80,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) +=
> > > > > > clk-
> > > > > > mt8192-msdc.o
> > > > > >  obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) +=
> > > > 
> > > > clk-mt8192-scp_adsp.o
> > > > > >  obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-
> > > > > > vdec.o
> > > > > >  obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-
> > > > > > venc.o
> > > > > > +obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195.o
> > > > > >  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
> > > > > >  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> > > > > > diff --git a/drivers/clk/mediatek/clk-mt8195.c
> > > > > > b/drivers/clk/mediatek/clk-mt8195.c
> > > > > > new file mode 100644
> > > > > > index 000000000000..aea9ebe4c051
> > > > > > --- /dev/null
> > > > > > +++ b/drivers/clk/mediatek/clk-mt8195.c
> > > > > > @@ -0,0 +1,1958 @@
> > > > > > +// SPDX-License-Identifier: GPL-2.0-only
> > > > > > +//
> > > > > > +// Copyright (c) 2021 MediaTek Inc.
> > > > > > +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > > > > > +
> > > > > > +#include <linux/clk.h>
> > > > > > +#include <linux/delay.h>
> > > > > > +#include <linux/mfd/syscon.h>
> > > > > > +#include <linux/of.h>
> > > > > > +#include <linux/of_address.h>
> > > > > > +#include <linux/of_device.h>
> > > > > > +#include <linux/platform_device.h>
> > > > > > +#include <linux/slab.h>
> > > > > > +
> > > > > > +#include "clk-mtk.h"
> > > > > > +#include "clk-mux.h"
> > > > > > +#include "clk-gate.h"
> > > > > > +
> > > > > > +#include <dt-bindings/clock/mt8195-clk.h>
> > > > > > +
> > > > > > +static DEFINE_SPINLOCK(mt8195_clk_lock);
> > > > > > +
> > > > > > +static const struct mtk_fixed_clk top_fixed_clks[] = {
> > > > > > +       FIXED_CLK(CLK_TOP_IN_DGI, "in_dgi", NULL,
> > > > > > 165000000),
> > > > > > +       FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL,
> > > > > > 248000000),
> > > > > > +       FIXED_CLK(CLK_TOP_ULPOSC2, "ulposc2", NULL,
> > > > > > 326000000),
> > > > > > +       FIXED_CLK(CLK_TOP_MEM_466M, "mem_466m", NULL,
> > > > 
> > > > 533000000),
> > > > > > +       FIXED_CLK(CLK_TOP_MPHONE_SLAVE_B, "mphone_slave_b",
> > > > 
> > > > NULL,
> > > > > > 49152000),
> > > > > > +       FIXED_CLK(CLK_TOP_PEXTP_PIPE, "pextp_pipe", NULL,
> > > > > > 250000000),
> > > > > > +       FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL, "ufs_rx_symbol",
> > > > > > NULL,
> > > > > > 166000000),
> > > > > > +       FIXED_CLK(CLK_TOP_UFS_TX_SYMBOL, "ufs_tx_symbol",
> > > > > > NULL,
> > > > > > 166000000),
> > > > > > +       FIXED_CLK(CLK_TOP_SSUSB_U3PHY_P1_P_P0,
> > > > > > "ssusb_u3phy_p1_p_p0", NULL, 131000000),
> > > > > > +       FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL1, "ufs_rx_symbol1",
> > > > 
> > > > NULL,
> > > > > > 166000000),
> > > > > > +       FIXED_CLK(CLK_TOP_FPC, "fpc", NULL, 50000000),
> > > > > > +       FIXED_CLK(CLK_TOP_HDMIRX_P, "hdmirx_p", NULL,
> > > > 
> > > > 594000000),
> > > > 
> > > > I assume these are fixed PLLs? They should have inputs
> > > > (parents).
> > > > 
> > > > Moreover, at least ULPOSC and ULPOSC2 look like they are in
> > > > APMIXEDSYS
> > > > 
> > 
> > The clock in top_fixed_clks is special clock that generated from
> > the
> > specific hardware block, not PLLs in APMIXEDSYS. ULPOSC and ULPOSC2
> > has
> > configuration register in APMIXEDSYS, but their clock source are
> > not
> > "clk26m" (other plls in APMIXEDSYS in is generated from "clk26m")
> 
> I see. Surely they have some input though. It would be nice to be
> able
> to have them described.
> 
> > > > > > +};T
> > > > > > +
> > > > > > +static const struct mtk_fixed_factor top_early_divs[] = {
> > > > > > +       FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1,
> > > > > > 2),
> > > > > > +};
> > > > > > +
> > > > > > +static const struct mtk_fixed_factor top_divs[] = {
> > > > > > +       FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m",
> > > > > > 1,
> > > > 
> > > > 52),
> > > > > > +       FACTOR(CLK_TOP_IN_DGI_D2, "in_dgi_d2", "in_dgi", 1,
> > > > > > 2),
> > > > > > +       FACTOR(CLK_TOP_IN_DGI_D4, "in_dgi_d4", "in_dgi", 1,
> > > > > > 4),
> > > > > > +       FACTOR(CLK_TOP_IN_DGI_D6, "in_dgi_d6", "in_dgi", 1,
> > > > > > 6),
> > > > > > +       FACTOR(CLK_TOP_IN_DGI_D8, "in_dgi_d8", "in_dgi", 1,
> > > > > > 8),
> > > > > > +       FACTOR(CLK_TOP_MFGPLL_OPP, "mfgpll_opp", "mfgpll",
> > > > > > 1,
> > > > 
> > > > 1),
> > > > > > +       FACTOR(CLK_TOP_MAINPLL, "mainpll_ck", "mainpll", 1,
> > > > > > 1),
> > > > 
> > > > Why are this and other 1:1 factor clks needed? They look like
> > > > placeholders.
> > > > Please remove them.
> > 
> > 
> > 
> > These 1:1 factors make more readable between dividers. For example,
> > CLK_APMIXED_MAINPLL and CLK_TOP_MAINPLL_D3 is not easy to see the
> > relation, but CLK_TOP_MAINPLL and CLK_TOP_MAINPLL_D3 is more clear
> > to
> > see the relation.
> 
> If the clocks are named appropriately, it should be clear that
> "mainpll_dX"
> is derived from "mainpll". We really don't need an extra "mainpll_ck"
> in
> between.
> 
> The only thing gained here is having the parent clock in the same
> driver.
> But that is only a problem because we are directly using global clock
> names
> for parent names. This isn't the preferred way for clock parenting.
> 
> For proper parenting, the driver should be using `struct
> clk_parent_data`
> if possible, or using of_clk_get_parent_name() or of_clk_get_hw()
> manually
> to get the parent's global name or a reference to it. This is
> something
> the clk drivers should slowly be converted to doing.
> 
> I'm not saying we should do everything now, but we can start by
> getting
> rid of some of the excess baggage.
> 
> [...]

Ok, I will remove the 1-to-1 divider in next version.
Thanks for your comment.

> 
> > > > > > +static const char * const dsp7_parents[] = {
> > > > > > +       "clk26m",
> > > > > > +       "univpll_d6_d2",
> > > > > > +       "univpll_d4_d2",
> > > > > > +       "univpll_d5",
> > > > > > +       "univpll_d4",
> > > > > > +       "mmpll_d4",
> > > > > > +       "mainpll_d3",
> > > > > > +       "univpll_d3"
> > > > > > +};
> > > > 
> > > > If dsp~dsp7_parents are all the same, please merge them and
> > > > share
> > > 
> > > one
> > > > instance. And since they are located a bit far from the clock
> > > > definitions
> > > > in this file, please add comments describing which clocks share
> > > > the
> > > > same
> > > > set of parents.
> > > > 
> > 
> > I will merge it if they can share the same parent source data
> > (include
> > you mention below), thanks for your comment.
> 
> Great!
> 
> [...]
> 
> Tip: You can trim out portions of the original email from your reply,
> like
> what I did here, so that the emails are shorter. Keeping just the
> bits that
> are relevant to the discussion is better for the reader. In cases
> here a
> lot of it are related cases, you could keep just the one nearest to
> your
> reply.
> 
> > > > > > +static const char * const spinor_parents[] = {
> > > > > > +       "clk26m",
> > > > 
> > > > Datasheet says first parent is "univpll_d5_d8". Please check
> > > > with
> > > > hardware
> > > > engineers. If the datasheet is wrong please add a comment
> > > > saying so.
> > > > 
> > > 
> > > 
> > > > > > +       "clk26m_d2",
> > > > > > +       "mainpll_d7_d8",
> > > > > > +       "univpll_d6_d8"
> > > > > > +};
> > > > > > +
> > 
> > The parent source here is correct, but not update to the latest in
> > datasheet.
> 
> For future reference, could you leave a comment stating that the
> datasheet
> has not been updated then? Please include the version of the
> datasheet.
> 

The parent source here was updated at v25 internal version.

> > > > > > +static const char * const dvio_dgi_ref_parents[] = {
> > > > > > +       "clk26m",
> > > > > > +       "in_dgi",
> > > > > > +       "in_dgi_d2",
> > > > > > +       "in_dgi_d4",
> > > > > > +       "in_dgi_d6",
> > > > > > +       "in_dgi_d8",
> > > > > > +       "mmpll_d4_d4"
> > > > > > +};
> > > > > > +
> > > > > > +static const char * const srck_parents[] = {
> > > > > > +       "ulposc_d10",
> > > > > > +       "clk26m"
> > > > > > +};
> > > > > > +
> > > > > > +static const char * const rsvd1_parents[] = {
> > > > > > +       "clk26m",
> > > > > > +       "mainpll_d4_d4",
> > > > > > +       "mainpll_d5_d4",
> > > > > > +       "mainpll_d6_d4",
> > > > > > +       "mainpll_d7_d4",
> > > > > > +       "univpll_d6_d4",
> > > > 
> > > > These are completely different from the datasheet. Please
> > > > check.
> > > > 
> > > 
> > > 
> > > > > > +       "ulposc",
> > > > > > +       "ulposc2"
> > > > > > +};
> > > > > > +
> > 
> > The parent source here is correct, but not update to the latest in
> > datasheet.
> 
> Same for this one.
> 

The parent source here was updated at v25 internal version.

> > > > > > +static const char * const mfg_fast_parents[] = {
> > > > > > +       "mfg_sel",
> > > > > > +       "mfgpll_opp"
> > > > > > +};
> > > > > > +
> > > > > > +static const struct mtk_mux top_mtk_muxes[] = {
> > > > > > +       /* CLK_CFG_0 */
> > > > > > +       MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL,
> > > > > > "axi_sel",
> > > > 
> > > > Please drop the "_sel" suffix from the clock names. It would
> > > > have
> > > > made
> > > > sense if this were purely a mux, and there was another clock
> > > > gate.
> > > > But
> > > > since the driver combines the two components into one
> > > 
> > > representation,
> > > > please just drop the suffix that implies just a mux. This goes
> > > > for
> > > > all
> > > > clocks in the series and also the macro bindings.
> > 
> > 
> > 
> > If we move the "_sel" suffix from clock names, it's hard to
> > represent
> > this mux with gate control. Do you think revise it to
> > "XXX_sel_gate" in
> > CCF name but keep the binding name because change the binding name
> > need
> > all CCF consumer changes.
> 
> Please elaborate. Does the "type" of the clock matter? All that is
> really needed is that the name is unique, matches the datasheet more
> or
> less, and describes the usage or purpose of the clock.
> 
> For example, on Allwinner sunxi platforms, we don't include the type
> of the clock in the clock names. Only the base clock name is used.
> That is because the clocks are modeled as composite-ish clocks, so
> only one clock is needed to describe a full mux+divider+gate.
> 
> On other platforms, the clock driver deliberately uses base clock
> types,
> mux, div, and gate, to build up a representation of the full clock
> unit.
> In these cases, we end up with "XXX_mux", "XXX_div", and "XXX_gate".
> 
> Since the Mediatek clock driver is more like the first case, I would
> prefer to see clock names with just the base name, and none of the
> typing.
> 
> And regarding binding names, please change them as well. Right now
> the
> only place that needs to be changed are the header files. This is the
> time to get them right.
> 

Ok, I will remove suffix "_SEL" in binding name and change
clock name from "xxx_sel" to "top_xxx".
Thanks for your comment.

> > > > > > +               axi_parents, 0x020, 0x024, 0x028, 0, 3, 7,
> > > > > > 0x04,
> > > > 
> > > > 0,
> > > > > > CLK_IS_CRITICAL),
> > > > > > +       MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL,
> > > > > > "spm_sel",
> > > > > > +               spm_parents, 0x020, 0x024, 0x028, 8, 2, 15,
> > > > 
> > > > 0x04,
> > > > > > 1, CLK_IS_CRITICAL),
> > > > 
> > > > Where is the SCP clock?
> > 
> > 
> > 
> > Because SCP is always on and no other clock gates need to reference
> > it,
> > so move it.
> 
> Please add a comment as a placeholder then. The comment could simply
> state "clock is always on and should not be handled by Linux".
> 
> [...]
> 

Ok, I will leave some comment to describe why skip or why make is
critical in next version.

> > > > > > +       /* CLK_CFG_11 */
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SEL, "usb_sel",
> > > > 
> > > > The datasheet lists these as "usb_top" and "usb_top_Xp". Please
> > > > keep
> > > > the name
> > > > the same as the datasheet so it is easy to search for. Also
> > > > note the
> > > > discrepency
> > > > between the macro name and the clock name. Same goes for the
> > > > three
> > > > other USB
> > > > clocks.
> > 
> > 
> > 
> > Do you think revise the name the same as datasheet in CCF name but
> > keep
> > binding name?
> 
> Please have them match each other. The whole point of keeping names
> consistent is to be able to search for them easily.
> 

Ok, I will revise the clock name which can match in datasheet.

> > > > 
> > > 
> > > 
> > > > > > +               usb_parents, 0x0A4, 0x0A8, 0x0AC, 0, 2, 7,
> > > > > > 0x08,
> > > > > > 12),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL,
> > > > > > "ssusb_xhci_sel",
> > > > > > +               ssusb_xhci_parents, 0x0A4, 0x0A8, 0x0AC, 8,
> > > > > > 2,
> > > > 
> > > > 15,
> > > > > > 0x08, 13),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_1P_SEL,
> > > > > > "usb_1p_sel",
> > > > > > +               usb_1p_parents, 0x0A4, 0x0A8, 0x0AC, 16, 2,
> > > > > > 23,
> > > > > > 0x08, 14),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_1P_SEL,
> > > > > > "ssusb_xhci_1p_sel",
> > > > > > +               ssusb_xhci_1p_parents, 0x0A4, 0x0A8, 0x0AC,
> > > > > > 24,
> > > > 
> > > > 2,
> > > > > > 31, 0x08, 15),
> > > > > > +       /* CLK_CFG_12 */
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_2P_SEL,
> > > > > > "usb_2p_sel",
> > > > > > +               usb_2p_parents, 0x0B0, 0x0B4, 0x0B8, 0, 2,
> > > > > > 7,
> > > > 
> > > > 0x08,
> > > > > > 16),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P_SEL,
> > > > > > "ssusb_xhci_2p_sel",
> > > > > > +               ssusb_xhci_2p_parents, 0x0B0, 0x0B4, 0x0B8,
> > > > > > 8,
> > > > 
> > > > 2,
> > > > > > 15, 0x08, 17),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_3P_SEL,
> > > > > > "usb_3p_sel",
> > > > > > +               usb_3p_parents, 0x0B0, 0x0B4, 0x0B8, 16, 2,
> > > > > > 23,
> > > > > > 0x08, 18),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P_SEL,
> > > > > > "ssusb_xhci_3p_sel",
> > > > > > +               ssusb_xhci_3p_parents, 0x0B0, 0x0B4, 0x0B8,
> > > > > > 24,
> > > > 
> > > > 2,
> > > > > > 31, 0x08, 19),
> > > > > > +       /* CLK_CFG_13 */
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel",
> > > > > > +               i2c_parents, 0x0BC, 0x0C0, 0x0C4, 0, 2, 7,
> > > > > > 0x08,
> > > > > > 20),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL,
> > > > > > "seninf_sel",
> > > > > > +               seninf_parents, 0x0BC, 0x0C0, 0x0C4, 8, 3,
> > > > > > 15,
> > > > > > 0x08, 21),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL,
> > > > 
> > > > "seninf1_sel",
> > > > > > +               seninf1_parents, 0x0BC, 0x0C0, 0x0C4, 16,
> > > > > > 3, 23,
> > > > > > 0x08, 22),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2_SEL,
> > > > 
> > > > "seninf2_sel",
> > > > > > +               seninf2_parents, 0x0BC, 0x0C0, 0x0C4, 24,
> > > > > > 3, 31,
> > > > > > 0x08, 23),
> > > > > > +       /* CLK_CFG_14 */
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3_SEL,
> > > > 
> > > > "seninf3_sel",
> > > > > > +               seninf3_parents, 0x0C8, 0x0CC, 0x0D0, 0, 3,
> > > > > > 7,
> > > > > > 0x08, 24),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, "gcpu_sel",
> > > > > > +               gcpu_parents, 0x0C8, 0x0CC, 0x0D0, 8, 3,
> > > > > > 15,
> > > > 
> > > > 0x08,
> > > > > > 25),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel",
> > > > > > +               dxcc_parents, 0x0C8, 0x0CC, 0x0D0, 16, 2,
> > > > > > 23,
> > > > 
> > > > 0x08,
> > > > > > 26),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_SEL,
> > > > > > "dpmaif_sel",
> > > > > > +               dpmaif_parents, 0x0C8, 0x0CC, 0x0D0, 24, 3,
> > > > > > 31,
> > > > > > 0x08, 27),
> > > > > > +       /* CLK_CFG_15 */
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL,
> > > > > > "aes_ufsfde_sel",
> > > > > > +               aes_ufsfde_parents, 0x0D4, 0x0D8, 0x0DC, 0,
> > > > > > 3,
> > > > 
> > > > 7,
> > > > > > 0x08, 28),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_SEL, "ufs_sel",
> > > > > > +               ufs_parents, 0x0D4, 0x0D8, 0x0DC, 8, 3, 15,
> > > > 
> > > > 0x08,
> > > > > > 29),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_TICK1US_SEL,
> > > > > > "ufs_tick1us_sel",
> > > > > > +               ufs_tick1us_parents, 0x0D4, 0x0D8, 0x0DC,
> > > > > > 16, 1,
> > > > > > 23, 0x08, 30),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_MP_SAP_SEL,
> > > > > > "ufs_mp_sap_sel",
> > > > > > +               ufs_mp_sap_parents, 0x0D4, 0x0D8, 0x0DC,
> > > > > > 24, 1,
> > > > 
> > > > 31,
> > > > > > 0x08, 31),
> > > > > > +       /* CLK_CFG_16 */
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel",
> > > > > > +               venc_parents, 0x0E0, 0x0E4, 0x0E8, 0, 4, 7,
> > > > 
> > > > 0x0C,
> > > > > > 0),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel",
> > > > > > +               vdec_parents, 0x0E0, 0x0E4, 0x0E8, 8, 4,
> > > > > > 15,
> > > > 
> > > > 0x0C,
> > > > > > 1),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel",
> > > > > > +               pwm_parents, 0x0E0, 0x0E4, 0x0E8, 16, 1,
> > > > > > 23,
> > > > 
> > > > 0x0C,
> > > > > > 2),
> > > > 
> > > > MCU clock? Not sure what it's supposed to be called since the
> > > > naming
> > > > has a
> > > > slightly different format.
> > > > 
> > > > If you are skipping clocks, please leave a comment in the list
> > > > explaining
> > > > why.
> > > > 
> > > 
> > > "mcupm" is another micro-processor and is always on, and no
> > > others
> > > clock gates need to reference it, so remove it.
> 
> Please add a comment, just like in the SCP clock case.
> 
> > > > > > +       /* CLK_CFG_17 */
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST_SEL,
> > > > > > "spmi_p_mst_sel",
> > > > > > +               spmi_p_mst_parents, 0x0EC, 0x0F0, 0x0F4, 0,
> > > > > > 4,
> > > > 
> > > > 7,
> > > > > > 0x0C, 4),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST_SEL,
> > > > > > "spmi_m_mst_sel",
> > > > > > +               spmi_m_mst_parents, 0x0EC, 0x0F0, 0x0F4, 8,
> > > > > > 4,
> > > > 
> > > > 15,
> > > > > > 0x0C, 5),
> > > > 
> > > > DVFSRC clock?
> > > > 
> > > 
> > > "DVFSRC" IP block is always on  and no others clock gates need to
> > > reference it, so remove it.
> 
> This one as well.
> 
> [...]
> 
> > > > > > +       /* CLK_CFG_24 */
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5_SEL,
> > > > > > "apll5_sel",
> > > > > > +               apll5_parents, 0x0140, 0x0144, 0x0148, 0,
> > > > > > 1, 7,
> > > > > > 0x010, 0),
> > > > 
> > > > For the APLLs, you will need to differentiate them from the
> > > > actual
> > > > PLLs in
> > > > the APMIXEDSYS block.
> > > > 
> > > 
> > > APLLX providers more precise clock so it has more configuration
> > > register, but it still has same control flow like other PLLs in
> > > APMIXEDSYS.
> 
> I think what I meant was, because I asked to remove the "_sel"
> suffix,
> the global clock names here now collide with the ones in APMIXEDSYS.
> So what I was asking was the names here need to be changed, maybe to
> something like "top_apllX".
> 
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1_M_SEL,
> > > > 
> > > > "i2so1_m_sel",
> > > > > > +               i2so1_m_parents, 0x0140, 0x0144, 0x0148, 8,
> > > > > > 3,
> > > > 
> > > > 15,
> > > > > > 0x010, 1),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2_M_SEL,
> > > > 
> > > > "i2so2_m_sel",
> > > > > > +               i2so2_m_parents, 0x0140, 0x0144, 0x0148,
> > > > > > 16, 3,
> > > > 
> > > > 23,
> > > > > > 0x010, 2),
> > > > 
> > > > I2SO4_M?
> > > > 
> > > 
> > > 
> > > > > > +       /* CLK_CFG_25 */
> > > > 
> > > > I2SO5_M?
> > > > 
> > > 
> > > 
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1_M_SEL,
> > > > 
> > > > "i2si1_m_sel",
> > > > > > +               i2si1_m_parents, 0x014C, 0x0150, 0x0154, 8,
> > > > > > 3,
> > > > 
> > > > 15,
> > > > > > 0x010, 5),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2_M_SEL,
> > > > 
> > > > "i2si2_m_sel",
> > > > > > +               i2si2_m_parents, 0x014C, 0x0150, 0x0154,
> > > > > > 16, 3,
> > > > 
> > > > 23,
> > > > > > 0x010, 6),
> > > > 
> > > > I2SI4_M?
> > > > 
> > > 
> > > 
> > > > > > +       /* CLK_CFG_26 */
> > > > 
> > > > I2SI5_M?
> > > > 
> > > 
> > > I2SO4/I2SO5/I2SI4_M/I2SI5_M is not used in MT8195, so remove it
> > > here.
> 
> Please add comments as placeholders for them. The comment could state
> that the clock is unused in the hardware design, so it was skipped.
> 
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX_M_SEL,
> > > > > > "dptx_m_sel",
> > > > > > +               dptx_m_parents, 0x0158, 0x015C, 0x0160, 8,
> > > > > > 3,
> > > > 
> > > > 15,
> > > > > > 0x010, 9),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC_SEL,
> > > > 
> > > > "aud_iec_sel",
> > > > > > +               aud_iec_parents, 0x0158, 0x015C, 0x0160,
> > > > > > 16, 3,
> > > > 
> > > > 23,
> > > > > > 0x010, 10),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP_SEL,
> > > > 
> > > > "a1sys_hp_sel",
> > > > > > +               a1sys_hp_parents, 0x0158, 0x015C, 0x0160,
> > > > > > 24, 1,
> > > > > > 31, 0x010, 11),
> > > > > > +       /* CLK_CFG_27 */
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS_SEL,
> > > > > > "a2sys_sel",
> > > > > > +               a2sys_parents, 0x0164, 0x0168, 0x016C, 0,
> > > > > > 1, 7,
> > > > > > 0x010, 12),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS_SEL,
> > > > > > "a3sys_sel",
> > > > > > +               a3sys_parents, 0x0164, 0x0168, 0x016C, 8,
> > > > > > 3, 15,
> > > > > > 0x010, 13),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS_SEL,
> > > > > > "a4sys_sel",
> > > > > > +               a4sys_parents, 0x0164, 0x0168, 0x016C, 16,
> > > > > > 3,
> > > > 
> > > > 23,
> > > > > > 0x010, 14),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_B_SEL,
> > > > 
> > > > "spinfi_b_sel",
> > > > > > +               spinfi_b_parents, 0x0164, 0x0168, 0x016C,
> > > > > > 24, 3,
> > > > > > 31, 0x010, 15),
> > > > > > +       /* CLK_CFG_28 */
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL,
> > > > > > "nfi1x_sel",
> > > > > > +               nfi1x_parents, 0x0170, 0x0174, 0x0178, 0,
> > > > > > 3, 7,
> > > > > > 0x010, 16),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, "ecc_sel",
> > > > > > +               ecc_parents, 0x0170, 0x0174, 0x0178, 8, 3,
> > > > > > 15,
> > > > > > 0x010, 17),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS_SEL,
> > > > > > "audio_local_bus_sel",
> > > > > > +               audio_local_bus_parents, 0x0170, 0x0174,
> > > > > > 0x0178,
> > > > > > 16, 4, 23, 0x010, 18),
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR_SEL,
> > > > > > "spinor_sel",
> > > > > > +               spinor_parents, 0x0170, 0x0174, 0x0178, 24,
> > > > > > 2,
> > > > 
> > > > 31,
> > > > > > 0x010, 19),
> > > > > > +       /* CLK_CFG_29 */
> > > > > > +       MUX_GATE_CLR_SET_UPD(CLK_TOP_DVIO_DGI_REF_SEL,
> > > > > > "dvio_dgi_ref_sel",
> > > > > > +               dvio_dgi_ref_parents, 0x017C, 0x0180,
> > > > > > 0x0184, 0,
> > > > 
> > > > 3,
> > > > > > 7, 0x010, 20),
> > > > 
> > > > ULPOSC and ULPOSC_CORE?
> > > > 
> > 
> > 
> > 
> > ULPOSC and ULPOSC_CORE is always on and no other clock gate needs
> > to
> > reference it, so just remove it.
> 
> Please add placeholder comments describing them, specifically why
> they
> are missing from the driver. Are the clocks used at all in the
> hardware
> design? If so then it might be better to add them to the clock
> driver.
> 
> Also, even if they, including SCP and MCU above, are always on, it
> might
> still be nice to have driver support for them, just to be able to
> read
> their state from Linux. We could have CLK_IS_CRITICAL set so they
> don't
> get disabled, and CLK_GET_RATE_NOCACHE if the clocks are expected to
> be
> changed by firmware running alongside of Linux.
> 
> > > > > > +       MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK_SEL,
> > > > 
> > > > "srck_sel",
> > > > > > +               srck_parents, 0x017C, 0x0180, 0x0184, 24,
> > > > > > 1, 31,
> > > > > > 0x010, 23, CLK_IS_CRITICAL),
> > > > 
> > > > What happened to CLK_CFG_30~36?
> > > > 
> > 
> > The muxes in CLK_CFG_30 ~ 36 are not used, so just remove it from
> > CCF.
> 
> Please add placeholder comments about them.
> 
> > > > > > +       /* CLK_CFG_37 */
> > > > > > +       MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_RSVD1_SEL,
> > > > 
> > > > "rsvd1_sel",
> > > > > > +               rsvd1_parents, 0x01DC, 0x01E0, 0x01E4, 0,
> > > > > > 3, 7,
> > > > > > 0x014, 20, CLK_IS_CRITICAL),
> > > > 
> > > > What about the other three?
> > > > 
> > 
> > 
> > "rsvd2" and "rsvd3" is not used, so remove it.
> 
> Same here.
> 
> To be honest, a "rsvd", which I interpret as "reserved", clock being
> used seems kind of contradicting. Do we know what hardware is using
> rsvd1?
> 
> > > > > > +};
> > > > > > +
> > > > > > +static struct mtk_composite top_muxes[] = {
> > > > > > +       /* CLK_MISC_CFG_3 */
> > > > > > +       MUX(CLK_TOP_MFG_FAST_SEL, "mfg_fast_sel",
> > > > 
> > > > mfg_fast_parents,
> > > > > > 0x0250, 8, 1),
> > > > > > +};
> > > > > > +
> > > > > > +static const struct mtk_composite top_adj_divs[] = {
> > > > > > +       DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0",
> > > > 
> > > > "i2si1_m_sel",
> > > > > > 0x0320, 0, 0x0328, 8, 0),
> > > > > > +       DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1",
> > > > 
> > > > "i2si2_m_sel",
> > > > > > 0x0320, 1, 0x0328, 8, 8),
> > > > > > +       DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2",
> > > > 
> > > > "i2so1_m_sel",
> > > > > > 0x0320, 2, 0x0328, 8, 16),
> > > > > > +       DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3",
> > > > 
> > > > "i2so2_m_sel",
> > > > > > 0x0320, 3, 0x0328, 8, 24),
> > > > > > +       DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4",
> > > > 
> > > > "aud_iec_sel",
> > > > > > 0x0320, 4, 0x0334, 8, 0),
> > > > 
> > > > What about 5~8?
> > > > 
> > > 
> > > div5 ~ 8 are not used in MT8195, so remove it.
> 
> Placeholder comments please.
> 
> [...]
> 
> > > > > > +static const struct mtk_gate_regs top0_cg_regs = {
> > > > > > +       .set_ofs = 0x238,
> > > > > > +       .clr_ofs = 0x238,
> > > > > > +       .sta_ofs = 0x238,
> > > > > > +};
> > > > > > +
> > > > > > +static const struct mtk_gate_regs top1_cg_regs = {
> > > > > > +       .set_ofs = 0x250,
> > > > > > +       .clr_ofs = 0x250,
> > > > > > +       .sta_ofs = 0x250,
> > > > > > +};
> > > > > > +
> > > > > > +#define GATE_TOP0_FLAGS(_id, _name, _parent, _shift,
> > > > > > _flag)            \
> > > > > > +       GATE_MTK_FLAGS(_id, _name, _parent, &top0_cg_regs,
> > > > > > _shift,      \
> > > > > > +               &mtk_clk_gate_ops_no_setclr_inv, _flag)
> > > > > > +
> > > > > > +#define GATE_TOP0(_id, _name, _parent,
> > > > 
> > > > _shift)                 \
> > > > > > +       GATE_TOP0_FLAGS(_id, _name, _parent, _shift, 0)
> > > > > > +
> > > > > > +#define GATE_TOP1(_id, _name, _parent,
> > > > 
> > > > _shift)                 \
> > > > > > +       GATE_MTK(_id, _name, _parent, &top1_cg_regs,
> > > > > > _shift,
> > > > > > &mtk_clk_gate_ops_no_setclr_inv)
> > > > > > +
> > > > > > +static const struct mtk_gate top_clks[] = {
> > > > > > +       /* TOP0 */
> > > > > > +       GATE_TOP0(CLK_TOP_CFG_VPP0, "cfg_vpp0", "vpp_sel",
> > > > > > 0),
> > > > > > +       GATE_TOP0(CLK_TOP_CFG_VPP1, "cfg_vpp1", "vpp_sel",
> > > > > > 1),
> > > > > > +       GATE_TOP0(CLK_TOP_CFG_VDO0, "cfg_vdo0", "vpp_sel",
> > > > > > 2),
> > > > > > +       GATE_TOP0(CLK_TOP_CFG_VDO1, "cfg_vdo1", "vpp_sel",
> > > > > > 3),
> > > > > > +       GATE_TOP0(CLK_TOP_CFG_UNIPLL_SES, "cfg_unipll_ses",
> > > > > > "univpll_d2", 4),
> > > > > > +       GATE_TOP0(CLK_TOP_CFG_26M_VPP0, "cfg_26m_vpp0",
> > > > 
> > > > "clk26m",
> > > > > > 5),
> > > > > > +       GATE_TOP0(CLK_TOP_CFG_26M_VPP1, "cfg_26m_vpp1",
> > > > 
> > > > "clk26m",
> > > > > > 6),
> > > > > > +       GATE_TOP0(CLK_TOP_CFG_26M_AUD, "cfg_26m_aud",
> > > > > > "clk26m",
> > > > 
> > > > 9),
> > > > > > +       GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST,
> > > > > > "cfg_axi_east",
> > > > > > "axi_sel", 10, CLK_IS_CRITICAL),
> > > > > > +       GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST_NORTH,
> > > > > > "cfg_axi_east_north", "axi_sel", 11,
> > > > > > +               CLK_IS_CRITICAL),
> > > > > > +       GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_NORTH,
> > > > > > "cfg_axi_north",
> > > > > > "axi_sel", 12, CLK_IS_CRITICAL),
> > > > > > +       GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_SOUTH,
> > > > > > "cfg_axi_south",
> > > > > > "axi_sel", 13, CLK_IS_CRITICAL),
> > > > > > +       GATE_TOP0(CLK_TOP_CFG_EXT_TEST, "cfg_ext_test",
> > > > > > "msdcpll_d2", 15),
> > > > > > +       /* TOP1 */
> > > > > > +       GATE_TOP1(CLK_TOP_SSUSB_REF, "ssusb_ref", "clk26m",
> > > > > > 0),
> > > > > > +       GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref",
> > > > 
> > > > "clk26m",
> > > > > > 1),
> > > > > > +       GATE_TOP1(CLK_TOP_SSUSB_P1_REF, "ssusb_p1_ref",
> > > > 
> > > > "clk26m",
> > > > > > 2),
> > > > > > +       GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF,
> > > > > > "ssusb_phy_p1_ref",
> > > > > > "clk26m", 3),
> > > > > > +       GATE_TOP1(CLK_TOP_SSUSB_P2_REF, "ssusb_p2_ref",
> > > > 
> > > > "clk26m",
> > > > > > 4),
> > > > > > +       GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF,
> > > > > > "ssusb_phy_p2_ref",
> > > > > > "clk26m", 5),
> > > > > > +       GATE_TOP1(CLK_TOP_SSUSB_P3_REF, "ssusb_p3_ref",
> > > > 
> > > > "clk26m",
> > > > > > 6),
> > > > > > +       GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF,
> > > > > > "ssusb_phy_p3_ref",
> > > > > > "clk26m", 7),
> > > > > > +};
> > > > 
> > > > These should be grouped with the other TOPCKGEN clocks. Another
> > > > reason to
> > > > split this driver into multiple ones.
> > > > 
> > 
> > 
> > 
> > These clocks are "clock gate" in TOPCKGEN, so we separate the data
> > of
> > "clock gate" from "clock mux".
> 
> Right, but it gets really confusing when the driver is mixing clocks
> from different clock controllers. Code that gets used together should
> be grouped together. In this case, code for the same hardware block
> should be grouped together. So please split the drivers up if they
> end
> up being really big, and then group the remaining ones by hardware
> block first, then type second.
> 

I will separate the clocks here to different clock driver, each driver
only keep the clocks that provided by same IP block.

> > > > > > +
> > > > > > +static const struct mtk_gate_regs apmixed_cg_regs = {
> > > > > > +       .set_ofs = 0x8,
> > > > > > +       .clr_ofs = 0x8,
> > > > > > +       .sta_ofs = 0x8,
> > > > > > +};
> > > > > > +
> > > > > > +#define GATE_APMIXED(_id, _name, _parent,
> > > > > > _shift)                      \
> > > > > > +       GATE_MTK(_id, _name, _parent, &apmixed_cg_regs,
> > > > > > _shift,
> > > > > > &mtk_clk_gate_ops_no_setclr_inv)
> > > > > > +
> > > > > > +static const struct mtk_gate apmixed_clks[] = {
> > > > > > +       GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M,
> > > > > > "pll_ssusb26m",
> > > > > > "clk26m", 1),
> > > > > > +};
> > > > > > +
> > > > > > +#define MT8195_PLL_FMAX                (3800UL * MHZ)
> > > > > > +#define MT8195_PLL_FMIN                (1500UL * MHZ)
> > > > > > +#define MT8195_INTEGER_BITS    8
> > > > > > +
> > > > > > +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask,
> > > > 
> > > > _flags,      \
> > > > > > +                       _rst_bar_mask, _pcwbits, _pd_reg,
> > > > > > _pd_shift,    \
> > > > > > +                       _tuner_reg, _tuner_en_reg,
> > > > > > _tuner_en_bit,       \
> > > > > > +                       _pcw_reg, _pcw_shift,
> > > > > > _pcw_chg_reg,                             \
> > > > > > +                       _en_reg, _pll_en_bit)
> > > > > > {                                 \
> > > > > > +               .id =
> > > > > > _id,                                              \
> > > > > > +               .name =
> > > > > > _name,                                          \
> > > > > > +               .reg =
> > > > > > _reg,                                            \
> > > > > > +               .pwr_reg =
> > > > > > _pwr_reg,                                    \
> > > > > > +               .en_mask =
> > > > > > _en_mask,                                    \
> > > > > > +               .flags =
> > > > > > _flags,                                        \
> > > > > > +               .rst_bar_mask =
> > > > > > _rst_bar_mask,                          \
> > > > > > +               .fmax =
> > > > > > MT8195_PLL_FMAX,                                \
> > > > > > +               .fmin =
> > > > > > MT8195_PLL_FMIN,                                \
> > > > > > +               .pcwbits =
> > > > > > _pcwbits,                                    \
> > > > > > +               .pcwibits =
> > > > > > MT8195_INTEGER_BITS,                        \
> > > > > > +               .pd_reg =
> > > > > > _pd_reg,                                      \
> > > > > > +               .pd_shift =
> > > > > > _pd_shift,                                  \
> > > > > > +               .tuner_reg =
> > > > > > _tuner_reg,                                \
> > > > > > +               .tuner_en_reg =
> > > > > > _tuner_en_reg,                          \
> > > > > > +               .tuner_en_bit =
> > > > > > _tuner_en_bit,                          \
> > > > > > +               .pcw_reg =
> > > > > > _pcw_reg,                                    \
> > > > > > +               .pcw_shift =
> > > > > > _pcw_shift,                                \
> > > > > > +               .pcw_chg_reg =
> > > > > > _pcw_chg_reg,                            \
> > > > > > +               .en_reg =
> > > > > > _en_reg,                                      \
> > > > > > +               .pll_en_bit =
> > > > > > _pll_en_bit,                              \
> > > > > > +       }
> > > > > > +
> > > > > > +static const struct mtk_pll_data plls[] = {
> > > > > > +       PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0,
> > > > > > 0,
> > > > > > +               0, 0, 22, 0x0398, 24, 0, 0, 0, 0x0398, 0,
> > > > 
> > > > 0x0398,
> > > > > > 0, 9),
> > > > > > +       PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320,
> > > > > > 0,
> > > > > > +               0, 0, 22, 0x0198, 24, 0, 0, 0, 0x0198, 0,
> > > > 
> > > > 0x0198,
> > > > > > 0, 9),
> > > > > > +       PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370,
> > > > > > 0,
> > > > > > +               0, 0, 22, 0x0368, 24, 0, 0, 0, 0x0368, 0,
> > > > 
> > > > 0x0368,
> > > > > > 0, 9),
> > > > > > +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720,
> > > > > > 0,
> > > > > > +               0, 0, 22, 0x0718, 24, 0, 0, 0, 0x0718, 0,
> > > > 
> > > > 0x0718,
> > > > > > 0, 9),
> > > > > > +       PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x00a0, 0x00b0,
> > > > > > 0,
> > > > > > +               0, 0, 22, 0x00a8, 24, 0, 0, 0, 0x00a8, 0,
> > > > 
> > > > 0x00a8,
> > > > > > 0, 9),
> > > > > > +       PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x00c0, 0x00d0,
> > > > > > 0,
> > > > > > +               0, 0, 22, 0x00c8, 24, 0, 0, 0, 0x00c8, 0,
> > > > 
> > > > 0x00c8,
> > > > > > 0, 9),
> > > > > > +       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x00e0, 0x00f0,
> > > > 
> > > > 0xff000000,
> > > > > > +               HAVE_RST_BAR, BIT(23), 22, 0x00e8, 24, 0,
> > > > > > 0, 0,
> > > > > > 0x00e8, 0, 0x00e8, 0, 9),
> > > > > > +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x01d0, 0x01e0,
> > > > > > 0xff000000,
> > > > > > +               HAVE_RST_BAR, BIT(23), 22, 0x01d8, 24, 0,
> > > > > > 0, 0,
> > > > > > 0x01d8, 0, 0x01d8, 0, 9),
> > > > > > +       PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x0890, 0x08a0,
> > > > > > 0,
> > > > > > +               0, 0, 22, 0x0898, 24, 0, 0, 0, 0x0898, 0,
> > > > 
> > > > 0x0898,
> > > > > > 0, 9),
> > > > > > +       PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0100, 0x0110,
> > > > > > 0,
> > > > > > +               0, 0, 22, 0x0108, 24, 0, 0, 0, 0x0108, 0,
> > > > 
> > > > 0x0108,
> > > > > > 0, 9),
> > > > > > +       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x01f0, 0x0700,
> > > > > > 0xff000000,
> > > > > > +               HAVE_RST_BAR, BIT(23), 22, 0x01f8, 24, 0,
> > > > > > 0, 0,
> > > > > > 0x01f8, 0, 0x01f8, 0, 9),
> > > > > > +       PLL(CLK_APMIXED_HDMIPLL1, "hdmipll1", 0x08c0,
> > > > > > 0x08d0,
> > > > 
> > > > 0,
> > > > > > +               0, 0, 22, 0x08c8, 24, 0, 0, 0, 0x08c8, 0,
> > > > 
> > > > 0x08c8,
> > > > > > 0, 9),
> > > > > > +       PLL(CLK_APMIXED_HDMIPLL2, "hdmipll2", 0x0870,
> > > > > > 0x0880,
> > > > 
> > > > 0,
> > > > > > +               0, 0, 22, 0x0878, 24, 0, 0, 0, 0x0878, 0,
> > > > 
> > > > 0x0878,
> > > > > > 0, 9),
> > > > > > +       PLL(CLK_APMIXED_HDMIRX_APLL, "hdmirx_apll", 0x08e0,
> > > > 
> > > > 0x0dd4,
> > > > > > 0,
> > > > > > +               0, 0, 32, 0x08e8, 24, 0, 0, 0, 0x08ec, 0,
> > > > 
> > > > 0x08e8,
> > > > > > 0, 9),
> > > > > > +       PLL(CLK_APMIXED_USB1PLL, "usb1pll", 0x01a0, 0x01b0,
> > > > > > 0,
> > > > > > +               0, 0, 22, 0x01a8, 24, 0, 0, 0, 0x01a8, 0,
> > > > 
> > > > 0x01a8,
> > > > > > 0, 9),
> > > > > > +       PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x07e0, 0x07f0,
> > > > > > 0,
> > > > > > +               0, 0, 22, 0x07e8, 24, 0, 0, 0, 0x07e8, 0,
> > > > 
> > > > 0x07e8,
> > > > > > 0, 9),
> > > > > > +       PLL(CLK_APMIXED_APLL1, "apll1", 0x07c0, 0x0dc0, 0,
> > > > > > +               0, 0, 32, 0x07c8, 24, 0x0470, 0x0000, 12,
> > > > 
> > > > 0x07cc,
> > > > > > 0, 0x07c8, 0, 9),
> > > > > > +       PLL(CLK_APMIXED_APLL2, "apll2", 0x0780, 0x0dc4, 0,
> > > > > > +               0, 0, 32, 0x0788, 24, 0x0474, 0x0000, 13,
> > > > 
> > > > 0x078c,
> > > > > > 0, 0x0788, 0, 9),
> > > > > > +       PLL(CLK_APMIXED_APLL3, "apll3", 0x0760, 0x0dc8, 0,
> > > > > > +               0, 0, 32, 0x0768, 24, 0x0478, 0x0000, 14,
> > > > 
> > > > 0x076c,
> > > > > > 0, 0x0768, 0, 9),
> > > > > > +       PLL(CLK_APMIXED_APLL4, "apll4", 0x0740, 0x0dcc, 0,
> > > > > > +               0, 0, 32, 0x0748, 24, 0x047C, 0x0000, 15,
> > > > 
> > > > 0x074c,
> > > > > > 0, 0x0748, 0, 9),
> > > > > > +       PLL(CLK_APMIXED_APLL5, "apll5", 0x07a0, 0x0dd0,
> > > > 
> > > > 0x100000,
> > > > > > +               0, 0, 32, 0x07a8, 24, 0x0480, 0x0000, 16,
> > > > 
> > > > 0x07ac,
> > > > > > 0, 0x07a8, 0, 9),
> > > > > > +       PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x0350,
> > > > > > 0,
> > > > > > +               0, 0, 22, 0x0348, 24, 0, 0, 0, 0x0348, 0,
> > > > 
> > > > 0x0348,
> > > > > > 0, 9),
> > > > > > +       PLL(CLK_APMIXED_DGIPLL, "dgipll", 0x0150, 0x0160,
> > > > > > 0,
> > > > > > +               0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0,
> > > > 
> > > > 0x0158,
> > > > > > 0, 9),
> > > > > > +};
> > > > > > +
> > > > > > +static struct clk_onecell_data *top_clk_data;
> > > > > > +
> > > > > > +static void clk_mt8195_top_init_early(struct device_node
> > > > 
> > > > *node)
> > > > > > +{
> > > > > > +       int i;
> > > > > > +
> > > > > > +       top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
> > > > > > +       if (!top_clk_data)
> > > > > > +               return;
> > > > > > +
> > > > > > +       for (i = 0; i < CLK_TOP_NR_CLK; i++)
> > > > > > +               top_clk_data->clks[i] = ERR_PTR(-
> > > > > > EPROBE_DEFER);
> > > > > > +
> > > > > > +       mtk_clk_register_factors(top_early_divs,
> > > > > > ARRAY_SIZE(top_early_divs), top_clk_data);
> > > > > > +
> > > > > > +       of_clk_add_provider(node, of_clk_src_onecell_get,
> > > > > > top_clk_data);
> > > > > > +}
> > > > > > +
> > > > > > +CLK_OF_DECLARE_DRIVER(mt8195_topckgen,
> > > > 
> > > > "mediatek,mt8195-topckgen",
> > > > > > +                       clk_mt8195_top_init_early);
> > > > > > +
> > > > > > +static int clk_mt8195_top_probe(struct platform_device
> > > > > > *pdev)
> > > > > > +{
> > > > > > +       struct device_node *node = pdev->dev.of_node;
> > > > > > +       int r;
> > > > > > +       void __iomem *base;
> > > > > > +
> > > > > > +       base = devm_platform_ioremap_resource(pdev, 0);
> > > > > > +       if (IS_ERR(base))
> > > > > > +               return PTR_ERR(base);
> > > > > > +
> > > > > > +       mtk_clk_register_fixed_clks(top_fixed_clks,
> > > > > > ARRAY_SIZE(top_fixed_clks),
> > > > > > +                       top_clk_data);
> > > > > > +       mtk_clk_register_factors(top_early_divs,
> > > > > > ARRAY_SIZE(top_early_divs), top_clk_data);
> > > > > > +       mtk_clk_register_factors(top_divs,
> > > > > > ARRAY_SIZE(top_divs),
> > > > > > top_clk_data);
> > > > > > +       mtk_clk_register_muxes(top_mtk_muxes,
> > > > > > ARRAY_SIZE(top_mtk_muxes), node,
> > > > > > +                       &mt8195_clk_lock, top_clk_data);
> > > > > > +       mtk_clk_register_composites(top_muxes,
> > > > > > ARRAY_SIZE(top_muxes), base,
> > > > > > +                       &mt8195_clk_lock, top_clk_data);
> > > > > > +       mtk_clk_register_composites(top_adj_divs,
> > > > > > ARRAY_SIZE(top_adj_divs), base,
> > > > > > +                       &mt8195_clk_lock, top_clk_data);
> > > > 
> > > > Future work: these functions probably should be made to return
> > > > errors.
> > > > 
> > > 
> > > 
> > > > > > +       r = mtk_clk_register_gates(node, top_clks,
> > > > > > ARRAY_SIZE(top_clks), top_clk_data);
> > > > > > +       if (r)
> > > > > > +               return r;
> > > > > > +
> > > > > > +       return of_clk_add_provider(node,
> > > > > > of_clk_src_onecell_get,
> > > > > > top_clk_data);
> > > > > > +}
> > > > > > +
> > > > > > +static int clk_mt8195_infra_ao_probe(struct
> > > > > > platform_device
> > > > 
> > > > *pdev)
> > > > > > +{
> > > > > > +       struct clk_onecell_data *clk_data;
> > > > > > +       struct device_node *node = pdev->dev.of_node;
> > > > > > +       int r;
> > > > > > +
> > > > > > +       clk_data = mtk_alloc_clk_data(CLK_INFRA_AO_NR_CLK);
> > > > > > +       if (!clk_data)
> > > > > > +               return -ENOMEM;
> > > > > > +
> > > > > > +       r = mtk_clk_register_gates(node, infra_ao_clks,
> > > > > > ARRAY_SIZE(infra_ao_clks), clk_data);
> > > > > > +       if (r)
> > > > > > +               return r;
> > > > > > +
> > > > > > +       return of_clk_add_provider(node,
> > > > > > of_clk_src_onecell_get,
> > > > > > clk_data);
> > > > 
> > > > You are leaking clk_data if mtk_clk_register_gates() or
> > > > of_clk_add_provider()
> > > > fail.
> > > > 
> > 
> > 
> > 
> > Ok, I will fix it include you mention below, thanks for you
> > comment.
> > 
> > 
> > > > > > +}
> > > > > > +
> > > > > > +static int clk_mt8195_apmixed_probe(struct platform_device
> > > > 
> > > > *pdev)
> > > > > > +{
> > > > > > +       struct clk_onecell_data *clk_data;
> > > > > > +       struct device_node *node = pdev->dev.of_node;
> > > > > > +       int r;
> > > > > > +
> > > > > > +       clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
> > > > > > +       if (!clk_data)
> > > > > > +               return -ENOMEM;
> > > > > > +
> > > > > > +       mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
> > > > > > clk_data);
> > > > > > +       r = mtk_clk_register_gates(node, apmixed_clks,
> > > > > > ARRAY_SIZE(apmixed_clks), clk_data);
> > > > > > +       if (r)
> > > > > > +               return r;
> > > > > > +
> > > > > > +       return of_clk_add_provider(node,
> > > > > > of_clk_src_onecell_get,
> > > > > > clk_data);
> > > > 
> > > > Same here.
> > > > 
> > > 
> > > 
> > > > > > +}
> > > > > > +
> > > > > > +static int clk_mt8195_peri_ao_probe(struct platform_device
> > > > 
> > > > *pdev)
> > > > > > +{
> > > > > > +       struct clk_onecell_data *clk_data;
> > > > > > +       struct device_node *node = pdev->dev.of_node;
> > > > > > +       int r;
> > > > > > +
> > > > > > +       clk_data = mtk_alloc_clk_data(CLK_PERI_AO_NR_CLK);
> > > > > > +       if (!clk_data)
> > > > > > +               return -ENOMEM;
> > > > > > +
> > > > > > +       r = mtk_clk_register_gates(node, peri_ao_clks,
> > > > > > ARRAY_SIZE(peri_ao_clks), clk_data);
> > > > > > +       if (r)
> > > > > > +               return r;
> > > > > > +
> > > > > > +       return of_clk_add_provider(node,
> > > > > > of_clk_src_onecell_get,
> > > > > > clk_data);
> > > > 
> > > > And here.
> > > > 
> > > 
> > > 
> > > > > > +}
> > > > > > +
> > > > > > +static const struct of_device_id of_match_clk_mt8195[] = {
> > > > > > +       {
> > > > > > +               .compatible = "mediatek,mt8195-apmixedsys",
> > > > > > +               .data = clk_mt8195_apmixed_probe,
> > > > > > +       }, {
> > > > > > +               .compatible = "mediatek,mt8195-topckgen",
> > > > > > +               .data = clk_mt8195_top_probe,
> > > > > > +       }, {
> > > > > > +               .compatible = "mediatek,mt8195-
> > > > > > infracfg_ao",
> > > > > > +               .data = clk_mt8195_infra_ao_probe,
> > > > > > +       }, {
> > > > > > +               .compatible = "mediatek,mt8195-pericfg_ao",
> > > > > > +               .data = clk_mt8195_peri_ao_probe,
> > > > 
> > > > This file contains four drivers. They do not have depend on
> > > > each
> > > > other,
> > > > and do not need to be in the same file. Please split them into
> > > > different
> > > > files and preferably different patches so people reading them
> > > > don't
> > > > have
> > > > to look through unrelated data. Then you don't need the pointer
> > > > to
> > > > the
> > > > probe function.
> > > > 
> > 
> > 
> > 
> > Ok, I will split to different driver.
> > 
> > 
> > > > You can keep them under the same Kconfig symbol.
> > > > 
> > > 
> > > 
> > > > > > +       }, {
> > > > > > +               /* sentinel */
> > > > > > +       }
> > > > > > +};
> > > > > > +
> > > > > > +static int clk_mt8195_probe(struct platform_device *pdev)
> > > > > > +{
> > > > > > +       int (*clk_probe)(struct platform_device *pdev);
> > > > > > +       int r;
> > > > > > +
> > > > > > +       clk_probe = of_device_get_match_data(&pdev->dev);
> > > > > > +       if (!clk_probe)
> > > > > > +               return -EINVAL;
> > > > > > +
> > > > > > +       r = clk_probe(pdev);
> > > > > > +       if (r)
> > > > > > +               dev_err(&pdev->dev,
> > > > > > +                       "could not register clock provider:
> > > > > > %s:
> > > > > > %d\n",
> > > > > > +                       pdev->name, r);
> > > > > > +
> > > > > > +       return r;
> > > > > > +}
> > > > > > +
> > > > > > +static struct platform_driver clk_mt8195_drv = {
> > > > > > +       .probe = clk_mt8195_probe,
> > > > > > +       .driver = {
> > > > > > +               .name = "clk-mt8195",
> > > > > > +               .of_match_table = of_match_clk_mt8195,
> > > > > > +       },
> > > > > > +};
> > > > > > +
> > > > > > +static int __init clk_mt8195_init(void)
> > > > > > +{
> > > > > > +       return platform_driver_register(&clk_mt8195_drv);
> > > > > > +}
> > > > > > +
> > > > > > +arch_initcall(clk_mt8195_init);
> > > > 
> > > > Is there any particular reason for arch_initcall?
> > > > 
> > 
> > 
> > APMIXEDSYS/TOPCKGEN are clock source of others IP block and
> > PERICFG/INFRACFG provide peripheral and bus clocks control, so we
> > want
> > to init early.
> 
> Sure, but this should really be done through standard dependency
> handling, and not trying to sequence them by hand.
> 
> Is there an observable benefit to having arch_initcall() vs the
> standard
> order with builtin_platform_driver()? If so, this should be
> documented
> here as a justifcation for arch_initcall().
> 

I will use builtin_platform_driver like other subsys ip block
in next version.

Best Regards,
Chun-Jie

> 
> Regards
> ChenYu

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 08/22] clk: mediatek: Add MT8195 ccusys clock support
  2021-07-06  9:00   ` Chen-Yu Tsai
@ 2021-08-17  0:56     ` Chun-Jie Chen
  0 siblings, 0 replies; 59+ messages in thread
From: Chun-Jie Chen @ 2021-08-17  0:56 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Matthias Brugger, Stephen Boyd, Nicolas Boichat, Rob Herring,
	linux-arm-kernel, LKML, linux-mediatek, linux-clk, devicetree,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

On Tue, 2021-07-06 at 17:00 +0800, Chen-Yu Tsai wrote:
> On Thu, Jun 17, 2021 at 6:59 AM Chun-Jie Chen
> <chun-jie.chen@mediatek.com> wrote:
> > 
> > Add MT8195 ccusys clock provider
> > 
> > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> 
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
> 
> Also, I noticed that Mediatek drivers don't support the reset
> controls found
> in these clock controllers. Are there plans to add support for them?

At present, we have no plan to support reset control in clock
controllers because no request from sub system, but we have reset
controller in MT8195 from TOPRGU [1].

[1] 
https://patchwork.kernel.org/project/linux-mediatek/list/?series=521219

Best Regards,
Chun-Jie

^ permalink raw reply	[flat|nested] 59+ messages in thread

* Re: [PATCH 20/22] clk: mediatek: Add MT8195 wpesys clock support
  2021-06-16 22:47 ` [PATCH 20/22] clk: mediatek: Add MT8195 wpesys " Chun-Jie Chen
@ 2021-08-25 11:26   ` Chen-Yu Tsai
  0 siblings, 0 replies; 59+ messages in thread
From: Chen-Yu Tsai @ 2021-08-25 11:26 UTC (permalink / raw)
  To: Chun-Jie Chen, Stephen Boyd
  Cc: Matthias Brugger, Nicolas Boichat, Rob Herring,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, LKML,
	moderated list:ARM/Mediatek SoC support, linux-clk,
	Devicetree List, srv_heupstream,
	Project_Global_Chrome_Upstream_Group

On Thu, Jun 17, 2021 at 7:12 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 wpesys clock providers
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  drivers/clk/mediatek/Kconfig          |   6 ++
>  drivers/clk/mediatek/Makefile         |   1 +
>  drivers/clk/mediatek/clk-mt8195-wpe.c | 145 ++++++++++++++++++++++++++
>  3 files changed, 152 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt8195-wpe.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 91b1c19da1ab..5089bacdf0a5 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -678,6 +678,12 @@ config COMMON_CLK_MT8195_VPPSYS1
>         help
>           This driver supports MediaTek MT8195 vppsys1 clocks.
>
> +config COMMON_CLK_MT8195_WPESYS
> +       bool "Clock driver for MediaTek MT8195 wpesys"
> +       depends on COMMON_CLK_MT8195
> +       help
> +         This driver supports MediaTek MT8195 wpesys clocks.
> +
>  config COMMON_CLK_MT8516
>         bool "Clock driver for MediaTek MT8516"
>         depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index fbf57473bb91..32cfb0030d92 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -96,5 +96,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS1) += clk-mt8195-vdo1.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS0) += clk-mt8195-vpp0.o
>  obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS1) += clk-mt8195-vpp1.o
> +obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
>  obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
>  obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-wpe.c b/drivers/clk/mediatek/clk-mt8195-wpe.c
> new file mode 100644
> index 000000000000..99e8b1297ef7
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-wpe.c
> @@ -0,0 +1,145 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +
> +static const struct mtk_gate_regs wpe_cg_regs = {
> +       .set_ofs = 0x0,
> +       .clr_ofs = 0x0,
> +       .sta_ofs = 0x0,
> +};
> +
> +static const struct mtk_gate_regs wpe_vpp0_cg_regs = {
> +       .set_ofs = 0x58,
> +       .clr_ofs = 0x58,
> +       .sta_ofs = 0x58,
> +};
> +
> +static const struct mtk_gate_regs wpe_vpp1_cg_regs = {
> +       .set_ofs = 0x5c,
> +       .clr_ofs = 0x5c,
> +       .sta_ofs = 0x5c,
> +};
> +
> +#define GATE_WPE(_id, _name, _parent, _shift)                  \
> +       GATE_MTK(_id, _name, _parent, &wpe_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
> +
> +#define GATE_WPE_VPP0(_id, _name, _parent, _shift)                     \
> +       GATE_MTK(_id, _name, _parent, &wpe_vpp0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
> +
> +#define GATE_WPE_VPP1(_id, _name, _parent, _shift)                     \
> +       GATE_MTK(_id, _name, _parent, &wpe_vpp1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
> +
> +static const struct mtk_gate wpe_clks[] = {
> +       GATE_WPE(CLK_WPE_VPP0, "wpe_vpp0", "wpe_vpp_sel", 16),
> +       GATE_WPE(CLK_WPE_VPP1, "wpe_vpp1", "wpe_vpp_sel", 17),
> +       GATE_WPE(CLK_WPE_SMI_LARB7, "wpe_smi_larb7", "wpe_vpp_sel", 18),
> +       GATE_WPE(CLK_WPE_SMI_LARB8, "wpe_smi_larb8", "wpe_vpp_sel", 19),
> +       GATE_WPE(CLK_WPE_EVENT_TX, "wpe_event_tx", "wpe_vpp_sel", 20),
> +       GATE_WPE(CLK_WPE_SMI_LARB7_P, "wpe_smi_larb7_p", "wpe_vpp_sel", 24),
> +       GATE_WPE(CLK_WPE_SMI_LARB8_P, "wpe_smi_larb8_p", "wpe_vpp_sel", 25),
> +};
> +
> +static const struct mtk_gate wpe_vpp0_clks[] = {
> +       /* WPE_VPP0 */
> +       GATE_WPE_VPP0(CLK_WPE_VPP0_VGEN, "wpe_vpp0_vgen", "img_sel", 0),
> +       GATE_WPE_VPP0(CLK_WPE_VPP0_EXT, "wpe_vpp0_ext", "img_sel", 1),
> +       GATE_WPE_VPP0(CLK_WPE_VPP0_VFC, "wpe_vpp0_vfc", "img_sel", 2),
> +       GATE_WPE_VPP0(CLK_WPE_VPP0_CACH0_TOP, "wpe_vpp0_cach0_top", "img_sel", 3),
> +       GATE_WPE_VPP0(CLK_WPE_VPP0_CACH0_DMA, "wpe_vpp0_cach0_dma", "img_sel", 4),
> +       GATE_WPE_VPP0(CLK_WPE_VPP0_CACH1_TOP, "wpe_vpp0_cach1_top", "img_sel", 5),
> +       GATE_WPE_VPP0(CLK_WPE_VPP0_CACH1_DMA, "wpe_vpp0_cach1_dma", "img_sel", 6),
> +       GATE_WPE_VPP0(CLK_WPE_VPP0_CACH2_TOP, "wpe_vpp0_cach2_top", "img_sel", 7),
> +       GATE_WPE_VPP0(CLK_WPE_VPP0_CACH2_DMA, "wpe_vpp0_cach2_dma", "img_sel", 8),
> +       GATE_WPE_VPP0(CLK_WPE_VPP0_CACH3_TOP, "wpe_vpp0_cach3_top", "img_sel", 9),
> +       GATE_WPE_VPP0(CLK_WPE_VPP0_CACH3_DMA, "wpe_vpp0_cach3_dma", "img_sel", 10),
> +       GATE_WPE_VPP0(CLK_WPE_VPP0_PSP, "wpe_vpp0_psp", "img_sel", 11),
> +       GATE_WPE_VPP0(CLK_WPE_VPP0_PSP2, "wpe_vpp0_psp2", "img_sel", 12),
> +       GATE_WPE_VPP0(CLK_WPE_VPP0_SYNC, "wpe_vpp0_sync", "img_sel", 13),
> +       GATE_WPE_VPP0(CLK_WPE_VPP0_C24, "wpe_vpp0_c24", "img_sel", 14),
> +       GATE_WPE_VPP0(CLK_WPE_VPP0_MDP_CROP, "wpe_vpp0_mdp_crop", "img_sel", 15),
> +       GATE_WPE_VPP0(CLK_WPE_VPP0_ISP_CROP, "wpe_vpp0_isp_crop", "img_sel", 16),
> +       GATE_WPE_VPP0(CLK_WPE_VPP0_TOP, "wpe_vpp0_top", "img_sel", 17),
> +       /* WPE_VPP1 */
> +       GATE_WPE_VPP1(CLK_WPE_VPP0_VECI, "wpe_vpp0_veci", "img_sel", 0),
> +       GATE_WPE_VPP1(CLK_WPE_VPP0_VEC2I, "wpe_vpp0_vec2i", "img_sel", 1),
> +       GATE_WPE_VPP1(CLK_WPE_VPP0_VEC3I, "wpe_vpp0_vec3i", "img_sel", 2),
> +       GATE_WPE_VPP1(CLK_WPE_VPP0_WPEO, "wpe_vpp0_wpeo", "img_sel", 3),
> +       GATE_WPE_VPP1(CLK_WPE_VPP0_MSKO, "wpe_vpp0_msko", "img_sel", 4),
> +};
> +
> +static const struct mtk_gate wpe_vpp1_clks[] = {
> +       /* WPE_VPP0 */
> +       GATE_WPE_VPP0(CLK_WPE_VPP1_VGEN, "wpe_vpp1_vgen", "img_sel", 0),
> +       GATE_WPE_VPP0(CLK_WPE_VPP1_EXT, "wpe_vpp1_ext", "img_sel", 1),
> +       GATE_WPE_VPP0(CLK_WPE_VPP1_VFC, "wpe_vpp1_vfc", "img_sel", 2),
> +       GATE_WPE_VPP0(CLK_WPE_VPP1_CACH0_TOP, "wpe_vpp1_cach0_top", "img_sel", 3),
> +       GATE_WPE_VPP0(CLK_WPE_VPP1_CACH0_DMA, "wpe_vpp1_cach0_dma", "img_sel", 4),
> +       GATE_WPE_VPP0(CLK_WPE_VPP1_CACH1_TOP, "wpe_vpp1_cach1_top", "img_sel", 5),
> +       GATE_WPE_VPP0(CLK_WPE_VPP1_CACH1_DMA, "wpe_vpp1_cach1_dma", "img_sel", 6),
> +       GATE_WPE_VPP0(CLK_WPE_VPP1_CACH2_TOP, "wpe_vpp1_cach2_top", "img_sel", 7),
> +       GATE_WPE_VPP0(CLK_WPE_VPP1_CACH2_DMA, "wpe_vpp1_cach2_dma", "img_sel", 8),
> +       GATE_WPE_VPP0(CLK_WPE_VPP1_CACH3_TOP, "wpe_vpp1_cach3_top", "img_sel", 9),
> +       GATE_WPE_VPP0(CLK_WPE_VPP1_CACH3_DMA, "wpe_vpp1_cach3_dma", "img_sel", 10),
> +       GATE_WPE_VPP0(CLK_WPE_VPP1_PSP, "wpe_vpp1_psp", "img_sel", 11),
> +       GATE_WPE_VPP0(CLK_WPE_VPP1_PSP2, "wpe_vpp1_psp2", "img_sel", 12),
> +       GATE_WPE_VPP0(CLK_WPE_VPP1_SYNC, "wpe_vpp1_sync", "img_sel", 13),
> +       GATE_WPE_VPP0(CLK_WPE_VPP1_C24, "wpe_vpp1_c24", "img_sel", 14),
> +       GATE_WPE_VPP0(CLK_WPE_VPP1_MDP_CROP, "wpe_vpp1_mdp_crop", "img_sel", 15),
> +       GATE_WPE_VPP0(CLK_WPE_VPP1_ISP_CROP, "wpe_vpp1_isp_crop", "img_sel", 16),
> +       GATE_WPE_VPP0(CLK_WPE_VPP1_TOP, "wpe_vpp1_top", "img_sel", 17),
> +       /* WPE_VPP1 */
> +       GATE_WPE_VPP1(CLK_WPE_VPP1_VECI, "wpe_vpp1_veci", "img_sel", 0),
> +       GATE_WPE_VPP1(CLK_WPE_VPP1_VEC2I, "wpe_vpp1_vec2i", "img_sel", 1),
> +       GATE_WPE_VPP1(CLK_WPE_VPP1_VEC3I, "wpe_vpp1_vec3i", "img_sel", 2),
> +       GATE_WPE_VPP1(CLK_WPE_VPP1_WPEO, "wpe_vpp1_wpeo", "img_sel", 3),
> +       GATE_WPE_VPP1(CLK_WPE_VPP1_MSKO, "wpe_vpp1_msko", "img_sel", 4),
> +};
> +
> +static const struct mtk_clk_desc wpe_desc = {
> +       .clks = wpe_clks,
> +       .num_clks = ARRAY_SIZE(wpe_clks),
> +};
> +
> +static const struct mtk_clk_desc wpe_vpp0_desc = {
> +       .clks = wpe_vpp0_clks,
> +       .num_clks = ARRAY_SIZE(wpe_vpp0_clks),
> +};
> +
> +static const struct mtk_clk_desc wpe_vpp1_desc = {
> +       .clks = wpe_vpp1_clks,
> +       .num_clks = ARRAY_SIZE(wpe_vpp1_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8195_wpe[] = {
> +       {
> +               .compatible = "mediatek,mt8195-wpesys",
> +               .data = &wpe_desc,
> +       }, {
> +               .compatible = "mediatek,mt8195-wpesys_vpp0",
> +               .data = &wpe_vpp0_desc,
> +       }, {
> +               .compatible = "mediatek,mt8195-wpesys_vpp1",
> +               .data = &wpe_vpp1_desc,

Same comment as vencsys patch: wpesys_vpp0 and wpesys_vpp1 look the same.
Are they identical hardware blocks? Are different compatible strings
really needed?

I suggest adding clock-output-names to the device tree, and patching
mtk_clk_register_gates_with_dev() to try to get a clock name from the
device tree, and falling back to the predefined name in the list.
Something like:

<---------------
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 74890759e98c..71e856c22960 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -125,11 +125,15 @@ int mtk_clk_register_gates_with_dev(struct
device_node *node,

        for (i = 0; i < num; i++) {
                const struct mtk_gate *gate = &clks[i];
+               const char *name = gate->name;

                if (!IS_ERR_OR_NULL(clk_data->clks[gate->id]))
                        continue;

-               clk = mtk_clk_register_gate(gate->name, gate->parent_name,
+               of_property_read_string(node, "clock-output-names", gate->id,
+                                       &name);
+
+               clk = mtk_clk_register_gate(name, gate->parent_name,
                                regmap,
                                gate->regs->set_ofs,
                                gate->regs->clr_ofs,
<---------------
(tabs replaced with spaces, do not apply directly)


ChenYu


> +       }, {
> +               /* sentinel */
> +       }
> +};
> +
> +static struct platform_driver clk_mt8195_wpe_drv = {
> +       .probe = mtk_clk_simple_probe,
> +       .driver = {
> +               .name = "clk-mt8195-wpe",
> +               .of_match_table = of_match_clk_mt8195_wpe,
> +       },
> +};
> +
> +builtin_platform_driver(clk_mt8195_wpe_drv);
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 59+ messages in thread

end of thread, other threads:[~2021-08-25 11:26 UTC | newest]

Thread overview: 59+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
2021-06-16 22:47 ` [PATCH 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock Chun-Jie Chen
2021-06-24 21:21   ` Rob Herring
2021-07-12  9:32   ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 02/22] clk: mediatek: Add dt-bindings of MT8195 clocks Chun-Jie Chen
2021-06-24 21:22   ` Rob Herring
2021-07-12  9:37   ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg Chun-Jie Chen
2021-06-30  7:31   ` Chen-Yu Tsai
2021-06-30 10:53     ` Matthias Brugger
2021-06-30 11:09       ` Chen-Yu Tsai
2021-06-30 11:43         ` Matthias Brugger
2021-07-01  4:02           ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 04/22] clk: mediatek: Add MT8195 basic clocks support Chun-Jie Chen
2021-07-02 11:44   ` Chen-Yu Tsai
     [not found]     ` <1626913060.1546.4.camel@mtksdaap41>
2021-07-22  7:44       ` Chen-Yu Tsai
2021-08-11  4:31         ` Chun-Jie Chen
2021-06-16 22:47 ` [PATCH 05/22] clk: mediatek: Add MT8195 audio clock support Chun-Jie Chen
2021-07-05  9:03   ` Chen-Yu Tsai
2021-07-12  1:26     ` Chun-Jie Chen
2021-07-12  2:09       ` Chen-Yu Tsai
2021-07-12  4:35         ` Chun-Jie Chen
2021-07-12  7:06           ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 06/22] clk: mediatek: Add MT8195 audio src " Chun-Jie Chen
2021-07-05 10:07   ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 07/22] clk: mediatek: Add MT8195 camsys " Chun-Jie Chen
2021-07-06  8:53   ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 08/22] clk: mediatek: Add MT8195 ccusys " Chun-Jie Chen
2021-07-06  9:00   ` Chen-Yu Tsai
2021-08-17  0:56     ` Chun-Jie Chen
2021-06-16 22:47 ` [PATCH 09/22] clk: mediatek: Add MT8195 imgsys " Chun-Jie Chen
2021-07-06  9:07   ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 10/22] clk: mediatek: Add MT8195 ipesys " Chun-Jie Chen
2021-07-06  9:11   ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 11/22] clk: mediatek: Add MT8195 mfgcfg " Chun-Jie Chen
2021-07-09  6:29   ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 12/22] clk: mediatek: Add MT8195 scp adsp " Chun-Jie Chen
2021-07-09  6:39   ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 13/22] clk: mediatek: Add MT8195 nnasys " Chun-Jie Chen
2021-07-09  8:24   ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 14/22] clk: mediatek: Add MT8195 vdecsys " Chun-Jie Chen
2021-07-09  8:40   ` Chen-Yu Tsai
2021-07-12  1:34     ` Chun-Jie Chen
2021-06-16 22:47 ` [PATCH 15/22] clk: mediatek: Add MT8195 vdosys0 " Chun-Jie Chen
2021-07-09  8:51   ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 16/22] clk: mediatek: Add MT8195 vdosys1 " Chun-Jie Chen
2021-07-09  9:30   ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 17/22] clk: mediatek: Add MT8195 vencsys " Chun-Jie Chen
2021-07-09 10:26   ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 18/22] clk: mediatek: Add MT8195 vppsys0 " Chun-Jie Chen
2021-07-09 10:38   ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 19/22] clk: mediatek: Add MT8195 vppsys1 " Chun-Jie Chen
2021-07-09 10:45   ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 20/22] clk: mediatek: Add MT8195 wpesys " Chun-Jie Chen
2021-08-25 11:26   ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 21/22] clk: mediatek: Add MT8195 imp i2c wrapper " Chun-Jie Chen
2021-07-12  8:34   ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 22/22] clk: mediatek: Add MT8195 apusys " Chun-Jie Chen
2021-07-12  8:51   ` Chen-Yu Tsai

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