* [PATCH 1/2] arm64: dts: exynos7: Add cpu cache information
[not found] <CGME20210617113313epcas5p1fb3fff0b301b9e67a771349e72c2445b@epcas5p1.samsung.com>
@ 2021-06-17 11:37 ` Alim Akhtar
[not found] ` <CGME20210617113314epcas5p4652e98d24d7f56a7c8461175bbb25456@epcas5p4.samsung.com>
0 siblings, 1 reply; 4+ messages in thread
From: Alim Akhtar @ 2021-06-17 11:37 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, robh+dt
Cc: krzysztof.kozlowski, linux-samsung-soc, Alim Akhtar
This patch adds cpu caches information to its dt
nodes so that the same is available to userspace
via sysfs.
This SoC has 48/32 KB I/D cache for each cores
and 2MB of L2 cache.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
arch/arm64/boot/dts/exynos/exynos7.dtsi | 35 +++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 10244e59d56d..8b06397ba6e7 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -54,6 +54,13 @@
compatible = "arm,cortex-a57";
reg = <0x0>;
enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
};
cpu_atlas1: cpu@1 {
@@ -61,6 +68,13 @@
compatible = "arm,cortex-a57";
reg = <0x1>;
enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
};
cpu_atlas2: cpu@2 {
@@ -68,6 +82,13 @@
compatible = "arm,cortex-a57";
reg = <0x2>;
enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
};
cpu_atlas3: cpu@3 {
@@ -75,6 +96,20 @@
compatible = "arm,cortex-a57";
reg = <0x3>;
enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
+ };
+
+ atlas_l2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x200000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
};
};
base-commit: 614124bea77e452aa6df7a8714e8bc820b489922
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] arm64: dts: exynos5433: Add cpu cache information
[not found] ` <CGME20210617113314epcas5p4652e98d24d7f56a7c8461175bbb25456@epcas5p4.samsung.com>
@ 2021-06-17 11:37 ` Alim Akhtar
2021-06-21 8:51 ` Krzysztof Kozlowski
0 siblings, 1 reply; 4+ messages in thread
From: Alim Akhtar @ 2021-06-17 11:37 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, robh+dt
Cc: krzysztof.kozlowski, linux-samsung-soc, Alim Akhtar
This patch adds cpu caches information to its dt
nodes so that the same is available to userspace
via sysfs.
This SoC has 48/32 KB I/D cache for each A57 cores
with 2MB L2 cache.
And 32/32 KB I/D cache for each A53 cores with
256KB L2 cache.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 70 ++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 18a912eee360..8183a59e9046 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -62,6 +62,13 @@
clock-names = "apolloclk";
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&apollo_l2>;
};
cpu1: cpu@101 {
@@ -72,6 +79,13 @@
clock-frequency = <1300000000>;
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&apollo_l2>;
};
cpu2: cpu@102 {
@@ -82,6 +96,13 @@
clock-frequency = <1300000000>;
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&apollo_l2>;
};
cpu3: cpu@103 {
@@ -92,6 +113,13 @@
clock-frequency = <1300000000>;
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&apollo_l2>;
};
cpu4: cpu@0 {
@@ -104,6 +132,13 @@
clock-names = "atlasclk";
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
};
cpu5: cpu@1 {
@@ -114,6 +149,13 @@
clock-frequency = <1900000000>;
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
};
cpu6: cpu@2 {
@@ -124,6 +166,13 @@
clock-frequency = <1900000000>;
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
};
cpu7: cpu@3 {
@@ -134,6 +183,27 @@
clock-frequency = <1900000000>;
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
+ };
+
+ atlas_l2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x200000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ };
+
+ apollo_l2: l2-cache1 {
+ compatible = "cache";
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
};
};
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] arm64: dts: exynos5433: Add cpu cache information
2021-06-17 11:37 ` [PATCH 2/2] arm64: dts: exynos5433: " Alim Akhtar
@ 2021-06-21 8:51 ` Krzysztof Kozlowski
2021-06-21 13:46 ` Alim Akhtar
0 siblings, 1 reply; 4+ messages in thread
From: Krzysztof Kozlowski @ 2021-06-21 8:51 UTC (permalink / raw)
To: Alim Akhtar, linux-kernel, linux-arm-kernel, robh+dt; +Cc: linux-samsung-soc
On 17/06/2021 13:37, Alim Akhtar wrote:
> This patch adds cpu caches information to its dt
> nodes so that the same is available to userspace
> via sysfs.
> This SoC has 48/32 KB I/D cache for each A57 cores
> with 2MB L2 cache.
> And 32/32 KB I/D cache for each A53 cores with
> 256KB L2 cache.
>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 70 ++++++++++++++++++++++
> 1 file changed, 70 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index 18a912eee360..8183a59e9046 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -62,6 +62,13 @@
> clock-names = "apolloclk";
> operating-points-v2 = <&cluster_a53_opp_table>;
> #cooling-cells = <2>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&apollo_l2>;
> };
>
> cpu1: cpu@101 {
> @@ -72,6 +79,13 @@
> clock-frequency = <1300000000>;
> operating-points-v2 = <&cluster_a53_opp_table>;
> #cooling-cells = <2>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&apollo_l2>;
> };
>
> cpu2: cpu@102 {
> @@ -82,6 +96,13 @@
> clock-frequency = <1300000000>;
> operating-points-v2 = <&cluster_a53_opp_table>;
> #cooling-cells = <2>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&apollo_l2>;
> };
>
> cpu3: cpu@103 {
> @@ -92,6 +113,13 @@
> clock-frequency = <1300000000>;
> operating-points-v2 = <&cluster_a53_opp_table>;
> #cooling-cells = <2>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&apollo_l2>;
> };
>
> cpu4: cpu@0 {
> @@ -104,6 +132,13 @@
> clock-names = "atlasclk";
> operating-points-v2 = <&cluster_a57_opp_table>;
> #cooling-cells = <2>;
> + i-cache-size = <0xc000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&atlas_l2>;
> };
>
> cpu5: cpu@1 {
> @@ -114,6 +149,13 @@
> clock-frequency = <1900000000>;
> operating-points-v2 = <&cluster_a57_opp_table>;
> #cooling-cells = <2>;
> + i-cache-size = <0xc000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&atlas_l2>;
> };
>
> cpu6: cpu@2 {
> @@ -124,6 +166,13 @@
> clock-frequency = <1900000000>;
> operating-points-v2 = <&cluster_a57_opp_table>;
> #cooling-cells = <2>;
> + i-cache-size = <0xc000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&atlas_l2>;
> };
>
> cpu7: cpu@3 {
> @@ -134,6 +183,27 @@
> clock-frequency = <1900000000>;
> operating-points-v2 = <&cluster_a57_opp_table>;
> #cooling-cells = <2>;
> + i-cache-size = <0xc000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&atlas_l2>;
> + };
> +
> + atlas_l2: l2-cache0 {
Few other nodes (PMU, OPP tables) use a57/a53 names instead of
codenames, so I would prefer to stay with them (so cluster_a57_l2).
For Exynos7 it's fine as it uses Atlas already in labels.
> + compatible = "cache";
> + cache-size = <0x200000>;
> + cache-line-size = <64>;
> + cache-sets = <2048>;
> + };
> +
> + apollo_l2: l2-cache1 {
> + compatible = "cache";
> + cache-size = <0x40000>;
> + cache-line-size = <64>;
> + cache-sets = <256>;
> };
> };
>
>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH 2/2] arm64: dts: exynos5433: Add cpu cache information
2021-06-21 8:51 ` Krzysztof Kozlowski
@ 2021-06-21 13:46 ` Alim Akhtar
0 siblings, 0 replies; 4+ messages in thread
From: Alim Akhtar @ 2021-06-21 13:46 UTC (permalink / raw)
To: 'Krzysztof Kozlowski', linux-kernel, linux-arm-kernel, robh+dt
Cc: linux-samsung-soc
Hello Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> Sent: 21 June 2021 14:22
> To: Alim Akhtar <alim.akhtar@samsung.com>; linux-kernel@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; robh+dt@kernel.org
> Cc: linux-samsung-soc@vger.kernel.org
> Subject: Re: [PATCH 2/2] arm64: dts: exynos5433: Add cpu cache information
>
> On 17/06/2021 13:37, Alim Akhtar wrote:
> > This patch adds cpu caches information to its dt nodes so that the
> > same is available to userspace via sysfs.
> > This SoC has 48/32 KB I/D cache for each A57 cores with 2MB L2 cache.
> > And 32/32 KB I/D cache for each A53 cores with 256KB L2 cache.
> >
> > Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> > ---
> > arch/arm64/boot/dts/exynos/exynos5433.dtsi | 70
> > ++++++++++++++++++++++
> > 1 file changed, 70 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> > b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> > index 18a912eee360..8183a59e9046 100644
> > --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> > +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> > @@ -62,6 +62,13 @@
> > clock-names = "apolloclk";
> > operating-points-v2 = <&cluster_a53_opp_table>;
> > #cooling-cells = <2>;
> > + i-cache-size = <0x8000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <256>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + next-level-cache = <&apollo_l2>;
> > };
> >
> > cpu1: cpu@101 {
> > @@ -72,6 +79,13 @@
> > clock-frequency = <1300000000>;
> > operating-points-v2 = <&cluster_a53_opp_table>;
> > #cooling-cells = <2>;
> > + i-cache-size = <0x8000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <256>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + next-level-cache = <&apollo_l2>;
> > };
> >
> > cpu2: cpu@102 {
> > @@ -82,6 +96,13 @@
> > clock-frequency = <1300000000>;
> > operating-points-v2 = <&cluster_a53_opp_table>;
> > #cooling-cells = <2>;
> > + i-cache-size = <0x8000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <256>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + next-level-cache = <&apollo_l2>;
> > };
> >
> > cpu3: cpu@103 {
> > @@ -92,6 +113,13 @@
> > clock-frequency = <1300000000>;
> > operating-points-v2 = <&cluster_a53_opp_table>;
> > #cooling-cells = <2>;
> > + i-cache-size = <0x8000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <256>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + next-level-cache = <&apollo_l2>;
> > };
> >
> > cpu4: cpu@0 {
> > @@ -104,6 +132,13 @@
> > clock-names = "atlasclk";
> > operating-points-v2 = <&cluster_a57_opp_table>;
> > #cooling-cells = <2>;
> > + i-cache-size = <0xc000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <256>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <256>;
> > + next-level-cache = <&atlas_l2>;
> > };
> >
> > cpu5: cpu@1 {
> > @@ -114,6 +149,13 @@
> > clock-frequency = <1900000000>;
> > operating-points-v2 = <&cluster_a57_opp_table>;
> > #cooling-cells = <2>;
> > + i-cache-size = <0xc000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <256>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <256>;
> > + next-level-cache = <&atlas_l2>;
> > };
> >
> > cpu6: cpu@2 {
> > @@ -124,6 +166,13 @@
> > clock-frequency = <1900000000>;
> > operating-points-v2 = <&cluster_a57_opp_table>;
> > #cooling-cells = <2>;
> > + i-cache-size = <0xc000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <256>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <256>;
> > + next-level-cache = <&atlas_l2>;
> > };
> >
> > cpu7: cpu@3 {
> > @@ -134,6 +183,27 @@
> > clock-frequency = <1900000000>;
> > operating-points-v2 = <&cluster_a57_opp_table>;
> > #cooling-cells = <2>;
> > + i-cache-size = <0xc000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <256>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <256>;
> > + next-level-cache = <&atlas_l2>;
> > + };
> > +
> > + atlas_l2: l2-cache0 {
>
> Few other nodes (PMU, OPP tables) use a57/a53 names instead of
> codenames, so I would prefer to stay with them (so cluster_a57_l2).
>
Thanks for review, will update in next patch set.
> For Exynos7 it's fine as it uses Atlas already in labels.
>
> > + compatible = "cache";
> > + cache-size = <0x200000>;
> > + cache-line-size = <64>;
> > + cache-sets = <2048>;
> > + };
> > +
> > + apollo_l2: l2-cache1 {
> > + compatible = "cache";
> > + cache-size = <0x40000>;
> > + cache-line-size = <64>;
> > + cache-sets = <256>;
> > };
> > };
> >
> >
>
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 4+ messages in thread
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2021-06-17 11:37 ` [PATCH 1/2] arm64: dts: exynos7: Add cpu cache information Alim Akhtar
[not found] ` <CGME20210617113314epcas5p4652e98d24d7f56a7c8461175bbb25456@epcas5p4.samsung.com>
2021-06-17 11:37 ` [PATCH 2/2] arm64: dts: exynos5433: " Alim Akhtar
2021-06-21 8:51 ` Krzysztof Kozlowski
2021-06-21 13:46 ` Alim Akhtar
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