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Mon, 21 Jun 2021 12:02:48 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id B89A93005C7; Mon, 21 Jun 2021 14:02:39 +0200 (CEST) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 0) id 42741235EE38C; Mon, 21 Jun 2021 14:02:39 +0200 (CEST) Message-ID: <20210621120121.491136646@infradead.org> User-Agent: quilt/0.66 Date: Mon, 21 Jun 2021 13:12:47 +0200 From: Peter Zijlstra To: jpoimboe@redhat.com, tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, peterz@infradead.org, joro@8bytes.org, boris.ostrovsky@oracle.com, jgross@suse.com, x86@kernel.org, mbenes@suse.com Subject: [RFC][PATCH 14/18] x86/xen: Make irq_enable() noinstr References: <20210621111233.344964031@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org vmlinux.o: warning: objtool: pv_ops[32]: native_irq_enable vmlinux.o: warning: objtool: pv_ops[32]: __raw_callee_save_xen_irq_enable vmlinux.o: warning: objtool: pv_ops[32]: xen_irq_enable_direct vmlinux.o: warning: objtool: lock_is_held_type()+0xfe: call to pv_ops[32]() leaves .noinstr.text section Signed-off-by: Peter Zijlstra (Intel) --- arch/x86/kernel/paravirt.c | 7 ++++- arch/x86/xen/irq.c | 4 +-- arch/x86/xen/xen-asm.S | 56 ++++++++++++++++++++++----------------------- 3 files changed, 36 insertions(+), 31 deletions(-) --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -258,6 +258,11 @@ static noinstr void pv_native_set_debugr native_set_debugreg(regno, val); } +static noinstr void pv_native_irq_enable(void) +{ + native_irq_enable(); +} + struct paravirt_patch_template pv_ops = { /* Cpu ops. */ .cpu.io_delay = native_io_delay, @@ -302,7 +307,7 @@ struct paravirt_patch_template pv_ops = /* Irq ops. */ .irq.save_fl = __PV_IS_CALLEE_SAVE(native_save_fl), .irq.irq_disable = __PV_IS_CALLEE_SAVE(native_irq_disable), - .irq.irq_enable = __PV_IS_CALLEE_SAVE(native_irq_enable), + .irq.irq_enable = __PV_IS_CALLEE_SAVE(pv_native_irq_enable), .irq.safe_halt = native_safe_halt, .irq.halt = native_halt, #endif /* CONFIG_PARAVIRT_XXL */ --- a/arch/x86/xen/irq.c +++ b/arch/x86/xen/irq.c @@ -53,7 +53,7 @@ asmlinkage __visible void xen_irq_disabl } PV_CALLEE_SAVE_REGS_THUNK(xen_irq_disable); -asmlinkage __visible void xen_irq_enable(void) +asmlinkage __visible noinstr void xen_irq_enable(void) { struct vcpu_info *vcpu; @@ -76,7 +76,7 @@ asmlinkage __visible void xen_irq_enable preempt_enable(); } -PV_CALLEE_SAVE_REGS_THUNK(xen_irq_enable); +__PV_CALLEE_SAVE_REGS_THUNK(xen_irq_enable, ".noinstr.text"); static void xen_safe_halt(void) { --- a/arch/x86/xen/xen-asm.S +++ b/arch/x86/xen/xen-asm.S @@ -22,33 +22,6 @@ #include /* - * Enable events. This clears the event mask and tests the pending - * event status with one and operation. If there are pending events, - * then enter the hypervisor to get them handled. - */ -SYM_FUNC_START(xen_irq_enable_direct) - FRAME_BEGIN - /* Unmask events */ - movb $0, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_mask - - /* - * Preempt here doesn't matter because that will deal with any - * pending interrupts. The pending check may end up being run - * on the wrong CPU, but that doesn't hurt. - */ - - /* Test for pending */ - testb $0xff, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending - jz 1f - - call check_events -1: - FRAME_END - ret -SYM_FUNC_END(xen_irq_enable_direct) - - -/* * Disabling events is simply a matter of making the event mask * non-zero. */ @@ -57,6 +30,8 @@ SYM_FUNC_START(xen_irq_disable_direct) ret SYM_FUNC_END(xen_irq_disable_direct) +.pushsection .noinstr.text, "ax" + /* * Force an event check by making a hypercall, but preserve regs * before making the call. @@ -86,7 +61,32 @@ SYM_FUNC_START(check_events) ret SYM_FUNC_END(check_events) -.pushsection .noinstr.text, "ax" +/* + * Enable events. This clears the event mask and tests the pending + * event status with one and operation. If there are pending events, + * then enter the hypervisor to get them handled. + */ +SYM_FUNC_START(xen_irq_enable_direct) + FRAME_BEGIN + /* Unmask events */ + movb $0, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_mask + + /* + * Preempt here doesn't matter because that will deal with any + * pending interrupts. The pending check may end up being run + * on the wrong CPU, but that doesn't hurt. + */ + + /* Test for pending */ + testb $0xff, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending + jz 1f + + call check_events +1: + FRAME_END + ret +SYM_FUNC_END(xen_irq_enable_direct) + /* * (xen_)save_fl is used to get the current interrupt enable status. * Callers expect the status to be in X86_EFLAGS_IF, and other bits