Re: [RESEND PATCH v4 03/10] KVM: vmx/pmu: Add MSR_ARCH_LBR_DEPTH emulation for Arch LBR

From: Yang Weijiang <weijiang.yang@intel.com>
To: Jim Mattson <jmattson@google.com>
Cc: Like Xu <like.xu@linux.intel.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Sean Christopherson <seanjc@google.com>,
	Vitaly Kuznetsov <vkuznets@redhat.com>,
	Wanpeng Li <wanpengli@tencent.com>,
	Joerg Roedel <joro@8bytes.org>,
	Yang Weijiang <weijiang.yang@intel.com>,
	Wei Wang <wei.w.wang@intel.com>, kvm list <kvm@vger.kernel.org>,
	LKML <linux-kernel@vger.kernel.org>
Subject: Re: [RESEND PATCH v4 03/10] KVM: vmx/pmu: Add MSR_ARCH_LBR_DEPTH emulation for Arch LBR
Date: Thu, 24 Jun 2021 09:31:53 +0800	[thread overview]
Message-ID: <20210624013153.GA15841@intel.com> (raw)
In-Reply-To: <CALMp9eT-KL-xDgV9p31NgnbW2tnwPes7r6GhJbMedim5e9Ab4g@mail.gmail.com>

On Wed, Jun 23, 2021 at 11:03:39AM -0700, Jim Mattson wrote:
> On Mon, May 10, 2021 at 1:16 AM Like Xu <like.xu@linux.intel.com> wrote:
> >
> > The number of Arch LBR entries available for recording operations
> > is dictated by the value in MSR_ARCH_LBR_DEPTH.DEPTH. The supported
> > LBR depth values can be found in CPUID.(EAX=01CH, ECX=0):EAX[7:0]
> > and for each bit "n" set in this field, the MSR_ARCH_LBR_DEPTH.DEPTH
> > value of "8*(n+1)" is supported.
> >
> > On a guest write to MSR_ARCH_LBR_DEPTH, all LBR entries are reset to 0.
> > KVM emulates the reset behavior by introducing lbr_desc->arch_lbr_reset.
> > KVM writes the guest requested value to the native ARCH_LBR_DEPTH MSR
> > (this is safe because the two values will be the same) when the Arch LBR
> > records MSRs are pass-through to the guest.
> >
> > Signed-off-by: Like Xu <like.xu@linux.intel.com>
> > ---
> >  arch/x86/kvm/vmx/pmu_intel.c | 43 ++++++++++++++++++++++++++++++++++++
> >  arch/x86/kvm/vmx/vmx.h       |  3 +++
> >  2 files changed, 46 insertions(+)
> >
> > diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
> > index 9efc1a6b8693..d9c9cb6c9a4b 100644
> > --- a/arch/x86/kvm/vmx/pmu_intel.c
> > +++ b/arch/x86/kvm/vmx/pmu_intel.c
> > @@ -220,6 +220,9 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
> >         case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
> >                 ret = pmu->version > 1;
> >                 break;
> > +       case MSR_ARCH_LBR_DEPTH:
> > +               ret = guest_cpuid_has(vcpu, X86_FEATURE_ARCH_LBR);
> > +               break;
> 
> This doesn't seem like a very safe test, since userspace can provide
> whatever CPUID tables it likes. You should definitely think about
> hardening this code against a malicious userspace.
> 
> When you add a new guest MSR, it should be enumerated by
> KVM_GET_MSR_INDEX_LIST. Otherwise, userspace will not save/restore the
> MSR value on suspend/resume.

Thanks Jim! Will improve this part in next version.