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[2a01:c23:bd64:8b00:f22f:74ff:fe21:725]) by smtp.googlemail.com with ESMTPSA id jz27sm6048861ejc.33.2021.06.27.15.40.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Jun 2021 15:40:17 -0700 (PDT) From: Martin Blumenstingl To: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org Cc: narmstrong@baylibre.com, jbrunet@baylibre.com, khilman@baylibre.com, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Martin Blumenstingl Subject: [PATCH v3 0/3] clk: meson: rounding for fast clocks on 32-bit SoCs Date: Mon, 28 Jun 2021 00:39:56 +0200 Message-Id: <20210627223959.188139-1-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On the 32-bit Amlogic Meson8/8b/8m2 SoCs we run into a problem with the fast HDMI PLL and it's OD (post-dividers). This clock tree can run at up to approx. 3GHz. This however causes a problem, because these rates require BIT(31) to be usable. Unfortunately this is not the case with clk_ops.round_rate on 32-bit systems. BIT(31) is reserved for the sign (+ or -). clk_ops.determine_rate does not suffer from this limitation. It uses an int to signal any errors and can then take all available 32 bits for the clock rate. Changes since v1 from [0]: - reworked the first patch so the the existing divider_{ro_}round_rate_parent implementations are using the new divider_{ro_}determine_rate implementations to avoid code duplication (thanks Jerome for the suggestion) - added a patch to switch the default clk_divider_{ro_}ops to use .determine_rate instead of .round_rate as suggested by Jerome (thanks) - dropped a patch for the Meson PLL ops as these are independent from the divider patches and Jerome has applied that one directly (thanks) - added Jerome's Reviewed-by to the meson clk-regmap patch (thanks!) - dropped the RFC prefix Changes since v2 from [1]: - Added Jerome's Reviewed-by to patches 1 and 2 (thank you!) - fixed typo in the cover letter (availble -> available) [0] https://patchwork.kernel.org/project/linux-clk/cover/20210517203724.1006254-1-martin.blumenstingl@googlemail.com/ [1] https://patchwork.kernel.org/project/linux-clk/cover/20210524103733.554878-1-martin.blumenstingl@googlemail.com/ Martin Blumenstingl (3): clk: divider: Add re-usable determine_rate implementations clk: divider: Switch from .round_rate to .determine_rate by default clk: meson: regmap: switch to determine_rate for the dividers drivers/clk/clk-divider.c | 93 +++++++++++++++++++++++++--------- drivers/clk/meson/clk-regmap.c | 19 ++++--- include/linux/clk-provider.h | 6 +++ 3 files changed, 85 insertions(+), 33 deletions(-) -- 2.32.0