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From: Leo Yan <leo.yan@linaro.org>
To: Arnaldo Carvalho de Melo <acme@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Ingo Molnar <mingo@redhat.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Borislav Petkov <bp@alien8.de>,
	x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
	Mathieu Poirier <mathieu.poirier@linaro.org>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mike Leach <mike.leach@linaro.org>,
	linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
	coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org
Cc: Leo Yan <leo.yan@linaro.org>
Subject: [PATCH v3 03/10] coresight: tmc-etf: Add comment for store ordering
Date: Sun,  4 Jul 2021 15:16:37 +0800	[thread overview]
Message-ID: <20210704071644.107397-4-leo.yan@linaro.org> (raw)
In-Reply-To: <20210704071644.107397-1-leo.yan@linaro.org>

AUX ring buffer is required to separate the data store and aux_head
store, since the function CS_LOCK() has contained memory barrier mb(),
mb() is a more conservative barrier than smp_wmb() on Arm32/Arm64, thus
it's needless to add any explicit barrier anymore.

Add comment to make clear for the barrier usage for ETF.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
 drivers/hwtracing/coresight/coresight-tmc-etf.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index 45b85edfc690..9a42ee689921 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -553,6 +553,12 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev,
 	if (buf->snapshot)
 		handle->head += to_read;
 
+	/*
+	 * AUX ring buffer requires to use memory barrier to separate the trace
+	 * data store and aux_head store, because CS_LOCK() contains mb() which
+	 * gives more heavy barrier than smp_wmb(), it's not necessary to
+	 * explicitly invoke any barrier.
+	 */
 	CS_LOCK(drvdata->base);
 out:
 	spin_unlock_irqrestore(&drvdata->spinlock, flags);
-- 
2.25.1


  parent reply	other threads:[~2021-07-04  7:17 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-04  7:16 [PATCH v3 00/10] perf: Refine barriers for AUX ring buffer Leo Yan
2021-07-04  7:16 ` [PATCH v3 01/10] perf/ring_buffer: Add comment for barriers on " Leo Yan
2021-07-04  7:16 ` [PATCH v3 02/10] coresight: tmc-etr: Add barrier after updating " Leo Yan
2021-07-04  7:16 ` Leo Yan [this message]
2021-07-04  7:16 ` [PATCH v3 04/10] perf/x86: Add barrier after updating bts Leo Yan
2021-07-04  7:16 ` [PATCH v3 05/10] perf auxtrace: Drop legacy __sync functions Leo Yan
2021-07-10 12:34   ` Adrian Hunter
2021-07-11  7:41     ` Leo Yan
2021-07-04  7:16 ` [PATCH v3 06/10] perf auxtrace: Remove auxtrace_mmap__read_snapshot_head() Leo Yan
2021-07-04  7:16 ` [PATCH v3 07/10] perf: Cleanup for HAVE_SYNC_COMPARE_AND_SWAP_SUPPORT Leo Yan
2021-07-10 12:36   ` Adrian Hunter
2021-07-11  8:08     ` Leo Yan
2021-07-04  7:16 ` [PATCH v3 08/10] perf auxtrace: Use WRITE_ONCE() for updating aux_tail Leo Yan
2021-07-04  7:16 ` [PATCH v3 09/10] perf env: Set kernel bit mode Leo Yan
2021-07-04  7:16 ` [PATCH v3 10/10] perf auxtrace: Add compat_auxtrace_mmap__{read_head|write_tail} Leo Yan

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