From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD1BDC07E9C for ; Mon, 5 Jul 2021 07:13:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9BA38613F1 for ; Mon, 5 Jul 2021 07:13:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230007AbhGEHQ3 (ORCPT ); Mon, 5 Jul 2021 03:16:29 -0400 Received: from mga17.intel.com ([192.55.52.151]:47704 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229941AbhGEHQ2 (ORCPT ); Mon, 5 Jul 2021 03:16:28 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10035"; a="189314758" X-IronPort-AV: E=Sophos;i="5.83,325,1616482800"; d="scan'208";a="189314758" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2021 00:13:49 -0700 X-IronPort-AV: E=Sophos;i="5.83,325,1616482800"; d="scan'208";a="422279299" Received: from paasikivi.fi.intel.com ([10.237.72.42]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2021 00:13:46 -0700 Received: from paasikivi.fi.intel.com (localhost [127.0.0.1]) by paasikivi.fi.intel.com (Postfix) with SMTP id BBB5420188; Mon, 5 Jul 2021 10:13:43 +0300 (EEST) Date: Mon, 5 Jul 2021 10:13:43 +0300 From: Sakari Ailus To: Stefan Riedmueller Cc: Laurent Pinchart , Rob Herring , Mauro Carvalho Chehab , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Enrico Scholz Subject: Re: [PATCH v3 1/6] media: mt9p031: Read back the real clock rate Message-ID: <20210705071343.GR3@paasikivi.fi.intel.com> References: <20210702095922.118614-1-s.riedmueller@phytec.de> <20210702095922.118614-2-s.riedmueller@phytec.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210702095922.118614-2-s.riedmueller@phytec.de> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Enrico, On Fri, Jul 02, 2021 at 11:59:17AM +0200, Stefan Riedmueller wrote: > From: Enrico Scholz > > The real and requested clock can differ and because it is used to > calculate PLL values, the real clock rate should be read. Do you have a system where this happens? That suggests there's a wrong value in DT. The preference nowadays is to rely on assigned-clock-rates, even though it's inherently somewhat unreliable, just as clk_set_rate(). This is an existing driver though. The old ones could be kept for compatibility with older DT binaries. > > Signed-off-by: Enrico Scholz > Signed-off-by: Stefan Riedmueller > Reviewed-by: Laurent Pinchart > --- > drivers/media/i2c/mt9p031.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c > index 77567341ec98..3eaaa8d44523 100644 > --- a/drivers/media/i2c/mt9p031.c > +++ b/drivers/media/i2c/mt9p031.c > @@ -255,6 +255,7 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) > > struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); > struct mt9p031_platform_data *pdata = mt9p031->pdata; > + unsigned long ext_freq; > int ret; > > mt9p031->clk = devm_clk_get(&client->dev, NULL); > @@ -265,13 +266,15 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) > if (ret < 0) > return ret; > > + ext_freq = clk_get_rate(mt9p031->clk); > + > /* If the external clock frequency is out of bounds for the PLL use the > * pixel clock divider only and disable the PLL. > */ > - if (pdata->ext_freq > limits.ext_clock_max) { > + if (ext_freq > limits.ext_clock_max) { > unsigned int div; > > - div = DIV_ROUND_UP(pdata->ext_freq, pdata->target_freq); > + div = DIV_ROUND_UP(ext_freq, pdata->target_freq); > div = roundup_pow_of_two(div) / 2; > > mt9p031->clk_div = min_t(unsigned int, div, 64); > @@ -280,7 +283,7 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) > return 0; > } > > - mt9p031->pll.ext_clock = pdata->ext_freq; > + mt9p031->pll.ext_clock = ext_freq; > mt9p031->pll.pix_clock = pdata->target_freq; > mt9p031->use_pll = true; > -- Kind regards, Sakari Ailus