From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-21.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D2F0C07E99 for ; Tue, 6 Jul 2021 03:08:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0228E61986 for ; Tue, 6 Jul 2021 03:08:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229950AbhGFDLZ (ORCPT ); Mon, 5 Jul 2021 23:11:25 -0400 Received: from mail.kernel.org ([198.145.29.99]:39538 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229880AbhGFDLY (ORCPT ); Mon, 5 Jul 2021 23:11:24 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id F0D646197E; Tue, 6 Jul 2021 03:08:43 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner , Marc Zyngier Cc: linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen , Chen Zhu Subject: [PATCH 0/9] irqchip: Add LoongArch-related irqchip drivers Date: Tue, 6 Jul 2021 11:08:55 +0800 Message-Id: <20210706030904.1411775-1-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its boot protocol LoongArch-specific interrupt controllers (similar to APIC) are already added in the next revision of ACPI Specification (current revision is 6.4). This patchset adds some irqchip drivers for LoongArch, it is preparing to add LoongArch support in mainline kernel, we can see a snapshot here: https://github.com/loongson/linux/tree/loongarch-next Cross-compile tool chain to build kernel: https://github.com/loongson/build-tools/releases Loongson and LoongArch documentations: https://github.com/loongson/LoongArch-Documentation LoongArch-specific interrupt controllers: https://mantis.uefi.org/mantis/view.php?id=2203 Huacai Chen and Chen Zhu(9): irqchip: Adjust Kconfig for Loongson. irqchip/loongson-pch-pic: Improve edge triggered interrupt support. irqchip/loongson-pch-pic: Add ACPI init support. irqchip/loongson-pch-msi: Add ACPI init support. irqchip/loongson-htvec: Add ACPI init support. irqchip/loongson-liointc: Add ACPI init support. irqchip: Add LoongArch CPU interrupt controller support. irqchip: Add Loongson Extended I/O interrupt controller. irqchip: Add Loongson PCH LPC controller support. Signed-off-by: Huacai Chen Signed-off-by: Chen Zhu --- drivers/irqchip/Kconfig | 37 +++- drivers/irqchip/Makefile | 3 + drivers/irqchip/irq-loongarch-cpu.c | 87 ++++++++++ drivers/irqchip/irq-loongson-eiointc.c | 308 +++++++++++++++++++++++++++++++++ drivers/irqchip/irq-loongson-htvec.c | 102 ++++++++++- drivers/irqchip/irq-loongson-liointc.c | 140 ++++++++++++++- drivers/irqchip/irq-loongson-pch-lpc.c | 204 ++++++++++++++++++++++ drivers/irqchip/irq-loongson-pch-msi.c | 69 +++++++- drivers/irqchip/irq-loongson-pch-pic.c | 139 ++++++++++++++- include/linux/cpuhotplug.h | 1 + 10 files changed, 1069 insertions(+), 21 deletions(-) create mode 100644 drivers/irqchip/irq-loongarch-cpu.c create mode 100644 drivers/irqchip/irq-loongson-eiointc.c create mode 100644 drivers/irqchip/irq-loongson-pch-lpc.c -- 2.27.0