From: Chun-Jie Chen <chun-jie.chen@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Stephen Boyd <sboyd@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>,
Rob Herring <robh+dt@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <srv_heupstream@mediatek.com>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Weiyi Lu <weiyi.lu@mediatek.com>,
Chun-Jie Chen <chun-jie.chen@mediatek.com>
Subject: [v13 14/21] clk: mediatek: Add MT8192 ipesys clock support
Date: Tue, 6 Jul 2021 14:19:13 +0800 [thread overview]
Message-ID: <20210706061920.16013-15-chun-jie.chen@mediatek.com> (raw)
In-Reply-To: <20210706061920.16013-1-chun-jie.chen@mediatek.com>
Add MT8192 ipesys clock provider
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
drivers/clk/mediatek/Kconfig | 6 +++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-ipe.c | 57 +++++++++++++++++++++++++++
3 files changed, 64 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8192-ipe.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 5becf049d9fa..02e626270ee7 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -532,6 +532,12 @@ config COMMON_CLK_MT8192_IMP_IIC_WRAP
help
This driver supports MediaTek MT8192 imp_iic_wrap clocks.
+config COMMON_CLK_MT8192_IPESYS
+ bool "Clock driver for MediaTek MT8192 ipesys"
+ depends on COMMON_CLK_MT8192
+ help
+ This driver supports MediaTek MT8192 ipesys clocks.
+
config COMMON_CLK_MT8516
bool "Clock driver for MediaTek MT8516"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 37981626b775..33dc974c6638 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -72,5 +72,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
obj-$(CONFIG_COMMON_CLK_MT8192_IMGSYS) += clk-mt8192-img.o
obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP) += clk-mt8192-imp_iic_wrap.o
+obj-$(CONFIG_COMMON_CLK_MT8192_IPESYS) += clk-mt8192-ipe.o
obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8192-ipe.c b/drivers/clk/mediatek/clk-mt8192-ipe.c
new file mode 100644
index 000000000000..730d91b64b3f
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8192-ipe.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 MediaTek Inc.
+// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8192-clk.h>
+
+static const struct mtk_gate_regs ipe_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_IPE(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate ipe_clks[] = {
+ GATE_IPE(CLK_IPE_LARB19, "ipe_larb19", "ipe_sel", 0),
+ GATE_IPE(CLK_IPE_LARB20, "ipe_larb20", "ipe_sel", 1),
+ GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "ipe_sel", 2),
+ GATE_IPE(CLK_IPE_FD, "ipe_fd", "ipe_sel", 3),
+ GATE_IPE(CLK_IPE_FE, "ipe_fe", "ipe_sel", 4),
+ GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "ipe_sel", 5),
+ GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "ipe_sel", 6),
+ GATE_IPE(CLK_IPE_GALS, "ipe_gals", "ipe_sel", 8),
+};
+
+static const struct mtk_clk_desc ipe_desc = {
+ .clks = ipe_clks,
+ .num_clks = ARRAY_SIZE(ipe_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8192_ipe[] = {
+ {
+ .compatible = "mediatek,mt8192-ipesys",
+ .data = &ipe_desc,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_driver clk_mt8192_ipe_drv = {
+ .probe = mtk_clk_simple_probe,
+ .driver = {
+ .name = "clk-mt8192-ipe",
+ .of_match_table = of_match_clk_mt8192_ipe,
+ },
+};
+
+builtin_platform_driver(clk_mt8192_ipe_drv);
--
2.18.0
next prev parent reply other threads:[~2021-07-06 6:21 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-06 6:18 [v13 00/21] Mediatek MT8192 clock support Chun-Jie Chen
2021-07-06 6:19 ` [v13 01/21] dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock Chun-Jie Chen
2021-07-06 6:19 ` [v13 02/21] dt-bindings: ARM: Mediatek: Add mmsys document binding for MT8192 Chun-Jie Chen
2021-07-13 21:49 ` Rob Herring
2021-07-06 6:19 ` [v13 03/21] dt-bindings: ARM: Mediatek: Add audsys " Chun-Jie Chen
2021-07-13 21:50 ` Rob Herring
2021-07-06 6:19 ` [v13 04/21] clk: mediatek: Add dt-bindings of MT8192 clocks Chun-Jie Chen
2021-07-06 6:19 ` [v13 05/21] clk: mediatek: Get regmap without syscon compatible check Chun-Jie Chen
2021-07-27 4:27 ` Ikjoon Jang
2021-07-06 6:19 ` [v13 06/21] clk: mediatek: Fix asymmetrical PLL enable and disable control Chun-Jie Chen
2021-07-06 6:19 ` [v13 07/21] clk: mediatek: Add configurable enable control to mtk_pll_data Chun-Jie Chen
2021-07-06 6:19 ` [v13 08/21] clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers Chun-Jie Chen
2021-07-27 4:27 ` Ikjoon Jang
2021-07-06 6:19 ` [v13 09/21] clk: mediatek: Add MT8192 basic clocks support Chun-Jie Chen
2021-07-06 6:19 ` [v13 10/21] clk: mediatek: Add MT8192 audio clock support Chun-Jie Chen
2021-07-06 6:19 ` [v13 11/21] clk: mediatek: Add MT8192 camsys " Chun-Jie Chen
2021-07-06 6:19 ` [v13 12/21] clk: mediatek: Add MT8192 imgsys " Chun-Jie Chen
2021-07-06 6:19 ` [v13 13/21] clk: mediatek: Add MT8192 imp i2c wrapper " Chun-Jie Chen
2021-07-06 6:19 ` Chun-Jie Chen [this message]
2021-07-06 6:19 ` [v13 15/21] clk: mediatek: Add MT8192 mdpsys " Chun-Jie Chen
2021-07-06 6:19 ` [v13 16/21] clk: mediatek: Add MT8192 mfgcfg " Chun-Jie Chen
2021-07-06 6:19 ` [v13 17/21] clk: mediatek: Add MT8192 mmsys " Chun-Jie Chen
2021-07-06 6:19 ` [v13 18/21] clk: mediatek: Add MT8192 msdc " Chun-Jie Chen
2021-07-06 6:19 ` [v13 19/21] clk: mediatek: Add MT8192 scp adsp " Chun-Jie Chen
2021-07-06 6:19 ` [v13 20/21] clk: mediatek: Add MT8192 vdecsys " Chun-Jie Chen
2021-07-06 6:19 ` [v13 21/21] clk: mediatek: Add MT8192 vencsys " Chun-Jie Chen
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