From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C8CEC11F7A for ; Tue, 6 Jul 2021 11:39:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3191061241 for ; Tue, 6 Jul 2021 11:39:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237591AbhGFLmV (ORCPT ); Tue, 6 Jul 2021 07:42:21 -0400 Received: from mail.kernel.org ([198.145.29.99]:35636 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233212AbhGFLZo (ORCPT ); Tue, 6 Jul 2021 07:25:44 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id D084861D54; Tue, 6 Jul 2021 11:19:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1625570379; bh=lFRZNA2axd6y0gh1OLNz3qNQ8ml1pC4bSsvWlDJIezE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uuDnwozQ1mpDOL9HYaIHzmibBVTPB+81lDiSvUPE/tLcj0O+XM4hrxiJnyI46986/ PnjPkHdRVQdfgZV//Ii3qblwPSesfl5bO7YzqbSiDE6neeoFMY3SWUnuulvsslGIr4 Y7nuk2YxI18YxUtdof0bllAjSO2hXPNbNLtFJ3TYgzdNaWwwgHhqKHQlt3LuqVvwoX mzrUdJrQxvnr2VJ9dHHQNLrKBRbruWlLaFPxYHWLrW5AOYxNDXeKPzEhV0trFj/tF/ LVNsmZF6JxZjtB0hoAhg/9LLzbTc1kACQI2DtVXJybBAgCumgayfqLZMVs59F0V9/N pOiLDdTnCRZIg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Paul Cercueil , Thomas Bogendoerfer , Sasha Levin , linux-mips@vger.kernel.org Subject: [PATCH AUTOSEL 5.12 054/160] MIPS: ingenic: Select CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER Date: Tue, 6 Jul 2021 07:16:40 -0400 Message-Id: <20210706111827.2060499-54-sashal@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210706111827.2060499-1-sashal@kernel.org> References: <20210706111827.2060499-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Paul Cercueil [ Upstream commit eb3849370ae32b571e1f9a63ba52c61adeaf88f7 ] The clock driving the XBurst CPUs in Ingenic SoCs is integer divided from the main PLL. As such, it is possible to control the frequency of the CPU, either by changing the divider, or by changing the rate of the main PLL. The XBurst CPUs also lack the CP0 timer; the TCU, a separate piece of hardware in the SoC, provides this functionality. Signed-off-by: Paul Cercueil Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin --- arch/mips/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e89d63cd92d1..ab73622b14dd 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -425,6 +425,8 @@ config MACH_INGENIC_SOC select MIPS_GENERIC select MACH_INGENIC select SYS_SUPPORTS_ZBOOT_UART16550 + select CPU_SUPPORTS_CPUFREQ + select MIPS_EXTERNAL_TIMER config LANTIQ bool "Lantiq based platforms" -- 2.30.2