From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD5FFC07E95 for ; Wed, 7 Jul 2021 08:49:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C017861CBF for ; Wed, 7 Jul 2021 08:49:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231173AbhGGIvx (ORCPT ); Wed, 7 Jul 2021 04:51:53 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:5574 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231209AbhGGIvw (ORCPT ); Wed, 7 Jul 2021 04:51:52 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1678anIb000467; Wed, 7 Jul 2021 10:48:56 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : references : in-reply-to : content-type : content-transfer-encoding : mime-version; s=selector1; bh=+UHKiuimh8eGcdGlwiV/tjsefnaHThxouA+MIurBhCk=; b=xXLhM1iuO/fkOho6EetbmJpYk9bWVj+574460Ba99eAcXuZI2zDjrKzD6hrMeP9OAcII mys7N2c3np3okzuFPasf1LZUBXsJwc6jTqPTCH0b+ox+WNT0Vaf7wycAlbIDCRPCJjQ4 ytAXwIm5VXf3bFrEquoE9SRauDCx/ZpQH5sOLarVZ48BxXBINaBwwOkmLLJtixedjvd6 DMypjp0wUBu50BeOu5QVDSBtaUUNSEwRCejtOp6rkJQQCMtcbNjKjf4Y3Hks+SUdaBe2 aBgOTUQjxkKFCFbZVA+JtH8m4syotz95wWSr9WGk3iTV6EwJj7V9BIa8J9cUokGCi31s Rg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 39mxgxjw08-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 Jul 2021 10:48:56 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id EAAC510002A; Wed, 7 Jul 2021 10:48:55 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D1B462171D3; Wed, 7 Jul 2021 10:48:55 +0200 (CEST) Received: from SFHDAG2NODE3.st.com (10.75.127.6) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 7 Jul 2021 10:48:55 +0200 Received: from SFHDAG2NODE3.st.com ([fe80::31b3:13bf:2dbe:f64c]) by SFHDAG2NODE3.st.com ([fe80::31b3:13bf:2dbe:f64c%20]) with mapi id 15.00.1497.015; Wed, 7 Jul 2021 10:48:55 +0200 From: Raphael GALLAIS-POU - foss To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Yannick FERTRE - foss , Philippe CORNU - foss , Benjamin Gaignard , Maxime Coquelin , Alexandre TORGUE - foss , Matt Roper , "dri-devel@lists.freedesktop.org" , "linux-kernel@vger.kernel.org" , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" CC: Yannick FERTRE , Philippe CORNU , Raphael GALLAIS-POU - foss , Raphael GALLAIS-POU Subject: [PATCH 2/2] drm/stm: ltdc: add crtc background color property support Thread-Topic: [PATCH 2/2] drm/stm: ltdc: add crtc background color property support Thread-Index: AQHXcwzrULWoh8jFv0qA90zmnYXzxA== Date: Wed, 7 Jul 2021 08:48:55 +0000 Message-ID: <20210707084557.22443-3-raphael.gallais-pou@foss.st.com> References: <20210707084557.22443-1-raphael.gallais-pou@foss.st.com> In-Reply-To: <20210707084557.22443-1-raphael.gallais-pou@foss.st.com> Accept-Language: fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.47] Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.790 definitions=2021-07-07_05:2021-07-06,2021-07-07 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch comes from the need to display small resolution pictures with very few DDR usage. In practice, using a background color, produced by the drm CRTC, around this picture allows to fetch less data in memory than setting a full frame picture. And therefore the picture in DDR is smaller than the size of the screen. It uses the DRM framework background color property and modifies the color to any value between 0x000000 and 0xFFFFFF from userland with a RGB24 value (0x00RRGGBB). Using this feature is observable only if layers are not full screen or if layers use color formats with alpha and are "transparent" at least on some pixels. Depending on the hardware version, the background color can not be properly displayed with non-alpha color formats derived from native alpha color formats (such as XR24 or XR15) since the use of this pixel format generates a non transparent layer. As a workaround, the stage background color of the layer and the general background color need to be synced. Signed-off-by: Raphael Gallais-Pou --- drivers/gpu/drm/stm/ltdc.c | 48 ++++++++++++++++++++++++++++++++++---- 1 file changed, 43 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index 1f9392fb58e1..0aca245288cc 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -196,6 +196,11 @@ =20 #define NB_PF 8 /* Max nb of HW pixel format */ =20 +#define DRM_ARGB_TO_LTDC_RGB24(bgcolor) \ + ((u32)(DRM_ARGB_RED(bgcolor, 8) << 16 \ + | DRM_ARGB_GREEN(bgcolor, 8) << 8 \ + | DRM_ARGB_BLUE(bgcolor, 8))) + enum ltdc_pix_fmt { PF_NONE, /* RGB formats */ @@ -364,6 +369,15 @@ static inline u32 get_pixelformat_without_alpha(u32 dr= m) } } =20 +/* + * All non-alpha color formats derived from native alpha color formats are + * either characterized by a FourCC format code (such as XR24, RX24, BX24.= ..) + */ +static inline u32 is_xrgb(u32 drm) +{ + return ((drm & 'X') =3D=3D 'X' || (drm & ('X' << 8)) =3D=3D ('X' << 8)); +} + static irqreturn_t ltdc_irq_thread(int irq, void *arg) { struct drm_device *ddev =3D arg; @@ -431,7 +445,8 @@ static void ltdc_crtc_atomic_enable(struct drm_crtc *cr= tc, pm_runtime_get_sync(ddev->dev); =20 /* Sets the background color value */ - reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK); + reg_write(ldev->regs, LTDC_BCCR, + DRM_ARGB_TO_LTDC_RGB24(crtc->state->bgcolor)); =20 /* Enable IRQ */ reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); @@ -452,6 +467,9 @@ static void ltdc_crtc_atomic_disable(struct drm_crtc *c= rtc, =20 drm_crtc_vblank_off(crtc); =20 + /* Reset background color */ + reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK); + /* disable IRQ */ reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); =20 @@ -790,6 +808,7 @@ static void ltdc_plane_atomic_update(struct drm_plane *= plane, u32 y1 =3D newstate->crtc_y + newstate->crtc_h - 1; u32 src_x, src_y, src_w, src_h; u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr; + u32 bgcolor =3D DRM_ARGB_TO_LTDC_RGB24(newstate->crtc->state->bgcolor); enum ltdc_pix_fmt pf; =20 if (!newstate->crtc || !fb) { @@ -853,10 +872,28 @@ static void ltdc_plane_atomic_update(struct drm_plane= *plane, if (!fb->format->has_alpha) val =3D BF1_CA | BF2_1CA; =20 - /* Manage hw-specific capabilities */ - if (ldev->caps.non_alpha_only_l1 && - plane->type !=3D DRM_PLANE_TYPE_PRIMARY) - val =3D BF1_PAXCA | BF2_1PAXCA; + /* + * Manage hw-specific capabilities + * + * Depending on the hardware version, the background color can not be + * properly displayed with non-alpha color formats derived from native + * alpha color formats (such as XR24 or XR15) since the use of this + * pixel format generates a non transparent layer. As a workaround, + * the stage background color of the layer and the general background + * color need to be synced. + * + * This is done by activating for all XRGB color format the default + * color as the background color and then setting blending factor + * accordingly. + */ + if (ldev->caps.non_alpha_only_l1) { + if (is_xrgb(fb->format->format)) { + val =3D BF1_CA | BF2_1CA; + reg_write(ldev->regs, LTDC_L1DCCR + lofs, bgcolor); + } else { + val =3D BF1_PAXCA | BF2_1PAXCA; + } + } =20 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs, LXBFCR_BF2 | LXBFCR_BF1, val); @@ -1033,6 +1070,7 @@ static int ltdc_crtc_init(struct drm_device *ddev, st= ruct drm_crtc *crtc) =20 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); =20 + drm_crtc_add_bgcolor_property(crtc); drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); =20 --=20 2.17.1