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From: <kostap@marvell.com>
To: <miquel.raynal@bootlin.com>, <kishon@ti.com>, <vkoul@kernel.org>,
	<robh+dt@kernel.org>, <andrew@lunn.ch>,
	<gregory.clement@bootlin.com>, <sebastian.hesselbarth@gmail.com>,
	<vladimir.vid@sartura.hr>, <luka.kovacic@sartura.hr>,
	<linux-phy@lists.infradead.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>
Cc: <mw@semihalf.com>, <jaz@semihalf.com>, <nadavh@marvell.com>,
	<stefanc@marvell.com>, <bpeled@marvell.com>,
	Konstantin Porotchkin <kostap@marvell.com>
Subject: [PATCH v7 5/5] arch/arm64: dts: change 10gbase-kr to 10gbase-r in Armada
Date: Thu, 8 Jul 2021 15:46:12 +0300	[thread overview]
Message-ID: <20210708124612.30742-6-kostap@marvell.com> (raw)
In-Reply-To: <20210708124612.30742-1-kostap@marvell.com>

From: Konstantin Porotchkin <kostap@marvell.com>

Change all 10G port modes in Armada family device trees from
10gbase-kr to 10gbase-r

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Suggested-by: Russell King <linux@armlinux.org.uk>
---
 arch/arm64/boot/dts/marvell/armada-7040-db.dts | 2 +-
 arch/arm64/boot/dts/marvell/armada-8040-db.dts | 4 ++--
 arch/arm64/boot/dts/marvell/cn9130-crb.dtsi    | 2 +-
 arch/arm64/boot/dts/marvell/cn9130-db.dtsi     | 2 +-
 arch/arm64/boot/dts/marvell/cn9131-db.dtsi     | 2 +-
 arch/arm64/boot/dts/marvell/cn9132-db.dtsi     | 2 +-
 6 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 51f3e2907597..cd326fe224ce 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -282,7 +282,7 @@
 &cp0_eth0 {
 	status = "okay";
 	/* Network PHY */
-	phy-mode = "10gbase-kr";
+	phy-mode = "10gbase-r";
 	/* Generic PHY, providing serdes lanes */
 	phys = <&cp0_comphy2 0>;
 
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index e39e1efc95b6..f2e8e0df8865 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -195,7 +195,7 @@
 
 &cp0_eth0 {
 	status = "okay";
-	phy-mode = "10gbase-kr";
+	phy-mode = "10gbase-r";
 
 	fixed-link {
 		speed = <10000>;
@@ -348,7 +348,7 @@
 
 &cp1_eth0 {
 	status = "okay";
-	phy-mode = "10gbase-kr";
+	phy-mode = "10gbase-r";
 
 	fixed-link {
 		speed = <10000>;
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
index 75933477324a..9f0efcdacdf1 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
@@ -202,7 +202,7 @@
 &cp0_eth0 {
 	/* This port is connected to 88E6393X switch */
 	status = "okay";
-	phy-mode = "10gbase-kr";
+	phy-mode = "10gbase-r";
 	managed = "in-band-status";
 	phys = <&cp0_comphy4 0>;
 };
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
index 39fc90716454..2cd4bb09e8ff 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
@@ -126,7 +126,7 @@
 /* SLM-1521-V2, CON9 */
 &cp0_eth0 {
 	status = "okay";
-	phy-mode = "10gbase-kr";
+	phy-mode = "10gbase-r";
 	/* Generic PHY, providing serdes lanes */
 	phys = <&cp0_comphy4 0>;
 	managed = "in-band-status";
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
index daddab638fb8..f995b1bcda01 100644
--- a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
@@ -85,7 +85,7 @@
 /* CON50 */
 &cp1_eth0 {
 	status = "okay";
-	phy-mode = "10gbase-kr";
+	phy-mode = "10gbase-r";
 	/* Generic PHY, providing serdes lanes */
 	phys = <&cp1_comphy4 0>;
 	managed = "in-band-status";
diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi
index 5948de6b4638..3f1795fb4fe7 100644
--- a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi
@@ -103,7 +103,7 @@
 /* SLM-1521-V2, CON9 */
 &cp2_eth0 {
 	status = "disabled";
-	phy-mode = "10gbase-kr";
+	phy-mode = "10gbase-r";
 	/* Generic PHY, providing serdes lanes */
 	phys = <&cp2_comphy4 0>;
 	managed = "in-band-status";
-- 
2.17.1


  parent reply	other threads:[~2021-07-08 12:46 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-08 12:46 [PATCH v7 0/5] DTS updates for Marvell Armada CN913x platforms kostap
2021-07-08 12:46 ` [PATCH v7 1/5] arch/arm64/boot/dts/marvell: fix NAND partitioning scheme kostap
2021-07-08 12:46 ` [PATCH v7 2/5] arm64: dts: cn913x: add device trees for topology B boards kostap
2021-07-08 12:46 ` [PATCH v7 3/5] dts: marvell: Enable 10G interfaces on 9130-DB and 9131-DB boards kostap
2021-07-08 12:46 ` [PATCH v7 4/5] arm64: dts: add support for Marvell cn9130-crb platform kostap
2021-07-08 12:46 ` kostap [this message]
2021-07-08 13:47   ` [PATCH v7 5/5] arch/arm64: dts: change 10gbase-kr to 10gbase-r in Armada Russell King (Oracle)
2021-07-23 12:58 ` [PATCH v7 0/5] DTS updates for Marvell Armada CN913x platforms Gregory CLEMENT

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