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* [RFC PATCH 0/4] split rk3568 and rk3566 device trees
@ 2021-07-10 15:10 Peter Geis
  2021-07-10 15:10 ` [RFC PATCH 1/4] arm64: dts: rockchip: move rk3568 dtsi to rk356x dtsi Peter Geis
                   ` (4 more replies)
  0 siblings, 5 replies; 9+ messages in thread
From: Peter Geis @ 2021-07-10 15:10 UTC (permalink / raw)
  To: Rob Herring, Heiko Stuebner, Liang Chen
  Cc: linux-arm-kernel, devicetree, linux-rockchip, linux-kernel, Peter Geis

This is an example patch set that addresses the split of the rk3568 and
rk3566 soc device trees.
This method attempts to avoid deleting and modifing nodes by maintaining
a common dtsi for all common items and adding in the differences in
separate dtsi files.
It also includes a basic dts for the Pine64 Quartz64 Model A board
as an example of a rk3566 device.

This series has the following prerequisite:
arm64: dts: rockchip: add pmu and qos nodes for rk3568
https://patchwork.kernel.org/project/linux-rockchip/patch/20210624114719.1685-4-cl@rock-chips.com/

Peter Geis (4):
  arm64: dts: rockchip: move rk3568 dtsi to rk356x dtsi
  arm64: dts: rockchip: split rk3568 device tree
  arm64: dts: rockchip: add rk3566 dtsi
  arm64: dts: rockchip: add basic dts for Pine64 Quartz64-A

 .../devicetree/bindings/arm/rockchip.yaml     |   5 +
 arch/arm64/boot/dts/rockchip/Makefile         |   1 +
 .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 321 +++++++
 arch/arm64/boot/dts/rockchip/rk3566.dtsi      |  20 +
 arch/arm64/boot/dts/rockchip/rk3568.dtsi      | 814 +-----------------
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      | 786 +++++++++++++++++
 6 files changed, 1153 insertions(+), 794 deletions(-)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3566.dtsi
 create mode 100644 arch/arm64/boot/dts/rockchip/rk356x.dtsi

-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [RFC PATCH 1/4] arm64: dts: rockchip: move rk3568 dtsi to rk356x dtsi
  2021-07-10 15:10 [RFC PATCH 0/4] split rk3568 and rk3566 device trees Peter Geis
@ 2021-07-10 15:10 ` Peter Geis
  2021-07-10 15:10 ` [RFC PATCH 2/4] arm64: dts: rockchip: split rk3568 device tree Peter Geis
                   ` (3 subsequent siblings)
  4 siblings, 0 replies; 9+ messages in thread
From: Peter Geis @ 2021-07-10 15:10 UTC (permalink / raw)
  To: Rob Herring, Heiko Stuebner, Liang Chen
  Cc: linux-arm-kernel, devicetree, linux-rockchip, linux-kernel, Peter Geis

In preparation for separating the rk3568 and rk3566 device trees, move
the base rk3568 dtsi to rk356x dtsi.
This will allow us to strip out the rk3568 specific nodes.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/{rk3568.dtsi => rk356x.dtsi} | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename arch/arm64/boot/dts/rockchip/{rk3568.dtsi => rk356x.dtsi} (100%)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
similarity index 100%
rename from arch/arm64/boot/dts/rockchip/rk3568.dtsi
rename to arch/arm64/boot/dts/rockchip/rk356x.dtsi
-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [RFC PATCH 2/4] arm64: dts: rockchip: split rk3568 device tree
  2021-07-10 15:10 [RFC PATCH 0/4] split rk3568 and rk3566 device trees Peter Geis
  2021-07-10 15:10 ` [RFC PATCH 1/4] arm64: dts: rockchip: move rk3568 dtsi to rk356x dtsi Peter Geis
@ 2021-07-10 15:10 ` Peter Geis
  2021-07-10 15:10 ` [RFC PATCH 3/4] arm64: dts: rockchip: add rk3566 dtsi Peter Geis
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 9+ messages in thread
From: Peter Geis @ 2021-07-10 15:10 UTC (permalink / raw)
  To: Rob Herring, Heiko Stuebner, Liang Chen
  Cc: linux-arm-kernel, devicetree, linux-rockchip, linux-kernel, Peter Geis

In preparation for the rk3566 inclusion, split apart the rk3568 specific
nodes into a separate device tree.
This allows us to create the rk3566 device tree without deleting nodes.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi | 48 ++++++++++++++++++++++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 36 ------------------
 2 files changed, 48 insertions(+), 36 deletions(-)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
new file mode 100644
index 000000000000..da01a59f6f26
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include "rk356x.dtsi"
+
+/ {
+	compatible = "rockchip,rk3568";
+
+	qos_pcie3x1: qos@fe190080 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x0 0xfe190080 0x0 0x20>;
+	};
+
+	qos_pcie3x2: qos@fe190100 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x0 0xfe190100 0x0 0x20>;
+	};
+
+	qos_sata0: qos@fe190200 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x0 0xfe190200 0x0 0x20>;
+	};
+};
+
+&cpu0_opp_table {
+	opp-1992000000 {
+		opp-hz = /bits/ 64 <1992000000>;
+		opp-microvolt = <1150000 1150000 1150000>;
+	};
+};
+
+&power {
+	power-domain@RK3568_PD_PIPE {
+		reg = <RK3568_PD_PIPE>;
+		clocks = <&cru PCLK_PIPE>;
+		pm_qos = <&qos_pcie2x1>,
+			 <&qos_pcie3x1>,
+			 <&qos_pcie3x2>,
+			 <&qos_sata0>,
+			 <&qos_sata1>,
+			 <&qos_sata2>,
+			 <&qos_usb3_0>,
+			 <&qos_usb3_1>;
+		#power-domain-cells = <0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 2737f26775ff..fb4ae22b827a 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -13,8 +13,6 @@
 #include <dt-bindings/thermal/thermal.h>
 
 / {
-	compatible = "rockchip,rk3568";
-
 	interrupt-parent = <&gic>;
 	#address-cells = <2>;
 	#size-cells = <2>;
@@ -121,11 +119,6 @@ opp-1800000000 {
 			opp-hz = /bits/ 64 <1800000000>;
 			opp-microvolt = <1050000 1050000 1150000>;
 		};
-
-		opp-1992000000 {
-			opp-hz = /bits/ 64 <1992000000>;
-			opp-microvolt = <1150000 1150000 1150000>;
-		};
 	};
 
 	firmware {
@@ -334,20 +327,6 @@ power-domain@RK3568_PD_RKVENC {
 					 <&qos_rkvenc_wr_m0>;
 				#power-domain-cells = <0>;
 			};
-
-			power-domain@RK3568_PD_PIPE {
-				reg = <RK3568_PD_PIPE>;
-				clocks = <&cru PCLK_PIPE>;
-				pm_qos = <&qos_pcie2x1>,
-					 <&qos_pcie3x1>,
-					 <&qos_pcie3x2>,
-					 <&qos_sata0>,
-					 <&qos_sata1>,
-					 <&qos_sata2>,
-					 <&qos_usb3_0>,
-					 <&qos_usb3_1>;
-				#power-domain-cells = <0>;
-			};
 		};
 	};
 
@@ -431,21 +410,6 @@ qos_pcie2x1: qos@fe190000 {
 		reg = <0x0 0xfe190000 0x0 0x20>;
 	};
 
-	qos_pcie3x1: qos@fe190080 {
-		compatible = "rockchip,rk3568-qos", "syscon";
-		reg = <0x0 0xfe190080 0x0 0x20>;
-	};
-
-	qos_pcie3x2: qos@fe190100 {
-		compatible = "rockchip,rk3568-qos", "syscon";
-		reg = <0x0 0xfe190100 0x0 0x20>;
-	};
-
-	qos_sata0: qos@fe190200 {
-		compatible = "rockchip,rk3568-qos", "syscon";
-		reg = <0x0 0xfe190200 0x0 0x20>;
-	};
-
 	qos_sata1: qos@fe190280 {
 		compatible = "rockchip,rk3568-qos", "syscon";
 		reg = <0x0 0xfe190280 0x0 0x20>;
-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [RFC PATCH 3/4] arm64: dts: rockchip: add rk3566 dtsi
  2021-07-10 15:10 [RFC PATCH 0/4] split rk3568 and rk3566 device trees Peter Geis
  2021-07-10 15:10 ` [RFC PATCH 1/4] arm64: dts: rockchip: move rk3568 dtsi to rk356x dtsi Peter Geis
  2021-07-10 15:10 ` [RFC PATCH 2/4] arm64: dts: rockchip: split rk3568 device tree Peter Geis
@ 2021-07-10 15:10 ` Peter Geis
  2021-07-10 15:10 ` [RFC PATCH 4/4] arm64: dts: rockchip: add basic dts for Pine64 Quartz64-A Peter Geis
  2021-07-23 12:02 ` [RFC PATCH 0/4] split rk3568 and rk3566 device trees Heiko Stuebner
  4 siblings, 0 replies; 9+ messages in thread
From: Peter Geis @ 2021-07-10 15:10 UTC (permalink / raw)
  To: Rob Herring, Heiko Stuebner, Liang Chen
  Cc: linux-arm-kernel, devicetree, linux-rockchip, linux-kernel, Peter Geis

Add the rk3566 dtsi which includes the soc specific changes for this
chip.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3566.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3566.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
new file mode 100644
index 000000000000..3839eef5e4f7
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x.dtsi"
+
+/ {
+	compatible = "rockchip,rk3566";
+};
+
+&power {
+	power-domain@RK3568_PD_PIPE {
+		reg = <RK3568_PD_PIPE>;
+		clocks = <&cru PCLK_PIPE>;
+		pm_qos = <&qos_pcie2x1>,
+			 <&qos_sata1>,
+			 <&qos_sata2>,
+			 <&qos_usb3_0>,
+			 <&qos_usb3_1>;
+		#power-domain-cells = <0>;
+	};
+};
-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [RFC PATCH 4/4] arm64: dts: rockchip: add basic dts for Pine64 Quartz64-A
  2021-07-10 15:10 [RFC PATCH 0/4] split rk3568 and rk3566 device trees Peter Geis
                   ` (2 preceding siblings ...)
  2021-07-10 15:10 ` [RFC PATCH 3/4] arm64: dts: rockchip: add rk3566 dtsi Peter Geis
@ 2021-07-10 15:10 ` Peter Geis
  2021-07-15 16:21   ` Rob Herring
  2021-07-23 12:02 ` [RFC PATCH 0/4] split rk3568 and rk3566 device trees Heiko Stuebner
  4 siblings, 1 reply; 9+ messages in thread
From: Peter Geis @ 2021-07-10 15:10 UTC (permalink / raw)
  To: Rob Herring, Heiko Stuebner, Liang Chen
  Cc: linux-arm-kernel, devicetree, linux-rockchip, linux-kernel, Peter Geis

Add a basic dts for the Pine64 Quartz64 Model A Single Board Computer.
This board outputs on uart2 for debug.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 .../devicetree/bindings/arm/rockchip.yaml     |   5 +
 arch/arm64/boot/dts/rockchip/Makefile         |   1 +
 .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 321 ++++++++++++++++++
 3 files changed, 327 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts

diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 6546b015fc62..652e40c309bd 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -455,6 +455,11 @@ properties:
           - const: pine64,rockpro64
           - const: rockchip,rk3399
 
+      - description: Pine64 Quartz64 Model A
+        items:
+          - const: pine64,quartz64-a
+          - const: rockchip,rk3566
+
       - description: Radxa Rock
         items:
           - const: radxa,rock
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 7fdb41de01ec..a1f4351be166 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -51,4 +51,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
new file mode 100644
index 000000000000..42dc21f2b350
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566.dtsi"
+
+/ {
+	model = "Pine64 RK3566 Quartz64-A Board";
+	compatible = "pine64,quartz64-a", "rockchip,rk3566";
+
+	aliases {
+		mmc1 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	vcc12v_dcin: vcc12v_dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	/* vbus feeds the rk817 usb input.
+	 * With no battery attached, also feeds vcc_bat+
+	 * via ON/OFF_BAT jumper
+	 */
+	vbus: vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_usb: vcc5v0_usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	/* sourced from vbus and vcc_bat+ via rk817 sw5 */
+	vcc_sys: vcc_sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <4400000>;
+		regulator-max-microvolt = <4400000>;
+		vin-supply = <&vbus>;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk817: pmic@20 {
+		compatible = "rockchip,rk817";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+		#clock-cells = <1>;
+
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc5-supply = <&vcc_sys>;
+		vcc6-supply = <&vcc_sys>;
+		vcc7-supply = <&vcc_sys>;
+		vcc8-supply = <&vcc_sys>;
+		vcc9-supply = <&dcdc_boost>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_logic";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_gpu";
+					regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc_ddr";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_3v3: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc_3v3";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_acodec";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc_1v8: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc1v8_dvp";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc2v8_dvp: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-name = "vcc2v8_dvp";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			dcdc_boost: BOOST {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5000000>;
+				regulator-name = "boost";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			otg_switch: OTG_SWITCH {
+				regulator-name = "otg_switch";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&pinctrl {
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [RFC PATCH 4/4] arm64: dts: rockchip: add basic dts for Pine64 Quartz64-A
  2021-07-10 15:10 ` [RFC PATCH 4/4] arm64: dts: rockchip: add basic dts for Pine64 Quartz64-A Peter Geis
@ 2021-07-15 16:21   ` Rob Herring
  2021-07-20 16:19     ` Peter Geis
  0 siblings, 1 reply; 9+ messages in thread
From: Rob Herring @ 2021-07-15 16:21 UTC (permalink / raw)
  To: Peter Geis
  Cc: Heiko Stuebner, linux-rockchip, Rob Herring, linux-kernel,
	linux-arm-kernel, Liang Chen, devicetree

On Sat, 10 Jul 2021 11:10:34 -0400, Peter Geis wrote:
> Add a basic dts for the Pine64 Quartz64 Model A Single Board Computer.
> This board outputs on uart2 for debug.
> 
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
>  .../devicetree/bindings/arm/rockchip.yaml     |   5 +
>  arch/arm64/boot/dts/rockchip/Makefile         |   1 +
>  .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 321 ++++++++++++++++++
>  3 files changed, 327 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [RFC PATCH 4/4] arm64: dts: rockchip: add basic dts for Pine64 Quartz64-A
  2021-07-15 16:21   ` Rob Herring
@ 2021-07-20 16:19     ` Peter Geis
  2021-07-28 17:25       ` Rob Herring
  0 siblings, 1 reply; 9+ messages in thread
From: Peter Geis @ 2021-07-20 16:19 UTC (permalink / raw)
  To: Rob Herring
  Cc: Heiko Stuebner, open list:ARM/Rockchip SoC...,
	Rob Herring, Linux Kernel Mailing List, arm-mail-list,
	Liang Chen, devicetree

On Thu, Jul 15, 2021 at 12:21 PM Rob Herring <robh@kernel.org> wrote:
>
> On Sat, 10 Jul 2021 11:10:34 -0400, Peter Geis wrote:
> > Add a basic dts for the Pine64 Quartz64 Model A Single Board Computer.
> > This board outputs on uart2 for debug.
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> >  .../devicetree/bindings/arm/rockchip.yaml     |   5 +
> >  arch/arm64/boot/dts/rockchip/Makefile         |   1 +
> >  .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 321 ++++++++++++++++++
> >  3 files changed, 327 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> >
>
> Acked-by: Rob Herring <robh@kernel.org>

Thank you!
I need to split the dt-bindings out into a separate patch, and the
quartz64-a dts has some mild changes.
Are you okay with me using your ack still?

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [RFC PATCH 0/4] split rk3568 and rk3566 device trees
  2021-07-10 15:10 [RFC PATCH 0/4] split rk3568 and rk3566 device trees Peter Geis
                   ` (3 preceding siblings ...)
  2021-07-10 15:10 ` [RFC PATCH 4/4] arm64: dts: rockchip: add basic dts for Pine64 Quartz64-A Peter Geis
@ 2021-07-23 12:02 ` Heiko Stuebner
  4 siblings, 0 replies; 9+ messages in thread
From: Heiko Stuebner @ 2021-07-23 12:02 UTC (permalink / raw)
  To: Rob Herring, Peter Geis, Liang Chen
  Cc: Heiko Stuebner, devicetree, linux-kernel, linux-rockchip,
	linux-arm-kernel

On Sat, 10 Jul 2021 11:10:30 -0400, Peter Geis wrote:
> This is an example patch set that addresses the split of the rk3568 and
> rk3566 soc device trees.
> This method attempts to avoid deleting and modifing nodes by maintaining
> a common dtsi for all common items and adding in the differences in
> separate dtsi files.
> It also includes a basic dts for the Pine64 Quartz64 Model A board
> as an example of a rk3566 device.
> 
> [...]

Applied, thanks!

[1/4] arm64: dts: rockchip: move rk3568 dtsi to rk356x dtsi
      commit: 94c75b5265fe899391e298eace826e4f8d1e8e40
[2/4] arm64: dts: rockchip: split rk3568 device tree
      commit: 92eb5ffbae440700dd38378e24d8091fe166c352
[3/4] arm64: dts: rockchip: add rk3566 dtsi
      commit: 04e1ecf6099cc3ba17c2d4279c968a656320cd12
[4/4] arm64: dts: rockchip: add basic dts for Pine64 Quartz64-A
      commit: c95414d68f116462acf9622f715b8a568bb1dd00

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [RFC PATCH 4/4] arm64: dts: rockchip: add basic dts for Pine64 Quartz64-A
  2021-07-20 16:19     ` Peter Geis
@ 2021-07-28 17:25       ` Rob Herring
  0 siblings, 0 replies; 9+ messages in thread
From: Rob Herring @ 2021-07-28 17:25 UTC (permalink / raw)
  To: Peter Geis
  Cc: Heiko Stuebner, open list:ARM/Rockchip SoC...,
	Linux Kernel Mailing List, arm-mail-list, Liang Chen, devicetree

On Tue, Jul 20, 2021 at 10:19 AM Peter Geis <pgwipeout@gmail.com> wrote:
>
> On Thu, Jul 15, 2021 at 12:21 PM Rob Herring <robh@kernel.org> wrote:
> >
> > On Sat, 10 Jul 2021 11:10:34 -0400, Peter Geis wrote:
> > > Add a basic dts for the Pine64 Quartz64 Model A Single Board Computer.
> > > This board outputs on uart2 for debug.
> > >
> > > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > > ---
> > >  .../devicetree/bindings/arm/rockchip.yaml     |   5 +
> > >  arch/arm64/boot/dts/rockchip/Makefile         |   1 +
> > >  .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 321 ++++++++++++++++++
> > >  3 files changed, 327 insertions(+)
> > >  create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> > >
> >
> > Acked-by: Rob Herring <robh@kernel.org>
>
> Thank you!
> I need to split the dt-bindings out into a separate patch, and the
> quartz64-a dts has some mild changes.
> Are you okay with me using your ack still?

Yes.

Rob

^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2021-07-28 17:25 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-10 15:10 [RFC PATCH 0/4] split rk3568 and rk3566 device trees Peter Geis
2021-07-10 15:10 ` [RFC PATCH 1/4] arm64: dts: rockchip: move rk3568 dtsi to rk356x dtsi Peter Geis
2021-07-10 15:10 ` [RFC PATCH 2/4] arm64: dts: rockchip: split rk3568 device tree Peter Geis
2021-07-10 15:10 ` [RFC PATCH 3/4] arm64: dts: rockchip: add rk3566 dtsi Peter Geis
2021-07-10 15:10 ` [RFC PATCH 4/4] arm64: dts: rockchip: add basic dts for Pine64 Quartz64-A Peter Geis
2021-07-15 16:21   ` Rob Herring
2021-07-20 16:19     ` Peter Geis
2021-07-28 17:25       ` Rob Herring
2021-07-23 12:02 ` [RFC PATCH 0/4] split rk3568 and rk3566 device trees Heiko Stuebner

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