[PATCH v5 0/3] Add DT bindings and DT nodes for USB in SC7280

[PATCH v5 0/3] Add DT bindings and DT nodes for USB in SC7280

[Sandeep Maheswaram]

This series includes usb controller and phy binding updates
for SC7280 SoC and DT chnages for SC7280 SoC and SC7280 IDP board.

changes in v5:
 Added patch for usb3-dp phy bindings for SC7280.
 Changed qmp usb phy to usb dp phy combo node as per Stephen's comments.
 Changed dwc to usb and added SC7280 compatible as per Bjorn's comments.

changes in v4:
 changed usb3-phy to lanes in qmp phy node as it was causing probe failure.

changes in v3:
  Moved the board specific changes to separate patch.
  Addressed comments from Matthias in v2.

changes in v2:
  Dropped dt bindings patches as they are already merged in linux-next.
  Addressed comments from Matthias in v1.

Sandeep Maheswaram (3):
  dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7280
  arm64: dts: qcom: sc7280: Add USB related nodes
  arm64: dts: qcom: sc7280: Add USB nodes for IDP board

 .../bindings/phy/qcom,qmp-usb3-dp-phy.yaml         |   1 +
 arch/arm64/boot/dts/qcom/sc7280-idp.dts            |  39 +++++
 arch/arm64/boot/dts/qcom/sc7280.dtsi               | 164 +++++++++++++++++++++
 3 files changed, 204 insertions(+)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v5 1/3] dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7280

[Sandeep Maheswaram]

Add compatible for SC7280 in QMP USB3 DP PHY bindings.

Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
---
 Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
index 217aa6c..2019983 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
@@ -14,6 +14,7 @@ properties:
   compatible:
     enum:
       - qcom,sc7180-qmp-usb3-dp-phy
+      - qcom,sc7280-qmp-usb3-dp-phy
       - qcom,sdm845-qmp-usb3-dp-phy
       - qcom,sm8250-qmp-usb3-dp-phy
   reg:
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v5 1/3] dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7280

[Stephen Boyd]

Quoting Sandeep Maheswaram (2021-07-06 06:00:11)
> Add compatible for SC7280 in QMP USB3 DP PHY bindings.
>
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

Re: [PATCH v5 1/3] dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7280

[Rob Herring]

On Tue, 06 Jul 2021 18:30:11 +0530, Sandeep Maheswaram wrote:
> Add compatible for SC7280 in QMP USB3 DP PHY bindings.
> 
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> ---
>  Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH v5 2/3] arm64: dts: qcom: sc7280: Add USB related nodes

[Sandeep Maheswaram]

Add nodes for DWC3 USB controller, QMP and HS USB PHYs in sc7280 SOC.

Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
---
Changed qmp usb phy to usb dp phy combo node as per Stephen's comments.
Changed dwc to usb and added SC7280 compatible as per Bjorn's comments.

 arch/arm64/boot/dts/qcom/sc7280.dtsi | 164 +++++++++++++++++++++++++++++++++++
 1 file changed, 164 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index a8c274a..cd6908f 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1035,6 +1035,125 @@
 			};
 		};
 
+		usb_1_hsphy: phy@88e3000 {
+			compatible = "qcom,sc7280-usb-hs-phy",
+				     "qcom,usb-snps-hs-7nm-phy";
+			reg = <0 0x088e3000 0 0x400>;
+			status = "disabled";
+			#phy-cells = <0>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "ref";
+
+			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+		};
+
+		usb_2_hsphy: phy@88e4000 {
+			compatible = "qcom,sc7280-usb-hs-phy",
+				     "qcom,usb-snps-hs-7nm-phy";
+			reg = <0 0x088e4000 0 0x400>;
+			status = "disabled";
+			#phy-cells = <0>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "ref";
+
+			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+		};
+
+		usb_1_qmpphy: phy-wrapper@88e9000 {
+			compatible = "qcom,sc7280-qmp-usb3-dp-phy",
+				     "qcom,sm8250-qmp-usb3-dp-phy";
+			reg = <0 0x088e9000 0 0x200>,
+			      <0 0x088e8000 0 0x40>,
+			      <0 0x088ea000 0 0x200>;
+			status = "disabled";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+			clock-names = "aux", "ref_clk_src", "com_aux";
+
+			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
+			reset-names = "phy", "common";
+
+			usb_1_ssphy: usb3-phy@88e9200 {
+				reg = <0 0x088e9200 0 0x200>,
+				      <0 0x088e9400 0 0x200>,
+				      <0 0x088e9c00 0 0x400>,
+				      <0 0x088e9600 0 0x200>,
+				      <0 0x088e9800 0 0x200>,
+				      <0 0x088e9a00 0 0x100>;
+				#clock-cells = <0>;
+				#phy-cells = <0>;
+				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+				clock-names = "pipe0";
+				clock-output-names = "usb3_phy_pipe_clk_src";
+			};
+
+			dp_phy: dp-phy@88ea200 {
+				reg = <0 0x088ea200 0 0x200>,
+				      <0 0x088ea400 0 0x200>,
+				      <0 0x088eac00 0 0x400>,
+				      <0 0x088ea600 0 0x200>,
+				      <0 0x088ea800 0 0x200>,
+				      <0 0x088eaa00 0 0x100>;
+				#phy-cells = <0>;
+				#clock-cells = <1>;
+				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+				clock-names = "pipe0";
+				clock-output-names = "usb3_phy_pipe_clk_src";
+			};
+		};
+
+		usb_2: usb@8cf8800 {
+			compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
+			reg = <0 0x08cf8800 0 0x400>;
+			status = "disabled";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			dma-ranges;
+
+			clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+				 <&gcc GCC_USB30_SEC_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+				 <&gcc GCC_USB30_SEC_SLEEP_CLK>;
+			clock-names = "cfg_noc", "core", "iface","mock_utmi",
+				      "sleep";
+
+			assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB30_SEC_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <200000000>;
+
+			interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pdc 13 IRQ_TYPE_EDGE_RISING>,
+				     <&pdc 12 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "hs_phy_irq",
+					  "dm_hs_phy_irq", "dp_hs_phy_irq";
+
+			power-domains = <&gcc GCC_USB30_SEC_GDSC>;
+
+			resets = <&gcc GCC_USB30_SEC_BCR>;
+
+			usb_2_dwc3: usb@8c00000 {
+				compatible = "snps,dwc3";
+				reg = <0 0x08c00000 0 0xe000>;
+				interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+				iommus = <&apps_smmu 0xa0 0x0>;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
+				phys = <&usb_2_hsphy>;
+				phy-names = "usb2-phy";
+				maximum-speed = "high-speed";
+			};
+		};
+
 		dc_noc: interconnect@90e0000 {
 			reg = <0 0x090e0000 0 0x5080>;
 			compatible = "qcom,sc7280-dc-noc";
@@ -1063,6 +1182,51 @@
 			qcom,bcm-voters = <&apps_bcm_voter>;
 		};
 
+		usb_1: usb@a6f8800 {
+			compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
+			reg = <0 0x0a6f8800 0 0x400>;
+			status = "disabled";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			dma-ranges;
+
+			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
+			clock-names = "cfg_noc", "core", "iface", "mock_utmi",
+				      "sleep";
+
+			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <200000000>;
+
+			interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
+					  "dm_hs_phy_irq", "ss_phy_irq";
+
+			power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+
+			resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+			usb_1_dwc3: usb@a600000 {
+				compatible = "snps,dwc3";
+				reg = <0 0x0a600000 0 0xe000>;
+				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+				iommus = <&apps_smmu 0xe0 0x0>;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
+				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
+				phy-names = "usb2-phy", "usb3-phy";
+				maximum-speed = "super-speed";
+			};
+		};
+
 		videocc: clock-controller@aaf0000 {
 			compatible = "qcom,sc7280-videocc";
 			reg = <0 0xaaf0000 0 0x10000>;
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v5 2/3] arm64: dts: qcom: sc7280: Add USB related nodes

[Stephen Boyd]

Quoting Sandeep Maheswaram (2021-07-06 06:00:12)
> Add nodes for DWC3 USB controller, QMP and HS USB PHYs in sc7280 SOC.
>
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

Re: [PATCH v5 2/3] arm64: dts: qcom: sc7280: Add USB related nodes

[Stephen Boyd]

Quoting Sandeep Maheswaram (2021-07-06 06:00:12)
> Add nodes for DWC3 USB controller, QMP and HS USB PHYs in sc7280 SOC.
>
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
> ---
> Changed qmp usb phy to usb dp phy combo node as per Stephen's comments.
> Changed dwc to usb and added SC7280 compatible as per Bjorn's comments.
>
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 164 +++++++++++++++++++++++++++++++++++
>  1 file changed, 164 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index a8c274a..cd6908f 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1035,6 +1035,125 @@
>                         };
>                 };
>
[...]
> +
> +               usb_2: usb@8cf8800 {
> +                       compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
> +                       reg = <0 0x08cf8800 0 0x400>;
> +                       status = "disabled";
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +                       dma-ranges;
> +
> +                       clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
> +                                <&gcc GCC_USB30_SEC_MASTER_CLK>,
> +                                <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
> +                                <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
> +                                <&gcc GCC_USB30_SEC_SLEEP_CLK>;
> +                       clock-names = "cfg_noc", "core", "iface","mock_utmi",
> +                                     "sleep";
> +
> +                       assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
> +                                         <&gcc GCC_USB30_SEC_MASTER_CLK>;
> +                       assigned-clock-rates = <19200000>, <200000000>;
> +
> +                       interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <&pdc 13 IRQ_TYPE_EDGE_RISING>,
> +                                    <&pdc 12 IRQ_TYPE_EDGE_RISING>;

I'm seeing this cause a warning at boot

[    4.724756] irq: type mismatch, failed to map hwirq-12 for
interrupt-controller@b220000!
[    4.733401] irq: type mismatch, failed to map hwirq-13 for
interrupt-controller@b220000!

> +                       interrupt-names = "hs_phy_irq",
> +                                         "dm_hs_phy_irq", "dp_hs_phy_irq";
> +
> +                       power-domains = <&gcc GCC_USB30_SEC_GDSC>;
> +
> +                       resets = <&gcc GCC_USB30_SEC_BCR>;
> +
> +                       usb_2_dwc3: usb@8c00000 {
> +                               compatible = "snps,dwc3";
> +                               reg = <0 0x08c00000 0 0xe000>;
> +                               interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
> +                               iommus = <&apps_smmu 0xa0 0x0>;
> +                               snps,dis_u2_susphy_quirk;
> +                               snps,dis_enblslpm_quirk;
> +                               phys = <&usb_2_hsphy>;
> +                               phy-names = "usb2-phy";
> +                               maximum-speed = "high-speed";
> +                       };
> +               };
> +
>                 dc_noc: interconnect@90e0000 {
>                         reg = <0 0x090e0000 0 0x5080>;
>                         compatible = "qcom,sc7280-dc-noc";
> @@ -1063,6 +1182,51 @@
>                         qcom,bcm-voters = <&apps_bcm_voter>;
>                 };
>
> +               usb_1: usb@a6f8800 {
> +                       compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
> +                       reg = <0 0x0a6f8800 0 0x400>;
> +                       status = "disabled";
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +                       dma-ranges;
> +
> +                       clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> +                                <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> +                                <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> +                                <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> +                                <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
> +                       clock-names = "cfg_noc", "core", "iface", "mock_utmi",
> +                                     "sleep";
> +
> +                       assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> +                                         <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> +                       assigned-clock-rates = <19200000>, <200000000>;
> +
> +                       interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> +                                             <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
> +                                             <&pdc 15 IRQ_TYPE_EDGE_BOTH>,

And this one too.

[    4.898667] irq: type mismatch, failed to map hwirq-14 for
interrupt-controller@b220000!
[    4.907241] irq: type mismatch, failed to map hwirq-15 for
interrupt-controller@b220000!

which looks like genirq code is complaining that the type is different
than what it is configured for. Are these trigger flags correct? If so,
then there' some sort of bug in the pdc driver.

> +                                             <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
> +                                         "dm_hs_phy_irq", "ss_phy_irq";
> +
> +                       power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
> +
> +                       resets = <&gcc GCC_USB30_PRIM_BCR>;
> +
> +                       usb_1_dwc3: usb@a600000 {

Re: [PATCH v5 2/3] arm64: dts: qcom: sc7280: Add USB related nodes

[Sandeep Maheswaram]

Hi Stephen,

On 8/18/2021 1:28 AM, Stephen Boyd wrote:
> Quoting Sandeep Maheswaram (2021-07-06 06:00:12)
>> Add nodes for DWC3 USB controller, QMP and HS USB PHYs in sc7280 SOC.
>>
>> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
>> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
>> ---
>> Changed qmp usb phy to usb dp phy combo node as per Stephen's comments.
>> Changed dwc to usb and added SC7280 compatible as per Bjorn's comments.
>>
>>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 164 +++++++++++++++++++++++++++++++++++
>>   1 file changed, 164 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index a8c274a..cd6908f 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -1035,6 +1035,125 @@
>>                          };
>>                  };
>>
> [...]
>> +
>> +               usb_2: usb@8cf8800 {
>> +                       compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
>> +                       reg = <0 0x08cf8800 0 0x400>;
>> +                       status = "disabled";
>> +                       #address-cells = <2>;
>> +                       #size-cells = <2>;
>> +                       ranges;
>> +                       dma-ranges;
>> +
>> +                       clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
>> +                                <&gcc GCC_USB30_SEC_MASTER_CLK>,
>> +                                <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
>> +                                <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
>> +                                <&gcc GCC_USB30_SEC_SLEEP_CLK>;
>> +                       clock-names = "cfg_noc", "core", "iface","mock_utmi",
>> +                                     "sleep";
>> +
>> +                       assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
>> +                                         <&gcc GCC_USB30_SEC_MASTER_CLK>;
>> +                       assigned-clock-rates = <19200000>, <200000000>;
>> +
>> +                       interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
>> +                                    <&pdc 13 IRQ_TYPE_EDGE_RISING>,
>> +                                    <&pdc 12 IRQ_TYPE_EDGE_RISING>;
> I'm seeing this cause a warning at boot
>
> [    4.724756] irq: type mismatch, failed to map hwirq-12 for
> interrupt-controller@b220000!
> [    4.733401] irq: type mismatch, failed to map hwirq-13 for
> interrupt-controller@b220000!
I should be using  IRQ_TYPE_LEVEL_HIGH. Will correct in next version.
>> +                       interrupt-names = "hs_phy_irq",
>> +                                         "dm_hs_phy_irq", "dp_hs_phy_irq";
>> +
>> +                       power-domains = <&gcc GCC_USB30_SEC_GDSC>;
>> +
>> +                       resets = <&gcc GCC_USB30_SEC_BCR>;
>> +
>> +                       usb_2_dwc3: usb@8c00000 {
>> +                               compatible = "snps,dwc3";
>> +                               reg = <0 0x08c00000 0 0xe000>;
>> +                               interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
>> +                               iommus = <&apps_smmu 0xa0 0x0>;
>> +                               snps,dis_u2_susphy_quirk;
>> +                               snps,dis_enblslpm_quirk;
>> +                               phys = <&usb_2_hsphy>;
>> +                               phy-names = "usb2-phy";
>> +                               maximum-speed = "high-speed";
>> +                       };
>> +               };
>> +
>>                  dc_noc: interconnect@90e0000 {
>>                          reg = <0 0x090e0000 0 0x5080>;
>>                          compatible = "qcom,sc7280-dc-noc";
>> @@ -1063,6 +1182,51 @@
>>                          qcom,bcm-voters = <&apps_bcm_voter>;
>>                  };
>>
>> +               usb_1: usb@a6f8800 {
>> +                       compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
>> +                       reg = <0 0x0a6f8800 0 0x400>;
>> +                       status = "disabled";
>> +                       #address-cells = <2>;
>> +                       #size-cells = <2>;
>> +                       ranges;
>> +                       dma-ranges;
>> +
>> +                       clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
>> +                                <&gcc GCC_USB30_PRIM_MASTER_CLK>,
>> +                                <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
>> +                                <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> +                                <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
>> +                       clock-names = "cfg_noc", "core", "iface", "mock_utmi",
>> +                                     "sleep";
>> +
>> +                       assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> +                                         <&gcc GCC_USB30_PRIM_MASTER_CLK>;
>> +                       assigned-clock-rates = <19200000>, <200000000>;
>> +
>> +                       interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
>> +                                             <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
>> +                                             <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
> And this one too.
>
> [    4.898667] irq: type mismatch, failed to map hwirq-14 for
> interrupt-controller@b220000!
> [    4.907241] irq: type mismatch, failed to map hwirq-15 for
> interrupt-controller@b220000!
>
> which looks like genirq code is complaining that the type is different
> than what it is configured for. Are these trigger flags correct? If so,
> then there' some sort of bug in the pdc driver.

I should be using  IRQ_TYPE_LEVEL_HIGH. Will correct in next version.


>
>> +                                             <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
>> +                       interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
>> +                                         "dm_hs_phy_irq", "ss_phy_irq";
>> +
>> +                       power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
>> +
>> +                       resets = <&gcc GCC_USB30_PRIM_BCR>;
>> +
>> +                       usb_1_dwc3: usb@a600000 {

Re: [PATCH v5 2/3] arm64: dts: qcom: sc7280: Add USB related nodes

[Stephen Boyd]

Quoting Sandeep Maheswaram (2021-08-19 22:34:14)
> On 8/18/2021 1:28 AM, Stephen Boyd wrote:
> > Quoting Sandeep Maheswaram (2021-07-06 06:00:12)
> >> Add nodes for DWC3 USB controller, QMP and HS USB PHYs in sc7280 SOC.
> >>
> >> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> >> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
> >> ---
> >> Changed qmp usb phy to usb dp phy combo node as per Stephen's comments.
> >> Changed dwc to usb and added SC7280 compatible as per Bjorn's comments.
> >>
> >>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 164 +++++++++++++++++++++++++++++++++++
> >>   1 file changed, 164 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >> index a8c274a..cd6908f 100644
> >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >> @@ -1035,6 +1035,125 @@
> >>                          };
> >>                  };
> >>
> > [...]
> >> +
> >> +               usb_2: usb@8cf8800 {
> >> +                       compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
> >> +                       reg = <0 0x08cf8800 0 0x400>;
> >> +                       status = "disabled";
> >> +                       #address-cells = <2>;
> >> +                       #size-cells = <2>;
> >> +                       ranges;
> >> +                       dma-ranges;
> >> +
> >> +                       clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
> >> +                                <&gcc GCC_USB30_SEC_MASTER_CLK>,
> >> +                                <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
> >> +                                <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
> >> +                                <&gcc GCC_USB30_SEC_SLEEP_CLK>;
> >> +                       clock-names = "cfg_noc", "core", "iface","mock_utmi",
> >> +                                     "sleep";
> >> +
> >> +                       assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
> >> +                                         <&gcc GCC_USB30_SEC_MASTER_CLK>;
> >> +                       assigned-clock-rates = <19200000>, <200000000>;
> >> +
> >> +                       interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
> >> +                                    <&pdc 13 IRQ_TYPE_EDGE_RISING>,
> >> +                                    <&pdc 12 IRQ_TYPE_EDGE_RISING>;
> > I'm seeing this cause a warning at boot
> >
> > [    4.724756] irq: type mismatch, failed to map hwirq-12 for
> > interrupt-controller@b220000!
> > [    4.733401] irq: type mismatch, failed to map hwirq-13 for
> > interrupt-controller@b220000!
> I should be using  IRQ_TYPE_LEVEL_HIGH. Will correct in next version.

Ok. Please send a patch to fix it as this is already staged to be merged
in the next merge window.

[PATCH v5 3/3] arm64: dts: qcom: sc7280: Add USB nodes for IDP board

[Sandeep Maheswaram]

Add USB nodes for sc7280 IDP board.

Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
---
 arch/arm64/boot/dts/qcom/sc7280-idp.dts | 39 +++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index 3900cfc..44326d8 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -276,6 +276,45 @@
 	status = "okay";
 };
 
+&usb_1 {
+	status = "okay";
+};
+
+&usb_1_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_1_hsphy {
+	status = "okay";
+
+	vdda-pll-supply = <&vreg_l10c_0p8>;
+	vdda33-supply = <&vreg_l2b_3p0>;
+	vdda18-supply = <&vreg_l1c_1p8>;
+};
+
+&usb_1_qmpphy {
+	status = "okay";
+
+	vdda-phy-supply = <&vreg_l6b_1p2>;
+	vdda-pll-supply = <&vreg_l1b_0p8>;
+};
+
+&usb_2 {
+	status = "okay";
+};
+
+&usb_2_dwc3 {
+	dr_mode = "peripheral";
+};
+
+&usb_2_hsphy {
+	status = "okay";
+
+	vdda-pll-supply = <&vreg_l10c_0p8>;
+	vdda33-supply = <&vreg_l2b_3p0>;
+	vdda18-supply = <&vreg_l1c_1p8>;
+};
+
 /* PINCTRL - additions to nodes defined in sc7280.dtsi */
 
 &qup_uart5_default {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v5 3/3] arm64: dts: qcom: sc7280: Add USB nodes for IDP board

[Stephen Boyd]

Quoting Sandeep Maheswaram (2021-07-06 06:00:13)
> Add USB nodes for sc7280 IDP board.
>
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>