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From: Apurva Nandan <a-nandan@ti.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>,
	Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Mark Brown <broonie@kernel.org>,
	Patrice Chotard <patrice.chotard@foss.st.com>,
	Boris Brezillon <boris.brezillon@collabora.com>,
	<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<linux-spi@vger.kernel.org>
Cc: Apurva Nandan <a-nandan@ti.com>, Pratyush Yadav <p.yadav@ti.com>
Subject: [PATCH 01/13] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase
Date: Tue, 13 Jul 2021 13:05:26 +0000	[thread overview]
Message-ID: <20210713130538.646-2-a-nandan@ti.com> (raw)
In-Reply-To: <20210713130538.646-1-a-nandan@ti.com>

Setting dtr field of spi_mem_op is useful when creating templates
for DTR ops in spinand.h. Also, 2 bytes cmd phases are required when
operating in Octal DTR SPI mode.

Create new templates for dtr mode cmd, address, dummy and data phase
in spi_mem_op, which set the dtr field to 1 and also allow passing
the nbytes for the cmd phase.

Signed-off-by: Apurva Nandan <a-nandan@ti.com>
---
 include/linux/spi/spi-mem.h | 87 ++++++++++++++++++++++++++-----------
 1 file changed, 61 insertions(+), 26 deletions(-)

diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index 85e2ff7b840d..73e52a3ecf66 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -13,46 +13,81 @@
 
 #include <linux/spi/spi.h>
 
-#define SPI_MEM_OP_CMD(__opcode, __buswidth)			\
-	{							\
-		.buswidth = __buswidth,				\
-		.opcode = __opcode,				\
-		.nbytes = 1,					\
+#define SPI_MEM_OP_CMD_ALL_ARGS(__nbytes, __opcode, __buswidth, __dtr)	\
+	{								\
+		.buswidth = __buswidth,					\
+		.opcode = __opcode,					\
+		.nbytes = __nbytes,					\
+		.dtr = __dtr,						\
 	}
 
-#define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth)		\
-	{							\
-		.nbytes = __nbytes,				\
-		.val = __val,					\
-		.buswidth = __buswidth,				\
+#define SPI_MEM_OP_CMD(__opcode, __buswidth)				\
+	SPI_MEM_OP_CMD_ALL_ARGS(1, __opcode, __buswidth, 0)
+
+#define SPI_MEM_OP_CMD_DTR(__nbytes, __opcode, __buswidth)		\
+	SPI_MEM_OP_CMD_ALL_ARGS(__nbytes, __opcode, __buswidth, 1)
+
+#define SPI_MEM_OP_ADDR_ALL_ARGS(__nbytes, __val, __buswidth, __dtr)	\
+	{								\
+		.nbytes = __nbytes,					\
+		.val = __val,						\
+		.buswidth = __buswidth,					\
+		.dtr = __dtr,						\
 	}
 
+#define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth)			\
+	SPI_MEM_OP_ADDR_ALL_ARGS(__nbytes, __val, __buswidth, 0)
+
+#define SPI_MEM_OP_ADDR_DTR(__nbytes, __val, __buswidth)		\
+	SPI_MEM_OP_ADDR_ALL_ARGS(__nbytes, __val, __buswidth, 1)
+
 #define SPI_MEM_OP_NO_ADDR	{ }
 
-#define SPI_MEM_OP_DUMMY(__nbytes, __buswidth)			\
-	{							\
-		.nbytes = __nbytes,				\
-		.buswidth = __buswidth,				\
+#define SPI_MEM_OP_DUMMY_ALL_ARGS(__nbytes, __buswidth, __dtr)		\
+	{								\
+		.nbytes = __nbytes,					\
+		.buswidth = __buswidth,					\
+		.dtr = __dtr,						\
 	}
 
+#define SPI_MEM_OP_DUMMY(__nbytes, __buswidth)				\
+	SPI_MEM_OP_DUMMY_ALL_ARGS(__nbytes, __buswidth, 0)
+
+#define SPI_MEM_OP_DUMMY_DTR(__nbytes, __buswidth)			\
+	SPI_MEM_OP_DUMMY_ALL_ARGS(__nbytes, __buswidth, 1)
+
 #define SPI_MEM_OP_NO_DUMMY	{ }
 
-#define SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth)		\
-	{							\
-		.dir = SPI_MEM_DATA_IN,				\
-		.nbytes = __nbytes,				\
-		.buf.in = __buf,				\
-		.buswidth = __buswidth,				\
+#define SPI_MEM_OP_DATA_IN_ALL_ARGS(__nbytes, __buf, __buswidth, __dtr)	\
+	{								\
+		.dir = SPI_MEM_DATA_IN,					\
+		.nbytes = __nbytes,					\
+		.buf.in = __buf,					\
+		.buswidth = __buswidth,					\
+		.dtr = __dtr,						\
 	}
 
-#define SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth)	\
-	{							\
-		.dir = SPI_MEM_DATA_OUT,			\
-		.nbytes = __nbytes,				\
-		.buf.out = __buf,				\
-		.buswidth = __buswidth,				\
+#define SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth)			\
+	SPI_MEM_OP_DATA_IN_ALL_ARGS(__nbytes, __buf, __buswidth, 0)
+
+#define SPI_MEM_OP_DATA_IN_DTR(__nbytes, __buf, __buswidth)		\
+	SPI_MEM_OP_DATA_IN_ALL_ARGS(__nbytes, __buf, __buswidth, 1)
+
+#define SPI_MEM_OP_DATA_OUT_ALL_ARGS(__nbytes, __buf, __buswidth, __dtr)\
+	{								\
+		.dir = SPI_MEM_DATA_OUT,				\
+		.nbytes = __nbytes,					\
+		.buf.out = __buf,					\
+		.buswidth = __buswidth,					\
+		.dtr = __dtr,						\
 	}
 
+#define SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth)		\
+	SPI_MEM_OP_DATA_OUT_ALL_ARGS(__nbytes, __buf, __buswidth, 0)
+
+#define SPI_MEM_OP_DATA_OUT_DTR(__nbytes, __buf, __buswidth)		\
+	SPI_MEM_OP_DATA_OUT_ALL_ARGS(__nbytes, __buf, __buswidth, 1)
+
 #define SPI_MEM_OP_NO_DATA	{ }
 
 /**
-- 
2.17.1


  reply	other threads:[~2021-07-13 13:06 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-13 13:05 [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Apurva Nandan
2021-07-13 13:05 ` Apurva Nandan [this message]
2021-07-14 17:06   ` [PATCH 01/13] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Mark Brown
2021-08-23  7:57   ` Boris Brezillon
2021-07-13 13:05 ` [PATCH 02/13] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode Apurva Nandan
2021-07-13 13:05 ` [PATCH 03/13] mtd: spinand: Setup spi_mem_op for the SPI IO protocol using reg_proto Apurva Nandan
2021-08-06 18:30   ` Miquel Raynal
2021-08-20  9:52     ` Apurva Nandan
2021-08-20 12:08       ` Miquel Raynal
2021-08-23  7:11         ` Boris Brezillon
2021-08-23  7:24           ` Miquel Raynal
2021-07-13 13:05 ` [PATCH 04/13] mtd: spinand: Fix odd byte addr and data phase in read/write reg op and write VCR op for Octal DTR mode Apurva Nandan
2021-08-06 18:43   ` Miquel Raynal
2021-08-20 10:27     ` Apurva Nandan
2021-08-20 12:06       ` Miquel Raynal
2021-07-13 13:05 ` [PATCH 05/13] mtd: spinand: Add adjust_op() in manufacturer_ops to modify the ops for manufacturer specific changes Apurva Nandan
2021-07-13 13:05 ` [PATCH 06/13] mtd: spinand: Add macros for Octal DTR page read and write operations Apurva Nandan
2021-08-06 18:54   ` Miquel Raynal
2021-08-20 10:35     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 07/13] mtd: spinand: Allow enabling Octal DTR mode in the core Apurva Nandan
2021-08-06 18:58   ` Miquel Raynal
2021-08-20 10:41     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 08/13] mtd: spinand: Reject 8D-8D-8D op_templates if octal_dtr_enale() is missing in manufacturer_op Apurva Nandan
2021-08-06 19:01   ` Miquel Raynal
2021-08-20 11:26     ` Apurva Nandan
2021-08-20 12:14       ` Miquel Raynal
2021-08-20 13:54         ` Apurva Nandan
2021-08-20 14:38           ` Miquel Raynal
2021-08-20 15:53             ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 09/13] mtd: spinand: Add support for write volatile configuration register op Apurva Nandan
2021-08-06 19:05   ` Miquel Raynal
2021-08-20 11:30     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 10/13] mtd: spinand: Add octal_dtr_enable() for Winbond manufacturer_ops Apurva Nandan
2021-08-06 19:06   ` Miquel Raynal
2021-08-20 11:31     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 11/13] mtd: spinand: Add support for Power-on-Reset (PoR) instruction Apurva Nandan
2021-08-06 19:08   ` Miquel Raynal
2021-08-20 11:39     ` Apurva Nandan
2021-08-20 12:18       ` Miquel Raynal
2021-08-20 13:41         ` Apurva Nandan
2021-08-20 14:17           ` Miquel Raynal
2021-08-20 15:56             ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 12/13] mtd: spinand: Perform Power-on-Reset when runtime_pm suspend is issued Apurva Nandan
2021-08-06 19:12   ` Miquel Raynal
2021-08-20 11:45     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 13/13] mtd: spinand: Add support for Winbond W35N01JW SPI NAND flash Apurva Nandan
2021-08-06 19:14   ` Miquel Raynal
2021-08-20 11:51     ` Apurva Nandan
2021-08-20 12:02       ` Miquel Raynal
2021-08-20 13:14         ` Apurva Nandan
2021-07-20 16:53 ` [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Nandan, Apurva

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