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From: Apurva Nandan <a-nandan@ti.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>,
	Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Mark Brown <broonie@kernel.org>,
	Patrice Chotard <patrice.chotard@foss.st.com>,
	Boris Brezillon <boris.brezillon@collabora.com>,
	<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<linux-spi@vger.kernel.org>
Cc: Apurva Nandan <a-nandan@ti.com>, Pratyush Yadav <p.yadav@ti.com>
Subject: [PATCH 03/13] mtd: spinand: Setup spi_mem_op for the SPI IO protocol using reg_proto
Date: Tue, 13 Jul 2021 13:05:28 +0000	[thread overview]
Message-ID: <20210713130538.646-4-a-nandan@ti.com> (raw)
In-Reply-To: <20210713130538.646-1-a-nandan@ti.com>

Currently, the op macros in spinand.h don't give the option to setup
any non-array access instructions for Dual/Quad/Octal DTR SPI bus.
Having a function that setups the op based on reg_proto would be
better than trying to write all the setup logic in op macros.

Create a spimem_setup_op() that would setup cmd, addr, dummy and data
phase of the spi_mem op, for the given spinand->reg_proto. And hence,
call the spimem_setup_op() before executing any spi_mem op.

Note: In this commit, spimem_setup_op() isn't called in the
read_reg_op(), write_reg_op() and wait() functions, as they need
modifications in address value and data nbytes when in Octal DTR mode.
This will be fixed in a later commit.

Signed-off-by: Apurva Nandan <a-nandan@ti.com>
---
 drivers/mtd/nand/spi/core.c | 51 +++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index a4f25649e293..2e59faecc8f5 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -20,6 +20,51 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/spi-mem.h>
 
+/**
+ * spinand_setup_op() - Helper function to setup the spi_mem op based on the
+ *			spinand->reg_proto
+ * @spinand: the spinand device
+ * @op: the spi_mem op to setup
+ *
+ * Set up buswidth and dtr fields for cmd, addr, dummy and data phase. Also
+ * adjust cmd opcode and dummy nbytes. This function doesn't make any changes
+ * to addr val or data buf.
+ */
+static void spinand_setup_op(const struct spinand_device *spinand,
+			     struct spi_mem_op *op)
+{
+	u8 op_buswidth = SPINAND_PROTO_BUSWIDTH(spinand->reg_proto);
+	u8 op_is_dtr = SPINAND_PROTO_IS_DTR(spinand->reg_proto);
+
+	if (spinand->reg_proto == SPINAND_SINGLE_STR)
+		return;
+
+	op->cmd.buswidth = op_buswidth;
+	op->cmd.dtr = op_is_dtr;
+	if (spinand->reg_proto == SPINAND_OCTAL_DTR) {
+		op->cmd.opcode = (op->cmd.opcode << 8) | op->cmd.opcode;
+		op->cmd.nbytes = 2;
+	}
+
+	if (op->addr.nbytes) {
+		op->addr.buswidth = op_buswidth;
+		op->addr.dtr = op_is_dtr;
+	}
+
+	if (op->dummy.nbytes) {
+		op->dummy.buswidth = op_buswidth;
+		if (op_is_dtr) {
+			op->dummy.nbytes *= 2;
+			op->dummy.dtr = true;
+		}
+	}
+
+	if (op->data.nbytes) {
+		op->data.buswidth = op_buswidth;
+		op->data.dtr = op_is_dtr;
+	}
+}
+
 static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
 {
 	struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg,
@@ -341,6 +386,7 @@ static int spinand_write_enable_op(struct spinand_device *spinand)
 {
 	struct spi_mem_op op = SPINAND_WR_EN_DIS_OP(true);
 
+	spinand_setup_op(spinand, &op);
 	return spi_mem_exec_op(spinand->spimem, &op);
 }
 
@@ -351,6 +397,7 @@ static int spinand_load_page_op(struct spinand_device *spinand,
 	unsigned int row = nanddev_pos_to_row(nand, &req->pos);
 	struct spi_mem_op op = SPINAND_PAGE_READ_OP(row);
 
+	spinand_setup_op(spinand, &op);
 	return spi_mem_exec_op(spinand->spimem, &op);
 }
 
@@ -475,6 +522,7 @@ static int spinand_program_op(struct spinand_device *spinand,
 	unsigned int row = nanddev_pos_to_row(nand, &req->pos);
 	struct spi_mem_op op = SPINAND_PROG_EXEC_OP(row);
 
+	spinand_setup_op(spinand, &op);
 	return spi_mem_exec_op(spinand->spimem, &op);
 }
 
@@ -485,6 +533,7 @@ static int spinand_erase_op(struct spinand_device *spinand,
 	unsigned int row = nanddev_pos_to_row(nand, pos);
 	struct spi_mem_op op = SPINAND_BLK_ERASE_OP(row);
 
+	spinand_setup_op(spinand, &op);
 	return spi_mem_exec_op(spinand->spimem, &op);
 }
 
@@ -531,6 +580,7 @@ static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr,
 		naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN);
 	int ret;
 
+	spinand_setup_op(spinand, &op);
 	ret = spi_mem_exec_op(spinand->spimem, &op);
 	if (!ret)
 		memcpy(buf, spinand->scratchbuf, SPINAND_MAX_ID_LEN);
@@ -543,6 +593,7 @@ static int spinand_reset_op(struct spinand_device *spinand)
 	struct spi_mem_op op = SPINAND_RESET_OP;
 	int ret;
 
+	spinand_setup_op(spinand, &op);
 	ret = spi_mem_exec_op(spinand->spimem, &op);
 	if (ret)
 		return ret;
-- 
2.17.1


  parent reply	other threads:[~2021-07-13 13:06 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-13 13:05 [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Apurva Nandan
2021-07-13 13:05 ` [PATCH 01/13] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Apurva Nandan
2021-07-14 17:06   ` Mark Brown
2021-08-23  7:57   ` Boris Brezillon
2021-07-13 13:05 ` [PATCH 02/13] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode Apurva Nandan
2021-07-13 13:05 ` Apurva Nandan [this message]
2021-08-06 18:30   ` [PATCH 03/13] mtd: spinand: Setup spi_mem_op for the SPI IO protocol using reg_proto Miquel Raynal
2021-08-20  9:52     ` Apurva Nandan
2021-08-20 12:08       ` Miquel Raynal
2021-08-23  7:11         ` Boris Brezillon
2021-08-23  7:24           ` Miquel Raynal
2021-07-13 13:05 ` [PATCH 04/13] mtd: spinand: Fix odd byte addr and data phase in read/write reg op and write VCR op for Octal DTR mode Apurva Nandan
2021-08-06 18:43   ` Miquel Raynal
2021-08-20 10:27     ` Apurva Nandan
2021-08-20 12:06       ` Miquel Raynal
2021-07-13 13:05 ` [PATCH 05/13] mtd: spinand: Add adjust_op() in manufacturer_ops to modify the ops for manufacturer specific changes Apurva Nandan
2021-07-13 13:05 ` [PATCH 06/13] mtd: spinand: Add macros for Octal DTR page read and write operations Apurva Nandan
2021-08-06 18:54   ` Miquel Raynal
2021-08-20 10:35     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 07/13] mtd: spinand: Allow enabling Octal DTR mode in the core Apurva Nandan
2021-08-06 18:58   ` Miquel Raynal
2021-08-20 10:41     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 08/13] mtd: spinand: Reject 8D-8D-8D op_templates if octal_dtr_enale() is missing in manufacturer_op Apurva Nandan
2021-08-06 19:01   ` Miquel Raynal
2021-08-20 11:26     ` Apurva Nandan
2021-08-20 12:14       ` Miquel Raynal
2021-08-20 13:54         ` Apurva Nandan
2021-08-20 14:38           ` Miquel Raynal
2021-08-20 15:53             ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 09/13] mtd: spinand: Add support for write volatile configuration register op Apurva Nandan
2021-08-06 19:05   ` Miquel Raynal
2021-08-20 11:30     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 10/13] mtd: spinand: Add octal_dtr_enable() for Winbond manufacturer_ops Apurva Nandan
2021-08-06 19:06   ` Miquel Raynal
2021-08-20 11:31     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 11/13] mtd: spinand: Add support for Power-on-Reset (PoR) instruction Apurva Nandan
2021-08-06 19:08   ` Miquel Raynal
2021-08-20 11:39     ` Apurva Nandan
2021-08-20 12:18       ` Miquel Raynal
2021-08-20 13:41         ` Apurva Nandan
2021-08-20 14:17           ` Miquel Raynal
2021-08-20 15:56             ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 12/13] mtd: spinand: Perform Power-on-Reset when runtime_pm suspend is issued Apurva Nandan
2021-08-06 19:12   ` Miquel Raynal
2021-08-20 11:45     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 13/13] mtd: spinand: Add support for Winbond W35N01JW SPI NAND flash Apurva Nandan
2021-08-06 19:14   ` Miquel Raynal
2021-08-20 11:51     ` Apurva Nandan
2021-08-20 12:02       ` Miquel Raynal
2021-08-20 13:14         ` Apurva Nandan
2021-07-20 16:53 ` [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Nandan, Apurva

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