From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Heiko Stuebner <heiko@sntech.de>,
Elaine Zhang <zhangqing@rock-chips.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org
Cc: Michael Turquette <mturquette@baylibre.com>,
Liu Ying <victor.liu@nxp.com>
Subject: [PATCH v1 2/3] clk: fractional-divider: Introduce NO_PRESCALER flag
Date: Thu, 15 Jul 2021 15:07:51 +0300 [thread overview]
Message-ID: <20210715120752.29174-2-andriy.shevchenko@linux.intel.com> (raw)
In-Reply-To: <20210715120752.29174-1-andriy.shevchenko@linux.intel.com>
The newly introduced flag, when set, makes the flow to skip
the assumption that the caller will use an additional 2^scale
prescaler to get the desired clock rate.
Reported-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/clk/clk-fractional-divider.c | 2 +-
include/linux/clk-provider.h | 5 +++++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index 535d299af646..b2f9aae9f172 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -84,7 +84,7 @@ void clk_fractional_divider_general_approximation(struct clk_hw *hw,
* by (scale - fd->nwidth) bits.
*/
scale = fls_long(*parent_rate / rate - 1);
- if (scale > fd->nwidth)
+ if (scale > fd->nwidth && !(fd->flags & CLK_FRAC_DIVIDER_NO_PRESCALER))
rate <<= scale - fd->nwidth;
rational_best_approximation(rate, *parent_rate,
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index d83b829305c0..f74d0afe275f 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -1001,6 +1001,10 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
* CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
* used for the divider register. Setting this flag makes the register
* accesses big endian.
+ * CLK_FRAC_DIVIDER_NO_PRESCALER - By default the resulting rate may be shifted
+ * left by a few bits in case when the asked one is quite small to satisfy
+ * the desired range of denominator. If the caller wants to get the best
+ * rate without using an additional prescaler, this flag may be set.
*/
struct clk_fractional_divider {
struct clk_hw hw;
@@ -1022,6 +1026,7 @@ struct clk_fractional_divider {
#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
+#define CLK_FRAC_DIVIDER_NO_PRESCALER BIT(2)
extern const struct clk_ops clk_fractional_divider_ops;
struct clk *clk_register_fractional_divider(struct device *dev,
--
2.30.2
next prev parent reply other threads:[~2021-07-15 12:07 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-15 12:07 [PATCH v1 1/3] clk: fractional-divider: Export approximation algo to the CCF users Andy Shevchenko
2021-07-15 12:07 ` Andy Shevchenko [this message]
2021-07-16 2:43 ` [PATCH v1 2/3] clk: fractional-divider: Introduce NO_PRESCALER flag Liu Ying
2021-07-16 13:19 ` Andy Shevchenko
2021-07-19 3:16 ` Liu Ying
2021-07-19 12:09 ` Andy Shevchenko
2021-07-22 6:02 ` Liu Ying
2021-07-22 7:24 ` Andy Shevchenko
2021-07-22 9:08 ` Liu Ying
2021-07-22 9:34 ` Andy Shevchenko
2021-07-22 9:59 ` Liu Ying
2021-07-15 12:07 ` [PATCH v1 3/3] clk: fractional-divider: Document the arithmetics used behind the code Andy Shevchenko
2021-07-15 15:38 ` [PATCH v1 1/3] clk: fractional-divider: Export approximation algo to the CCF users kernel test robot
2021-07-15 16:51 ` Andy Shevchenko
2021-07-15 17:58 ` Robin Murphy
2021-07-16 13:09 ` Andy Shevchenko
2021-07-15 22:41 ` kernel test robot
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