From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>,
Rob Herring <robh+dt@kernel.org>,
Wolfgang Grandegger <wg@grandegger.com>,
Marc Kleine-Budde <mkl@pengutronix.de>,
"David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: linux-can@vger.kernel.org, netdev@vger.kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Prabhakar <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 3/6] dt-bindings: clk: r9a07g044-cpg: Add entry for P0_DIV2 core clock
Date: Thu, 15 Jul 2021 19:21:20 +0100 [thread overview]
Message-ID: <20210715182123.23372-4-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20210715182123.23372-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Add P0_DIV2 core clock required for CANFD module. CANFD core clock is
sourced from P0_DIV2 referenced from HW manual Rev.0.50.
Also add R9A07G044_LAST_CORE_CLK entry to avoid changes in
r9a07g044-cpg.c file.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
include/dt-bindings/clock/r9a07g044-cpg.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h
index 0728ad07ff7a..2fd20db0b2f4 100644
--- a/include/dt-bindings/clock/r9a07g044-cpg.h
+++ b/include/dt-bindings/clock/r9a07g044-cpg.h
@@ -30,6 +30,8 @@
#define R9A07G044_CLK_P2 19
#define R9A07G044_CLK_AT 20
#define R9A07G044_OSCCLK 21
+#define R9A07G044_CLK_P0_DIV2 22
+#define R9A07G044_LAST_CORE_CLK 23
/* R9A07G044 Module Clocks */
#define R9A07G044_CA55_SCLK 0
--
2.17.1
next prev parent reply other threads:[~2021-07-15 18:21 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-15 18:21 [PATCH 0/6] Renesas RZ/G2L CANFD support Lad Prabhakar
2021-07-15 18:21 ` [PATCH 1/6] dt-bindings: net: can: renesas,rcar-canfd: Document RZ/G2L SoC Lad Prabhakar
2021-07-16 7:38 ` Geert Uytterhoeven
2021-07-16 8:30 ` Lad, Prabhakar
2021-07-15 18:21 ` [PATCH 2/6] can: rcar_canfd: Add support for RZ/G2L family Lad Prabhakar
2021-07-16 7:47 ` Geert Uytterhoeven
2021-07-16 8:32 ` Lad, Prabhakar
2021-07-16 10:10 ` Marc Kleine-Budde
2021-07-15 18:21 ` Lad Prabhakar [this message]
2021-07-16 8:07 ` [PATCH 3/6] dt-bindings: clk: r9a07g044-cpg: Add entry for P0_DIV2 core clock Geert Uytterhoeven
2021-07-16 8:45 ` Lad, Prabhakar
2021-07-16 8:56 ` Geert Uytterhoeven
2021-07-16 9:02 ` Lad, Prabhakar
2021-07-15 18:21 ` [PATCH 4/6] clk: renesas: r9a07g044-cpg: Add entry for fixed clock P0_DIV2 Lad Prabhakar
2021-07-16 8:09 ` Geert Uytterhoeven
2021-07-16 8:46 ` Lad, Prabhakar
2021-07-15 18:21 ` [PATCH 5/6] clk: renesas: r9a07g044-cpg: Add clock and reset entries for CANFD Lad Prabhakar
2021-07-16 7:55 ` Geert Uytterhoeven
2021-07-15 18:21 ` [PATCH 6/6] arm64: dts: renesas: r9a07g044: Add CANFD node Lad Prabhakar
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