* [PATCH 1/4] arm64: dts: ti: k3-am64-main: Add epwm nodes
2021-07-19 8:53 [PATCH 0/4] arm64: dts: ti: k3-am64: Add PWM nodes Lokesh Vutla
@ 2021-07-19 8:53 ` Lokesh Vutla
2021-07-19 8:54 ` [PATCH 2/4] arm64: dts: ti: k3-am64-main: Add ecap pwm nodes Lokesh Vutla
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Lokesh Vutla @ 2021-07-19 8:53 UTC (permalink / raw)
To: Nishanth Menon, kristo
Cc: Device Tree Mailing List, Rob Herring, Linux ARM Mailing List,
linux-kernel, Lokesh Vutla
Add DT nodes for all epwm instances present in AM64 SoC.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 87 ++++++++++++++++++++++++
1 file changed, 87 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 02c3fdf9cc46..9e762f64b631 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -217,6 +217,12 @@ phy_gmii_sel: phy@4044 {
reg = <0x4044 0x8>;
#phy-cells = <1>;
};
+
+ epwm_tbclk: clock@4140 {
+ compatible = "ti,am64-epwm-tbclk", "syscon";
+ reg = <0x4130 0x4>;
+ #clock-cells = <1>;
+ };
};
main_uart0: serial@2800000 {
@@ -859,4 +865,85 @@ pcie0_ep: pcie-ep@f102000 {
clock-names = "fck";
max-functions = /bits/ 8 <1>;
};
+
+ epwm0: pwm@23000000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x23000000 0x0 0x100>;
+ power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ epwm1: pwm@23010000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x23010000 0x0 0x100>;
+ power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ epwm2: pwm@23020000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x23020000 0x0 0x100>;
+ power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ epwm3: pwm@23030000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x23030000 0x0 0x100>;
+ power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ epwm4: pwm@23040000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x23040000 0x0 0x100>;
+ power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ epwm5: pwm@23050000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x23050000 0x0 0x100>;
+ power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ epwm6: pwm@23060000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x23060000 0x0 0x100>;
+ power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ epwm7: pwm@23070000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x23070000 0x0 0x100>;
+ power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ epwm8: pwm@23080000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x23080000 0x0 0x100>;
+ power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>;
+ clock-names = "tbclk", "fck";
+ };
};
--
2.30.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 2/4] arm64: dts: ti: k3-am64-main: Add ecap pwm nodes
2021-07-19 8:53 [PATCH 0/4] arm64: dts: ti: k3-am64: Add PWM nodes Lokesh Vutla
2021-07-19 8:53 ` [PATCH 1/4] arm64: dts: ti: k3-am64-main: Add epwm nodes Lokesh Vutla
@ 2021-07-19 8:54 ` Lokesh Vutla
2021-07-19 8:54 ` [PATCH 3/4] arm64: dts: ti: k3-am642-sk: Add ecap0 node Lokesh Vutla
2021-07-19 8:54 ` [PATCH 4/4] arm64: dts: ti: k3-am642-evm: " Lokesh Vutla
3 siblings, 0 replies; 9+ messages in thread
From: Lokesh Vutla @ 2021-07-19 8:54 UTC (permalink / raw)
To: Nishanth Menon, kristo
Cc: Device Tree Mailing List, Rob Herring, Linux ARM Mailing List,
linux-kernel, Lokesh Vutla
There are 3 instances of ecap modules that are capable of generating
a pwm when configured in apwm mode. Add DT nodes for these 3 ecap
instances.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 27 ++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 9e762f64b631..42d1d219a3fd 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -946,4 +946,31 @@ epwm8: pwm@23080000 {
clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>;
clock-names = "tbclk", "fck";
};
+
+ ecap0: pwm@23100000 {
+ compatible = "ti,am64-ecap", "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x0 0x23100000 0x0 0x60>;
+ power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 51 0>;
+ clock-names = "fck";
+ };
+
+ ecap1: pwm@23110000 {
+ compatible = "ti,am64-ecap", "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x0 0x23110000 0x0 0x60>;
+ power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 52 0>;
+ clock-names = "fck";
+ };
+
+ ecap2: pwm@23120000 {
+ compatible = "ti,am64-ecap", "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x0 0x23120000 0x0 0x60>;
+ power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 53 0>;
+ clock-names = "fck";
+ };
};
--
2.30.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 3/4] arm64: dts: ti: k3-am642-sk: Add ecap0 node
2021-07-19 8:53 [PATCH 0/4] arm64: dts: ti: k3-am64: Add PWM nodes Lokesh Vutla
2021-07-19 8:53 ` [PATCH 1/4] arm64: dts: ti: k3-am64-main: Add epwm nodes Lokesh Vutla
2021-07-19 8:54 ` [PATCH 2/4] arm64: dts: ti: k3-am64-main: Add ecap pwm nodes Lokesh Vutla
@ 2021-07-19 8:54 ` Lokesh Vutla
2021-07-19 15:23 ` Nishanth Menon
2021-07-19 8:54 ` [PATCH 4/4] arm64: dts: ti: k3-am642-evm: " Lokesh Vutla
3 siblings, 1 reply; 9+ messages in thread
From: Lokesh Vutla @ 2021-07-19 8:54 UTC (permalink / raw)
To: Nishanth Menon, kristo
Cc: Device Tree Mailing List, Rob Herring, Linux ARM Mailing List,
linux-kernel, Lokesh Vutla
ecap0 can be configured to use pad ECAP0_IN_APWM_OUT (D18) which has a
signal connected to Pin 1 of J3. Add support for adding this pinmux so
that pwm can be observed on pin 1 of Header J3
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index d3aa2901e6fd..eb0d10e6e787 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -210,6 +210,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
>;
};
+
+ main_ecap0_pins_default: main-ecap0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
+ >;
+ };
};
&mcu_uart0 {
@@ -453,3 +459,9 @@ &pcie0_rc {
&pcie0_ep {
status = "disabled";
};
+
+&ecap0 {
+ /* PWM is available on Pin 1 of header J3 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_ecap0_pins_default>;
+};
--
2.30.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 3/4] arm64: dts: ti: k3-am642-sk: Add ecap0 node
2021-07-19 8:54 ` [PATCH 3/4] arm64: dts: ti: k3-am642-sk: Add ecap0 node Lokesh Vutla
@ 2021-07-19 15:23 ` Nishanth Menon
2021-07-20 5:16 ` Lokesh Vutla
0 siblings, 1 reply; 9+ messages in thread
From: Nishanth Menon @ 2021-07-19 15:23 UTC (permalink / raw)
To: Lokesh Vutla
Cc: kristo, Device Tree Mailing List, Rob Herring,
Linux ARM Mailing List, linux-kernel
On 14:24-20210719, Lokesh Vutla wrote:
> ecap0 can be configured to use pad ECAP0_IN_APWM_OUT (D18) which has a
> signal connected to Pin 1 of J3. Add support for adding this pinmux so
> that pwm can be observed on pin 1 of Header J3
>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> index d3aa2901e6fd..eb0d10e6e787 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> @@ -210,6 +210,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
> AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
> >;
> };
> +
> + main_ecap0_pins_default: main-ecap0-pins-default {
> + pinctrl-single,pins = <
> + AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
> + >;
> + };
> };
>
> &mcu_uart0 {
> @@ -453,3 +459,9 @@ &pcie0_rc {
> &pcie0_ep {
> status = "disabled";
> };
> +
> +&ecap0 {
> + /* PWM is available on Pin 1 of header J3 */
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_ecap0_pins_default>;
> +};
> --
> 2.30.0
>
Do the other ecap and pwm nodes need to be disabled since they may not
be pinned out?
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 3/4] arm64: dts: ti: k3-am642-sk: Add ecap0 node
2021-07-19 15:23 ` Nishanth Menon
@ 2021-07-20 5:16 ` Lokesh Vutla
2021-07-20 12:05 ` Nishanth Menon
0 siblings, 1 reply; 9+ messages in thread
From: Lokesh Vutla @ 2021-07-20 5:16 UTC (permalink / raw)
To: Nishanth Menon
Cc: kristo, Device Tree Mailing List, Rob Herring,
Linux ARM Mailing List, linux-kernel
On 19/07/21 8:53 pm, Nishanth Menon wrote:
> On 14:24-20210719, Lokesh Vutla wrote:
>> ecap0 can be configured to use pad ECAP0_IN_APWM_OUT (D18) which has a
>> signal connected to Pin 1 of J3. Add support for adding this pinmux so
>> that pwm can be observed on pin 1 of Header J3
>>
>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
>> ---
>> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 ++++++++++++
>> 1 file changed, 12 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
>> index d3aa2901e6fd..eb0d10e6e787 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
>> @@ -210,6 +210,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
>> AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
>> >;
>> };
>> +
>> + main_ecap0_pins_default: main-ecap0-pins-default {
>> + pinctrl-single,pins = <
>> + AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
>> + >;
>> + };
>> };
>>
>> &mcu_uart0 {
>> @@ -453,3 +459,9 @@ &pcie0_rc {
>> &pcie0_ep {
>> status = "disabled";
>> };
>> +
>> +&ecap0 {
>> + /* PWM is available on Pin 1 of header J3 */
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&main_ecap0_pins_default>;
>> +};
>> --
>> 2.30.0
>>
>
>
> Do the other ecap and pwm nodes need to be disabled since they may not
> be pinned out?
Sure, Ill mark other ecap and epwm nodes as disabled. After looking at
schematics, epwm4 and 5 is pinned out on RPI header. But the header will most
likely be used for other use-cases. Shall I mark epwm4 and epwm5 disabled as
well with a comment with this information?
Thanks and regards,
Lokesh
>
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 3/4] arm64: dts: ti: k3-am642-sk: Add ecap0 node
2021-07-20 5:16 ` Lokesh Vutla
@ 2021-07-20 12:05 ` Nishanth Menon
0 siblings, 0 replies; 9+ messages in thread
From: Nishanth Menon @ 2021-07-20 12:05 UTC (permalink / raw)
To: Lokesh Vutla
Cc: kristo, Device Tree Mailing List, Rob Herring,
Linux ARM Mailing List, linux-kernel
On 10:46-20210720, Lokesh Vutla wrote:
>
>
> On 19/07/21 8:53 pm, Nishanth Menon wrote:
> > On 14:24-20210719, Lokesh Vutla wrote:
> >> ecap0 can be configured to use pad ECAP0_IN_APWM_OUT (D18) which has a
> >> signal connected to Pin 1 of J3. Add support for adding this pinmux so
> >> that pwm can be observed on pin 1 of Header J3
> >>
> >> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> >> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> >> ---
> >> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 ++++++++++++
> >> 1 file changed, 12 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> >> index d3aa2901e6fd..eb0d10e6e787 100644
> >> --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> >> +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> >> @@ -210,6 +210,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
> >> AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
> >> >;
> >> };
> >> +
> >> + main_ecap0_pins_default: main-ecap0-pins-default {
> >> + pinctrl-single,pins = <
> >> + AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
> >> + >;
> >> + };
> >> };
> >>
> >> &mcu_uart0 {
> >> @@ -453,3 +459,9 @@ &pcie0_rc {
> >> &pcie0_ep {
> >> status = "disabled";
> >> };
> >> +
> >> +&ecap0 {
> >> + /* PWM is available on Pin 1 of header J3 */
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&main_ecap0_pins_default>;
> >> +};
> >> --
> >> 2.30.0
> >>
> >
> >
> > Do the other ecap and pwm nodes need to be disabled since they may not
> > be pinned out?
>
> Sure, Ill mark other ecap and epwm nodes as disabled. After looking at
> schematics, epwm4 and 5 is pinned out on RPI header. But the header will most
> likely be used for other use-cases. Shall I mark epwm4 and epwm5 disabled as
> well with a comment with this information?
Yes, please. Thanks.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 4/4] arm64: dts: ti: k3-am642-evm: Add ecap0 node
2021-07-19 8:53 [PATCH 0/4] arm64: dts: ti: k3-am64: Add PWM nodes Lokesh Vutla
` (2 preceding siblings ...)
2021-07-19 8:54 ` [PATCH 3/4] arm64: dts: ti: k3-am642-sk: Add ecap0 node Lokesh Vutla
@ 2021-07-19 8:54 ` Lokesh Vutla
2021-07-19 15:23 ` Nishanth Menon
3 siblings, 1 reply; 9+ messages in thread
From: Lokesh Vutla @ 2021-07-19 8:54 UTC (permalink / raw)
To: Nishanth Menon, kristo
Cc: Device Tree Mailing List, Rob Herring, Linux ARM Mailing List,
linux-kernel, Lokesh Vutla
ecap0 can be configured to use pad ECAP0_IN_APWM_OUT (D18) which has a
signal connected to Pin 1 of J12 on EVM. Add support for adding this
pinmux so that pwm can be observed on pin 1 of Header J12
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 030712221188..7da1238cb1d6 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -288,6 +288,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
>;
};
+
+ main_ecap0_pins_default: main-ecap0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
+ >;
+ };
};
&main_uart0 {
@@ -574,3 +580,9 @@ &pcie0_ep {
num-lanes = <1>;
status = "disabled";
};
+
+&ecap0 {
+ /* PWM is available on Pin 1 of header J12 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_ecap0_pins_default>;
+};
--
2.30.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 4/4] arm64: dts: ti: k3-am642-evm: Add ecap0 node
2021-07-19 8:54 ` [PATCH 4/4] arm64: dts: ti: k3-am642-evm: " Lokesh Vutla
@ 2021-07-19 15:23 ` Nishanth Menon
0 siblings, 0 replies; 9+ messages in thread
From: Nishanth Menon @ 2021-07-19 15:23 UTC (permalink / raw)
To: Lokesh Vutla
Cc: kristo, Device Tree Mailing List, Rob Herring,
Linux ARM Mailing List, linux-kernel
On 14:24-20210719, Lokesh Vutla wrote:
> ecap0 can be configured to use pad ECAP0_IN_APWM_OUT (D18) which has a
> signal connected to Pin 1 of J12 on EVM. Add support for adding this
> pinmux so that pwm can be observed on pin 1 of Header J12
>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-am642-evm.dts | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> index 030712221188..7da1238cb1d6 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> @@ -288,6 +288,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
> AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
> >;
> };
> +
> + main_ecap0_pins_default: main-ecap0-pins-default {
> + pinctrl-single,pins = <
> + AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
> + >;
> + };
> };
>
> &main_uart0 {
> @@ -574,3 +580,9 @@ &pcie0_ep {
> num-lanes = <1>;
> status = "disabled";
> };
> +
> +&ecap0 {
> + /* PWM is available on Pin 1 of header J12 */
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_ecap0_pins_default>;
> +};
> --
> 2.30.0
>
Do the other ecap and pwm nodes need to be disabled since they may not
be pinned out?
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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