From: Zhu Lingshan <lingshan.zhu@intel.com>
To: peterz@infradead.org, pbonzini@redhat.com
Cc: bp@alien8.de, seanjc@google.com, vkuznets@redhat.com,
wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org,
kan.liang@linux.intel.com, ak@linux.intel.com,
wei.w.wang@intel.com, eranian@google.com,
liuxiangdong5@huawei.com, linux-kernel@vger.kernel.org,
x86@kernel.org, kvm@vger.kernel.org, like.xu.linux@gmail.com,
boris.ostrvsky@oracle.com, Zhu Lingshan <lingshan.zhu@intel.com>
Subject: [PATCH V9 07/18] x86/perf/core: Add pebs_capable to store valid PEBS_COUNTER_MASK value
Date: Thu, 22 Jul 2021 13:41:48 +0800 [thread overview]
Message-ID: <20210722054159.4459-8-lingshan.zhu@intel.com> (raw)
In-Reply-To: <20210722054159.4459-1-lingshan.zhu@intel.com>
From: "Peter Zijlstra (Intel)" <peterz@infradead.org>
The value of pebs_counter_mask will be accessed frequently
for repeated use in the intel_guest_get_msrs(). So it can be
optimized instead of endlessly mucking about with branches.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Zhu Lingshan <lingshan.zhu@intel.com>
---
arch/x86/events/intel/core.c | 14 ++++++--------
arch/x86/events/perf_event.h | 1 +
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index e52d73348343..c97e00083d10 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2867,10 +2867,7 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status)
* counters from the GLOBAL_STATUS mask and we always process PEBS
* events via drain_pebs().
*/
- if (x86_pmu.flags & PMU_FL_PEBS_ALL)
- status &= ~cpuc->pebs_enabled;
- else
- status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
+ status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
/*
* PEBS overflow sets bit 62 in the global status register
@@ -3908,10 +3905,7 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
arr[0].host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
arr[0].guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask;
- if (x86_pmu.flags & PMU_FL_PEBS_ALL)
- arr[0].guest &= ~cpuc->pebs_enabled;
- else
- arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
+ arr[0].guest &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
*nr = 1;
if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) {
@@ -5594,6 +5588,7 @@ __init int intel_pmu_init(void)
x86_pmu.events_mask_len = eax.split.mask_length;
x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
+ x86_pmu.pebs_capable = PEBS_COUNTER_MASK;
/*
* Quirk: v2 perfmon does not report fixed-purpose events, so
@@ -5778,6 +5773,7 @@ __init int intel_pmu_init(void)
x86_pmu.pebs_aliases = NULL;
x86_pmu.pebs_prec_dist = true;
x86_pmu.lbr_pt_coexist = true;
+ x86_pmu.pebs_capable = ~0ULL;
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
x86_pmu.flags |= PMU_FL_PEBS_ALL;
x86_pmu.get_event_constraints = glp_get_event_constraints;
@@ -6135,6 +6131,7 @@ __init int intel_pmu_init(void)
x86_pmu.pebs_aliases = NULL;
x86_pmu.pebs_prec_dist = true;
x86_pmu.pebs_block = true;
+ x86_pmu.pebs_capable = ~0ULL;
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
x86_pmu.flags |= PMU_FL_PEBS_ALL;
@@ -6178,6 +6175,7 @@ __init int intel_pmu_init(void)
x86_pmu.pebs_aliases = NULL;
x86_pmu.pebs_prec_dist = true;
x86_pmu.pebs_block = true;
+ x86_pmu.pebs_capable = ~0ULL;
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
x86_pmu.flags |= PMU_FL_PEBS_ALL;
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 1518f2754842..35d0a7ec5f20 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -807,6 +807,7 @@ struct x86_pmu {
void (*pebs_aliases)(struct perf_event *event);
unsigned long large_pebs_flags;
u64 rtm_abort_event;
+ u64 pebs_capable;
/*
* Intel LBR
--
2.27.0
next prev parent reply other threads:[~2021-07-22 5:43 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-22 5:41 [PATCH V9 00/18] KVM: x86/pmu: Add *basic* support to enable guest PEBS via DS Zhu Lingshan
2021-07-22 5:41 ` [PATCH V9 01/18] perf/core: Use static_call to optimize perf_guest_info_callbacks Zhu Lingshan
2021-07-22 5:41 ` [PATCH V9 02/18] perf/x86/intel: Add EPT-Friendly PEBS for Ice Lake Server Zhu Lingshan
2021-07-22 5:41 ` [PATCH V9 03/18] perf/x86/intel: Handle guest PEBS overflow PMI for KVM guest Zhu Lingshan
2021-08-05 1:15 ` Liuxiangdong
2021-08-06 12:23 ` Zhu, Lingshan
2021-07-22 5:41 ` [PATCH V9 04/18] perf/x86/core: Pass "struct kvm_pmu *" to determine the guest values Zhu Lingshan
2021-07-22 5:41 ` [PATCH V9 05/18] KVM: x86/pmu: Set MSR_IA32_MISC_ENABLE_EMON bit when vPMU is enabled Zhu Lingshan
2021-07-22 5:41 ` [PATCH V9 06/18] KVM: x86/pmu: Introduce the ctrl_mask value for fixed counter Zhu Lingshan
2021-07-22 5:41 ` Zhu Lingshan [this message]
2021-07-22 5:41 ` [PATCH V9 08/18] KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for extended PEBS Zhu Lingshan
2021-07-22 5:41 ` [PATCH V9 09/18] KVM: x86/pmu: Reprogram PEBS event to emulate guest PEBS counter Zhu Lingshan
2021-07-22 5:41 ` [PATCH V9 10/18] KVM: x86/pmu: Adjust precise_ip to emulate Ice Lake guest PDIR counter Zhu Lingshan
2021-07-22 5:41 ` [PATCH V9 11/18] KVM: x86/pmu: Add IA32_DS_AREA MSR emulation to support guest DS Zhu Lingshan
2021-07-22 5:41 ` [PATCH V9 12/18] KVM: x86/pmu: Add PEBS_DATA_CFG MSR emulation to support adaptive PEBS Zhu Lingshan
2021-07-22 5:41 ` [PATCH V9 13/18] KVM: x86: Set PEBS_UNAVAIL in IA32_MISC_ENABLE when PEBS is enabled Zhu Lingshan
2021-07-22 5:41 ` [PATCH V9 14/18] KVM: x86/pmu: Move pmc_speculative_in_use() to arch/x86/kvm/pmu.h Zhu Lingshan
2021-07-22 5:41 ` [PATCH V9 15/18] KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations Zhu Lingshan
2021-07-22 5:41 ` [PATCH V9 16/18] KVM: x86/pmu: Add kvm_pmu_cap to optimize perf_get_x86_pmu_capability Zhu Lingshan
2021-07-30 9:36 ` Zhu Lingshan
2021-07-22 5:41 ` [PATCH V9 17/18] KVM: x86/cpuid: Refactor host/guest CPU model consistency check Zhu Lingshan
2021-07-22 5:41 ` [PATCH V9 18/18] KVM: x86/pmu: Expose CPUIDs feature bits PDCM, DS, DTES64 Zhu Lingshan
2021-07-28 15:45 ` [PATCH V9 00/18] KVM: x86/pmu: Add *basic* support to enable guest PEBS via DS Peter Zijlstra
2021-07-28 16:40 ` Like Xu
2021-08-04 3:03 ` Zhu, Lingshan
2021-08-12 13:20 ` [PING][PATCH " Like Xu
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